Abstract: A home system includes a server having a first wireless communication port, and a plurality of devices, such as sensors. Each one of the devices includes a corresponding second wireless communication port. One or more of the devices is a timer/reminder sensor device associated with an object of interest. The timer/reminder sensor device includes a timer mechanism having a time input and an output. The timer mechanism is associated with the object and is adapted to input a time interval from the time input, time for the time interval and then responsively output to the output. The timer mechanism communicates the time input and the output of the timer mechanism between the second wireless communication port of the timer/reminder sensor device and the first wireless communication port of the server.

Abstract: A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.

Abstract: A method provides early estimation of product life using accelerated stress testing data. In an embodiment, data measured from a product operating in a first, high-stress environment is used to predict how long the product will operate in a second, normal operating environment before failure using a quadratic acceleration model. An additional feature of the present invention provides a quantified indication of how much the product has improved from a redesign.

Abstract: There is provided a timing generator that outputs a second periodic signal having a desired phase difference to a first periodic signal by superimposing a voltage on a control voltage of a voltage-controlled oscillating unit of a PLL circuit for generating the second periodic signal. The timing generator includes an initializing unit for measuring a timing shift gain indicative of a ratio of a timing shift amount to a change of a superimposed voltage and a voltage generating unit for generating the superimposed voltage based on the desired phase difference and the timing shift gain.

Abstract: A system and method provide Time-of-Use (TOU) rate schedules that are bound by windows of time, i.e., a type of fuzzy switch time, which is bounded on both sides, rather than instantaneous switch times. The fuzzy TOU schedule defines the time of a tier switch as the end time of the first completed interval recorded after the start of some window of time. A monitoring system may be included that implements configurable usage filters that allow for the classification of usage in terms of interval data. Usage filters can be defined so that they are applied against individual interval readings, various aggregations of interval readings, and/or the statistical products of interval readings, etc. A filtering algorithm allows for the comparison of incoming and/or historical interval data against defined usage and schedule filters to determine if usage is abnormal and should be investigated further.

Abstract: A performance monitor includes at least one Monitor Mode Control Register (MMCR) and plural Performance Control Monitors (PMCs). Each PMC is controlled by the MMCR to pair or group the PMCs so that the overflow from one PMC can be directed to its pair/group. By coupling the PMCs so that overflow from one can be directed to another, the effective size of the counters can be increased.

Abstract: A performance monitor includes at least one Monitor Mode Control Register (MMCR) and plural Performance Control Monitors (PMCs). Each PMC is controlled by the MMCR to pair or group the PMCs so that the overflow from one PMC can be directed to its pair/group. By coupling the PMCs so that overflow from one can be directed to another, the effective size of the counters can be increased.

Abstract: A method and apparatus for estimating the changing frequency of a signal received by a satellite receiver from, illustratively, positioning system satellites is disclosed that enables a more accurate measurement of the change in frequency of that signal due to movement of the satellite receiver relative to those satellites. The system includes a PLL having a numerically controlled oscillator (NCO) and a filter of frequency estimates (FFE). In operation, an analog signal is received at the satellite receiver and the PLL tracks the changing signal frequency and outputs non-smoothed frequency estimates into the FFE. The FFE then smoothes noise in the signal to produce a more accurate smoothed frequency estimate of the input signal. Comparing multiple estimates over time allows Doppler shift of the signal frequency received by the satellite receiver to be calculated more precisely, thus resulting in more accurate satellite receiver velocity vector determinations and, hence, position measurements.

Abstract: A variable persistence waveform database is generated by defining a First-In-First-Out (FIFO) time-ordered queue buffer for maintaining a selected number of waveform records. Digital data samples of a measurement signal are acquired and stored in a plurality of waveform records in the FIFO time-ordered queue buffer. Counts of the digital data samples for the plurality of waveform records are accumulated in a waveform database. Upon filling FIFO time-ordered queue buffer with waveform records, the digital data samples of the oldest acquired waveform record are subtracted from the accumulated counts of the waveform database and deleted from the FIFO time-ordered queue buffer and the digital data samples of the newest acquired waveform record are stored in the FIFO time-ordered queue buffer and added to the accumulated counts in the waveform database.

Abstract: In one embodiment, an apparatus comprises a mount, a housing, and a sensor. The mount is adapted to be disposed at least partially underneath a shoelace of a shoe. The housing is configured and arranged to be placed in at least first and second states in relation to the mount, wherein in the first state the housing is movable with respect to the mount and in the second state the housing is immovable with respect to the mount. There is a tongue on one of the mount and the housing and a groove on the other of the mount and the housing, the tongue being adapted to engage the groove when the housing is in the second state in relation to the mount and to disengage the groove then the housing is in the first state with respect to the mount. The sensor, which senses motion of the shoe, is disposed within the housing such that the sensor remains disposed within the housing when the housing is placed in the first state in relation to the mount and the housing is moved with respect to the mount.

Abstract: There is provided a delay amount measuring method of measuring a delay amount in an electronic device that outputs an output signal according to an input signal. The method includes a conversion step of converting the input signal and the output signal into digital data, a shift step of sequentially shifting the digital data of either of the input signal or the output signal in a time direction, an error computing step of computing a squared error of the digital data of the input signal and the digital data of the output signal with respect to each shift amount in the shift step, and a delay amount computing step of computing the shift amount when the squared error is a minimum value by means of a nonlinear least squares method and using the computed shift amount as the delay amount in the electronic device.

Abstract: An interpolation circuit (10) generates a plurality of intermediate amplitude values linearly related to two consecutive signal amplitude values using a system of adders and memory elements. A first stage (64) of the interpolation circuit calculates a one-half amplitude value; a second stage (66) calculates one-fourth and three-fourths amplitude values, and a third stage (68) calculates one-eighth, three-eighths, five-eighths, and seven-eighths amplitude values. A comparator (14) receives a threshold value (32) and compares each of the intermediate amplitude values to the threshold value. A decoder (16) generates a time of arrival adjustment value that is subtracted from a low resolution time of arrival to generate a high resolution time of arrival.

Abstract: Performing delay measurement between master and slave devices. The master transmits a delay measuring signal at a fixed timing relative to a synchronous pattern signal in an overhead and transmits a frame signal in which an internal delay time, associated with a frame signal generation, from a delay measurement start timing to a transmission timing of the delay measuring signal is stored in the delay measuring signal as a master offset value. The slave adds an internal delay time associated with a frame signal generation to the master offset value of the frame signal, making a slave offset value and transmits an updated delay measuring signal with the slave offset value. The master calculates a delay time by subtracting the slave offset value from a time difference between a timing at which the delay measuring signal transmitted from the slave is received and the delay measurement start timing.

Abstract: An automated system and method for conducting a usability test. The system conducts the usability test and records events that occur on the computer screen in sync with both the video and audio of the user and creates a complete chronicle of events that occur behind the scenes in the applications and the operating system. The system, depending upon the settings specified in the configuration, also captures other input streams and then saves the complete recording of the usability test, along with all the desired events and captures, in a file format. The system allows a remote viewer to observe, in real time, the recording of the usability test and to set markers at critical moments during the recording which are to be recorded. The system also allows the manager or administrator to configure the preferences, import and analyze the usability test and recording files, and prepare presentation videos of the usability test based upon the analyzed criteria.

Abstract: The invention relates to a device that is used to analyse the structure of a material. The inventive device comprises: probe elements (5) which are used to (i) emit a wave, in the material, with emission delay laws that correspond to several simultaneous deviations and (ii) receive, on the different probe elements (5), signals from the refraction of said wave by the material; detection channels, each detection channel being connected to a probe element (5), in order to collect the refraction signals and to transmit same to data processing means (4); and delay circuits that apply a delay on each detection channel according to the reception delay laws which are predetermined and which correspond to the different deviations of the wave emitted. The invention also relates to an analysis method which can be used, in particular, on said device.

Abstract: A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay line very robust pattern fault coverage. The XOR gate may consist of three current limiting inverters. A reference voltage generator generates constant voltages between a source voltage, bias voltages, and ground. These constant voltages decide the amount of current through the current limiting inverters. Selecting a different set of reference voltages programs a different current flowing in the current limiting inverters. This programmable current causes a programmable unit delay to be introduced by each XOR gate delay element.

Abstract: A structure having a parameter storing unit which stores a parameter to be used when a numeric control apparatus drives and controls the numeric control machine tool, a program interpretation unit which reads a part program to generate machining data for each block, an interpolation unit which interpolates a movement path instructed in an axis moving instruction referring to a parameter stored in the parameter storing unit and using an interpolation algorithm which is identical to a driving and controlling interpolation algorithm of the numeric control apparatus, an interpolation count counting unit which counts an interpolation count in the movement path, and an axis moving time calculating unit which multiplies an interpolation cycle when the numeric control apparatus drives and controls the numeric control machine tool and the counted interpolation count to calculate an axis moving time.

Abstract: A measuring device (1) has, e.g., a voice input portion (27) for a measurer to input an arbitrary comment at a time of measurement, and it allows a voice recognition portion (28) to recognize the measurer's comment inputted by the voice input portion (27) and also allows a recognition result to be stored in a comment storing portion (43) in correlation with information on date and time, thereby storing conditions or the like of the measurer at the time of measurement, together with the measurement data.

Abstract: A control system includes controllers that are coupled mutually by a communications network, on which information, transmitted from a master controller to a slave controller, is used to make timing corrections on the slave controller in order to synchronize event timers on the slave controller with that of the master controller. Timing accuracy for the occurrence of the event commanded by each controller is synchronized in narrow range of time, preferably within a few milliseconds depending on the specific application and system.

Abstract: The invention concerns a method to evaluate whether a statistical time delay (TD) between a first event and a second event of a device under test is better than a test limit (TL). The method includes the steps: performing a minimum number N of tests and evaluating the time delay (TD) from each test; modeling a first probability distribution (P1) of the evaluated time delays (TD); obtaining a second probability distribution (P2) of the evaluated time delays (TD); performing a statistical transformation in order to obtain a third probability distribution (P3) of the evaluated time delays (TD); and deciding to pass the device under test, if a certain percentage of the area of the third probability distribution (P3) is on a good side (GS) of the test limit (TL2).

Abstract: The invention concerns a method for filtering signals (Vin) generated by a piezo-electric type accelerometer in response to detection of a shock applied to an object to which the accelerometer is connected, this method characterised in that it ensures, during a particular step, that the signal (Vin) generated by the accelerometer, after having increased and exceeded a first threshold value (VTH,ON) decreases and becomes lower than a second threshold value (VTH,OFF) lower than the first threshold value (VTH,ON) after a period of time (TP,ON) greater than a minimum period of time (TP,ON,MIN) and less than a maximum period of time (TP,ON,MAX). The invention also concerns a device for filtering signals generated by an accelerometer in response to detection of a shock applied to an object connected to the accelerometer. Finally, the invention concerns a portable object such as a wristwatch including a detection device of this kind.

Abstract: System and method for reporting invalid parameter values for a system. An invalid value of a parameter is detected, and information related to the detection determined, including one or more valid values for the parameter, and optionally, an identifier (ID) of the parameter, the invalid value of the parameter, and/or contextual information related to the detection, e.g., a function ID and/or device ID indicating where the detection occurred, an error ID corresponding to the detection, a time value indicating when the detection occurred, and/or a text description of the error and/or parameter. The detection of the invalid value of the parameter is reported, optionally including some or all of the determined information, and the valid values for the parameter displayed. Input, e.g., user input, may optionally be received specifying a new valid value for the parameter, and the parameter set to the specified value.

Abstract: An object of the invention is to minimize the number of in-process items. To this end, in an inter-process buffer controlling apparatus according to the invention, the size of a buffer to be used for storage of work subjects of predetermined work is increased if a difference or a ratio between a variance of first intervals at which the work subjects are delivered to the buffer and a variance of duration that is taken for the preceding process exceeds a prescribed first threshold value, and the size of the buffer is decreased if a difference or a ratio between an average of second intervals at which work subjects generated by the work are delivered to the following buffer and an average of the first intervals exceeds a prescribed second threshold value.

Abstract: A sampling circuit for testing an integrated circuit receives several signals from points of interest in the integrated circuit, digitizes them, and determines whether the digitized signal is above or below a threshold. By sampling the signal at different phases of a system clock signal, a determination can be made of when during the system clock signal the signal at a point of interest changed state. Circuits are provided for making minimal impact on the circuit being observed. Circuits are also provided for clocking the observed signal so that it can be compared to other observed signals.

Abstract: Collected trial data is weighted to, for example, reflect the relevance of the data. A weighted confidence interval determination and application process described herein determines a confidence interval used to interpret the data. The confidence interval is derived by adjusting the sample size N to account for the impact of weighting when determining confidence intervals. The sample size N is adjusted in a downward trend to avoid overestimating the confidence interval. Lower and upper bounds of the confidence interval are determined using weight influenced variables. Thus, interpretation of weighted trial data, such as product demand data, can be achieved and acted upon with an accurate estimation of risk.

Abstract: A method and apparatus for establishing an average test time (TA) include determining a first time interval (TG) nominally associated with non-failing testing of a unit under test (UUT), and determining a second time interval (TPR) nominally associated with troubleshooting and repairing a failed unit under test. Additionally, a percent yield (Y) nominally associated with a proportion of non-failing units under test is determined. The average test time is a sum of the first time interval associated with the non-failing testing of the UUT, and a ratio of the second time interval associated with troubleshooting and repair of a failed UUT with respect to the yield.

Abstract: A method for producing a computer-assisted real-time system that includes at least one processing unit. Data exchange between the processing unit and the environment or one or more additional processing units is synchronous or asynchronous. At least one real clock is allocated to the processing unit to correlate data exchange.

Abstract: A time measurement circuit includes N time stamping units that each includes a dual sinusoid interpolator for achieving high timing resolution. The time measurement circuit is capable of time stamping input signals at a high re-trigger rate, and is thus well suited for quickly measuring the timing jitter of test signals in automatic test systems.

Abstract: Apparatus and method support the synchronization and calibration of a plurality of clocks in a medical device system that may provide treatment to a patient with a nervous system disorder. The plurality of clocks, which may be located at different components of the medical device system, includes a first clock and a second clock. The second clock may be synchronized to a first clock by disabling a run mode operation and setting the second clock to a selected time. When a reference time of the first clock approximately equals the selected time, the second clock enables the run mode operation. Additionally, a drift time that is indicative of a time difference between the first clock and the second clock is determined. If the drift time is greater than a predetermined amount, an indication to resynchronize the first and second clocks is provided.

Abstract: An integrated circuit is provided with multiple data processing components associated with respective sources which generate trace data streams. A reference timestamp generator is provided and the trace data streams are annotated such that they are output off-chip together with reference timestamp data. Outputting the reference timestamp data together with the trace data streams enables temporal correlation between points in different trace data streams by trace analysis tools.

Abstract: A computerized machine control (CMC) diagnostic system communicates with a computerized machine controller that utilizes a control program to control the operation of a machine through the use of a plurality of digital channels. In general terms, the system includes a data acquisition component, a data storage component and a viewing component. The data acquisition component queries and acquires time-based transition data about the plurality of digital channels. The data storage component stores the acquired transition data in order to establish an historical pattern of the transition data that can be compared to currently acquired transition data. The historical pattern of transition data is established independently of the control program. Upon comparison of the current transition data to the expected, historical pattern of transition data, a determination about the operational status of the machine being controlled can be made. The operational status can then be displayed on the viewing component.

Abstract: The invention relates to a method for monitoring at least one measuring signal, in particular for use in automation technology, production automation and process automation. Said method automatically determines and establishes an optimal time interval between measuring periods, by means of the course of a measuring signal. According to the invention, a computer system cyclically determines a characteristic value of the measuring signal in measuring periods, which are separated by a time interval, whereby a priority is automatically defined, said priority is assigned to the measuring signal and the time interval between the measuring periods is defined in accordance with the priority.

Abstract: System and method for maintenance and examination of timers for a computer system having connections in a networking system. Timer values in a connection table each indicate a timeout for a timer for a connection, where each connection has multiple timers, and one of the timer values is written to a global timer array for each connection such that the global timer array can be scanned to determine when timeouts occur for active connections. Sparse restart of a timer includes restarting the timer if data is communicated with a connected computer before the timeout occurs and after a predetermined time interval after timer start, and not restarting the timer if data is communicated before the timeout occurs and within the predetermined interval after timer start.

Abstract: A bus interface connects a device to a bus that connects a plurality of devices to one another. The bus interface described is distinguished in that a timer provided in the bus interface or a timer provided in the chip that contains the bus interface is used to ascertain the timing of operations taking place within the bus interface and/or on the bus. This allows data required for configuring the bus interface to be acquired more simply, more quickly, more accurately and more comprehensively than is the case up to now. In addition, the bus interface is consequently able to match itself to the given circumstances.

Abstract: A method (300) for detecting excessive use of a data processing system, such as a computer or a video game, is disclosed. In a first embodiment of the invention, the method estimates (315 340, 365) the length of a period of continuous use of the system, typically a computer. When the estimated period reaches a pre-set threshold value, a warning is provided to the user (325, 345), in order to discourage he or she from looking at the monitor. In a different embodiment of the invention, the system (typically a video game) is disabled when its usage during the current day reaches a further pre-set threshold value. In this way, parents may limit the daily usage of video games by their children.

Abstract: A device for calculating the steady state behavior of a controller includes an amount generating unit for generating the amount of deviation of the regulator, a first threshold value calculation unit that detects whether the amount of deviation of the regulator has fallen below a first threshold value and then starts a lag time delay unit, and a second threshold value calculation unit that detects whether the amount of deviation of the regulator has fallen below a second threshold value. A signal transmission unit transmits a ready message signal when the lag time delay unit has reached a predetermined lag time and the second threshold value calculation unit has detected that the amount of deviation of the regulator has fallen below the second threshold value.

Abstract: A method, an apparatus and a program for detecting similarity between two time-domain signals, at a high speed, and a recording medium on which is recorded such program. The process for detecting the similarity is split into a stage for calculating the similarity between feature vectors at each discrete time t and a stage for counting the number of similar vectors in the entire time series. In the calculating stage, the distances between the components for the same frame numbers of the feature vector time series gt, ft are hierarchically integrated. If the ultimate integrated value is lower than the distance threshold value S, the feature vector time series gt, ft are determined to be similar. If the integrated value exceeds the threshold value part way in the course of the hierarchical integration, the feature vector time series gt, ft are determined to be dissimilar and the integrating calculations for the remaining components are discontinued.

Abstract: A method, apparatus, and computer implemented instructions for maintaining data integrity in logs in a data processing system. A log is reviewed. A determination is made as to whether the log contains a data loss. Data may be added to replace the data loss in the log to increase integrity of the log if a determination is made that a data loss has occurred.

Abstract: A semiconductor device including a first signal path for guiding an input signal from a first pad to an input terminal of a macro cell; a second signal path for guiding a clock from a second pad to a clock input terminal of the macro cell; a third signal path for guiding an output signal from a signal output terminal of the macro cell to a third pad; and a fourth signal path for receiving the clock from the first signal path and guiding the clock to a fourth pad. It is possible to eliminate wiring delay by measuring the time from when the input signal and the clock are supplied by the first and second pads until the output signal is output by the third pad, and the time from when the clock is supplied to the second path until it is output by the fourth pad.

Abstract: A system and method for controlling a controlled parameter that affects a target parameter of a target zone is disclosed. The method comprises providing a feedback control loop having a switching controller, a controlled device, and an averaging device. The controlled device comprises a time constant and a specified operational characteristic. The controlled device comprises a first operational state and a second operational state. The method further comprises calculating a time constant for the averaging device based at least on the time constant for the controlled device, and the specified operational characteristic. The specified operational characteristic may comprises a minimum amount of time that the controlled device operates before it can be switched between the first operational state and the second operational state.

Abstract: A technique for implementing an extended bit timer with a time processing unit (TPU), without using the channel hardware of the TPU includes a number of steps. A timer of the TPU is periodically read to determine the value of the timer. A counter is incremented when rollover of the timer has occurred and a coherency flag is de-asserted after the timer transitions through a first count. The coherency flag is asserted after the value of the timer transitions through a third count and the value of the timer is combined with the value of the counter to provide a current count. When the coherency flag is asserted and the value of the timer is equal to or between the first and second counts, the current count is adjusted.

Abstract: The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to measure a signal propagation delay through an object connected to an optoelectronic device. The present invention includes determining for how long after a specific bit or bit group is transmitted by an optical transceiver the bit or bit group is received at the other end of the object connected to the optical transceiver.

Abstract: A method for monitoring the performance of a test apparatus (1) for testing a batch of integrated circuits. The apparatus 1 comprises a test site 2 in which the integrated circuits are sequentially tested, and a microprocessor (4) for carrying out the appropriate tests on the integrated circuits. A first ROM (5) stores a computer programme for controlling the operation of the microprocessor (4) for carrying out the tests, and a first RAM (10) stores a computer programme for controlling the operation of the microprocessor (4) for monitoring the performance of the test apparatus (1). In particular, the computer programme stored in the first RAM (10) operates the microprocessor (4) for computing the test time period for each integrated circuit tested, and also for computing the intervening time periods between each integrated circuit tested. The intervening time periods between the respective test time periods are classified as either first or second category delays or index time periods.

Abstract: An operating time is determined by an approximation method within the scope of the method for determining the actual operating time of a hydraulic, electrohydraulic or electric component of a motor vehicle or of a working machine within a reference time or a monitoring period.

Abstract: A system and corresponding method for measuring relative timing of signal events in at least one measurement signal includes input circuitry for receiving such a measurement signal. The input circuitry may include a comparator configured to convert the measurement input signal into a binary timing signal that is indicative of selected transitions, or signal events, in the measurement signal. The original measurement signal, or subsequently generated timing signal, is then provided to signal splitting circuitry that is configured to split such signal a predetermined number of times and to generate a plurality of data streams whose frequency level is lower than the frequency level of the original measurement signal.

Abstract: A production machine has at least one signal output with the capability of transmitting production status information to a production control system or production monitoring system. Signal outputs of the production machine are picked up and the statuses of the signal outputs are passed on via data connections to an operator console. The product status information obtained in this way is transmitted together with the information input manually by an operator via a data connection to a computer system for evaluation. A method generates events regarding production information while the production machine is operating.

Abstract: A dietetic scale and method for calculating and tracking nutritional content information. The scale includes a bar code reader for identifying a food product from its package, with food content data per unit weight of the product being retrieved from a database. The database is a compilation of standardized nutrition facts promulgated by the FDA or other authority for the food products, with the bar code being correlated with the food products by means of their individual UPC numbers. The scale cumulatively sends the nutritional content data for servings of food products consumed over a predetermined interval of time, and then compares the summed values with a predetermined goal that includes minimums and maximums for selected contents. The information may be outputted to a digital flashcard or other electronic storage media for subsequent retrieval and analysis.

Abstract: A system for automatic collection and transport of readings from water, gas and electricity meters wherein at least one receiver element and one element to transmit (1) define an ad-hoc wireless network, self organizing in an area (A), where the readings are transmitted to the next element using multihop techniques according to a routing algorithm. A value t is assigned to the receiver elements (1), with maximum value T. If the direct neighbours of a given network node have as a maximum an assigned value t, a value t-k is assigned to this node. Every node will transmit a message to a node with t value larger than its own. If there is more than one with the same maximum value, it will transmit to one of them. The system allows the meter reading to be transported automatically to the billing center.

Abstract: In an ensemble oscillator system including multiple free-running oscillators, a voltage controlled oscillator having a frequency responsive to a control signal, and a differencer unit that measures time differences between the oscillators, an adaptive Kalman Filter Processor (AKFP) generates the control signal responsive to the time differences. The AKFP uses oscillator noise models to model noise/errors of the ensemble system oscillators, including random noise parameters, and adaptively estimates the errors and the random noise parameters to derive the control signal.

Abstract: Methods and devices for monitoring distributed electric power are disclosed, including energy devices with a sensor for monitoring an electric circuit, and a memory to store sensor measurements. Various techniques are disclosed for using polymeric RAM, 1T-DRAM, enhanced SRAM, magnetoresistive RAM, organic RAM, chalcogenide RAM, holographic memory, PLEDM, single-electron RAM, fractal cluster glass memory and other technologies in energy devices with high-endurance, high-density, high-capacity, non-volatile, solid-state, or removable memories.