Abstract: A method for measuring performance of neural processing devices and devices for measuring performance are provided. The method for measuring performance of neural processing devices comprises receiving hardware information of a neural processing device, modeling hardware components according to the hardware information as agents, dividing a calculation task by events for the agents and modeling the calculation task, thereby generating an event model which includes nodes corresponding to the agents and edges corresponding to the events and measuring a total duration of the calculation task through simulation of the event model.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating output sequences using auto-regressive decoder neural networks. In particular, during generation, adaptive early exiting is used to reduce the time required to generate the output sequence.

Abstract: Disclosed is a method for implementing an adaptive stochastic spiking neuron based on a ferroelectric field effect transistor, relating to the technical field of spiking neurons in neuromorphic computing. Hardware in the method includes a ferroelectric field effect transistor (fefet), an n-type mosfet, and an l-fefet formed by enhancing a polarization degradation characteristic of a ferroelectric material for the ferroelectric field-effect transistor, wherein a series structure of the fefet and the n-type mosfet adaptively modulates a voltage pulse signal transmitted from a synapse. The l-fefet has a gate terminal connected to a source terminal of the fefet to receive the modulated pulse signal, and simulates integration, leakage, and stochastic spike firing characteristics of a biological neuron, thereby implementing an advanced function of adaptive stochastic spike firing of the neuron.

Abstract: The present disclosure discloses a data processing method and related products, in which the data processing method includes: generating, by a general-purpose processor, a binary instruction according to device information of an AI processor, and generating an AI learning task according to the binary instruction; transmitting, by the general-purpose processor, the AI learning task to the cloud AI processor for running; receiving, by the general-purpose processor, a running result corresponding to the AI learning task; and determining, by the general-purpose processor, an offline running file according to the running result, where the offline running file is generated according to the device information of the AI processor and the binary instruction when the running result satisfies a preset requirement. By implementing the present disclosure, the debugging between the AI algorithm model and the AI processor can be achieved in advance.

Abstract: Techniques to partition a neural network model for serial execution on multiple processing integrated circuit devices are described. An initial partitioning of the model into multiple partitions each corresponding to a processing integrated circuit device is performed. For each partition, an execution latency is calculated by aggregating compute clock cycles to perform computations in the partition, and weight loading clock cycles determined based on a number of weights used in the partition. The amount of data being outputted from the partition is also determined. The partitions can be adjusted by moving computations from a source partition to a target partition to change execution latencies of the partitions and the amount of data being transferred between partitions.

Abstract: A computer implemented method for speeding up execution of a convex optimization operation one or more quadratic complexity operations to be performed by an analog crossbar hardware switch, and identifying one or more linear complexity operations to be performed by a CPU. At least one of the quadratic complexity operations is performed by the analog crossbar hardware, and at least one of the linear complexity operations is performed by the CPU. An iteration of an approximation of a solution to the convex optimization operation is updated by the CPU.

Abstract: Various systems, devices, and methods for operating on a data sequence. A system includes a set of circuits that form an input layer to receive a data sequence; first hardware computing units to transform the data sequence, the first hardware computing units connected using a set of randomly selected weights, a first hardware computing unit to: receive an input from a second hardware computing unit, determine a weight of a connection between the first and second hardware computing units using an identifier of the second hardware computing unit and a fixed random weight generator, and operate on the input using the weight to determine a state of the first hardware computing unit; and second hardware computing units to operate on states of the first computing units to generate an output based on the data sequence.

Abstract: The present disclosure discloses a data processing method and related products, in which the data processing method includes: generating, by a general-purpose processor, a binary instruction according to device information of an AI processor, and generating an AI learning task according to the binary instruction; transmitting, by the general-purpose processor, the AI learning task to the cloud AI processor for running; receiving, by the general-purpose processor, a running result corresponding to the AI learning task; and determining, by the general-purpose processor, an offline running file according to the running result, where the offline running file is generated according to the device information of the AI processor and the binary instruction when the running result satisfies a preset requirement. By implementing the present disclosure, the debugging between the AI algorithm model and the AI processor can be achieved in advance.

Abstract: A promotion value model uses deep neural networks to learn to calculate the promotion value of a commercial brand. The model determines and reports the promotion value of a plurality of electronic media files each containing at least one commercial brand indicator. The learned model identifies the electronic media files and determines at least one context for each of the at least one commercial brand indicators. Promotion value is modeled with a deep neural network that maps the context for each of the commercial brand indicators to feature vectors mapped to an input layer of the neural network. Network parameters are learned to indicate relative weighted values between transitions of the layers of the neural network.

Abstract: A neural network system includes an array circuit and a gate circuit. The array circuit generates output data based on first input data, by a plurality of memory cells. The gate circuit outputs a select signal, based on defect information which is obtained based on the output data. A target memory cell, which is activated in response to the select signal, from among the plurality of memory cells is trained based on second input data, and the defect information is associated with a defect included in the plurality of memory cells.

Abstract: Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has at least one input and at least one output. The at least one input is arranged to receive streaming data passed through the reconfigurable stream switch, and the at least one output is arranged to stream resultant data through the reconfigurable stream switch. The arithmetic unit also has a plurality of data paths. At least one of the plurality of data paths is solely dedicated to performance of operations that accelerate an activation function represented in the form of a piece-wise second order polynomial approximation.

Abstract: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.

Abstract: Embodiments described herein relate to a method, comprising: receiving input data at a convolutional neural network (CNN) model; generating a factorized computation network comprising a plurality of connections between a first layer of the CNN model and a second layer of the CNN model, wherein: the factorized computation network comprises N inputs, the factorized computation network comprises M outputs, and the factorized computation network comprises at least one path from every input of the N inputs to every output of the M outputs; setting a connection weight for a plurality of connections in the factorized computation network to 1 so that a weight density for the factorized computation network is <100%; performing fast pointwise convolution using the factorized computation network to generate fast pointwise convolution output; and providing the fast pointwise convolution output to the second layer of the CNN model.

Abstract: An electronic device and a method for document segmentation are provided. The method includes: obtaining a first feature map and a second feature map corresponding to an original document; performing a first upsampling on the second feature map to generate a third feature map; concatenating the first feature map and the third feature map to generate a fourth feature map; inputting the fourth feature map to a first inverted residual block (IRB) and performing a first atrous convolution operation based on a first dilation rate to generate a fifth feature map; inputting the fourth feature map to a second IRB and performing a second atrous convolution operation based on a second dilation rate to generate a sixth feature map; concatenating the fifth feature map and the sixth feature map to generate a seventh feature map; performing a convolution operation on the seventh feature map to generate a segmented document.

Abstract: A method, device and computer program product for deep learning are provided. According to one example, a parameter related to a deep learning model for a training dataset allocated to a server is obtained at a client; a transmission state of the parameter is determined, the transmission state indicating whether the parameter has been transmitted to the server; and information associated with the parameter to be sent to the server is determined based on the transmission state to update the deep learning model. Therefore, the performance of deep learning may be improved, and the network load of deep leaning may be reduced.

Abstract: Systems for distributed, event-based computation are provided. In various embodiments, the systems include a plurality of neurosynaptic processors and a network interconnecting the plurality of neurosynaptic processors. Each neurosynaptic processor includes a clock uncoupled from the clock of each other neurosynaptic processor. Each neurosynaptic processor is adapted to receive an input stream, the input stream comprising a plurality of inputs and a clock value associated with each of the plurality of inputs. Each neurosynaptic processor is adapted to compute, for each clock value, an output based on the inputs associated with that clock value. Each neurosynaptic processor is adapted to send to another of the plurality of neurosynaptic processors, via the network, the output and an associated clock value.

Abstract: A computer-implemented method, a computer program product, and a computer system for efficient use of computing resources in two stage training of a deep learning model. A computer executes a first first-stage training job to train a deep learning model. The computer finishes the first first-stage training job by using early stopping and then registers a first second-stage training job to train a deep learning model that has been trained in the first first-stage training job. The computer executes the first second-stage training job with a small number of epochs. The computer interrupts the first second-stage training job and executes a second first-stage training job, in response to receiving a registration of the second first-stage training job. The computer interrupts the first second-stage training job and executes a second second-stage training job that has a higher priority, in response to receiving a registration of the second second-stage training job.

Abstract: A method, a system, and a computer program product for fast training and/or execution of neural networks. A description of a neural network architecture is received. Based on the received description, a graph representation of the neural network architecture is generated. The graph representation includes one or more nodes connected by one or more connections. At least one connection is modified. Based on the generated graph representation, a new graph representation is generated using the modified at least one connection. The new graph representation has a small-world property. The new graph representation is transformed into a new neural network architecture.

Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.

Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.

Abstract: Methods and systems for sensing physical quantities are provided. In one example, an apparatus comprises: a plurality of sensing elements, each sensing element being configured to measure a physical quantity and to generate a measurement result; and a controller configured to: receive first measurement results from at least a subset of the plurality of sensing elements, each of the first measurement results corresponding to an event based at least in part on satisfying a relationship with a threshold; populate an event matrix based in part on the first measurement results; populate a change matrix based in part on the threshold; and generate information related to a distribution of the measurement results among the plurality of sensing elements based at least in part on the event matrix and the change matrix.

Abstract: Non-limiting examples of the present disclosure describe a convolutional neural network (CNN) architecture configured to evaluate conversational relevance of query-response pairs. A CNN model is provided that can include a first branch, a second branch, and multilayer perceptron (MLP) layers. The first branch includes convolutional layers with dynamic pooling to process a query. The second branch includes convolutional layers with dynamic pooling to process candidate responses for the query. The query and the candidate responses are processed in parallel using the CNN model. The MLP layers are configured to rank query-response pairs based on conversational relevance.

Abstract: An information processing apparatus includes: a soma-related information storage unit in which two or more pieces of soma-related information having a soma identifier are stored; a connection information storage unit in which one or more pieces of connection information for specifying connection between two or more somas are stored; an information transfer unit that acquires soma identifiers of one or more somas that accept information based on accepted input information; an output information acquiring unit that acquires output information, which is information that is output, using the information accepted by each soma identified with the one or more soma identifiers acquired by the information transfer unit; an information output unit that outputs the output information; and a growth unit that performs soma generation processing for generating soma-related information and accumulating the information in the soma-related information storage unit.

Abstract: Core utilization optimization by dividing computational blocks across neurosynaptic cores is provided. In some embodiments, a neural network description describing a neural network is read. The neural network comprises a plurality of functional units on a plurality of cores. A functional unit is selected from the plurality of functional units. The functional unit is divided into a plurality of subunits. The plurality of subunits are connected to the neural network in place of the functional unit. The plurality of functional units and the plurality of subunits are reallocated between the plurality of cores. One or more unused cores are removed from the plurality of cores. An optimized neural network description is written based on the reallocation.

Abstract: A method for processing overhead of memory access includes: applying for a memory configured to perform value padding on at least one convolution operation in a deep learning model; determining input data of the deep learning model; performing deep learning processing on the input data by using the deep learning model; and releasing the memory after performing the deep learning processing.

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

Abstract: Systems and methods are provided for receiving input data to be processed by an encrypted neural network (NN) model, and encrypting the input data using a fully homomorphic encryption (FHE) public key associated with the encrypted NN model to generate encrypted input data. The systems and methods further provided for processing the encrypted input data to generate an encrypted inference output, using the encrypted NN model by, for each layer of a plurality of layers of the encrypted NN model, computing an encrypted weighted sum using encrypted parameters and a previous encrypted layer, the encrypted parameters comprising at least an encrypted weight and an encrypted bias, approximating an activation function for the level into a polynomial, and computing the approximated activation function on the encrypted weighted sum to generate an encrypted layer. The generated encrypted inference output is sent to a server system for decryption.

Abstract: The present disclosure relates to a neuron for an artificial neural network. The neuron comprises a dot product engine operative to: receive a set of weights; receive a set of data inputs based on a set of input data signals; and calculate the dot product of the set of data inputs and the set of weights to generate a dot product engine output. The neuron further comprises an activation function module arranged to apply an activation function to a signal indicative of the dot product engine output to generate a neuron output; and gain control circuitry. The gain control circuitry is operative to control: an input gain applied to the input data signals to generate the set of data inputs; and an output gain applied to the dot product engine output or by the activation function module. The output gain is selected to compensate for the applied input gain.

Abstract: A semiconductor device capable of efficiently recognizing images utilizing a neural network is provided. The semiconductor device includes a shift register group, a D/A converter, and a product-sum operation circuit. The product-sum operation circuit includes an analog memory and stores a parameter of a filter. The shift register group captures image data and outputs part of the image data to the D/A converter while shifting the image data. The D/A converter converts the part of the input image data into analog data and outputs the analog data to the product-sum operation circuit.

Abstract: A system for selection and configuration of an automated robotic process includes a media input module structured to receive at least one functional media, a media analysis module structured to analyze the at least one functional media and identify an action parameter; and a solution selection module structured to select at least one component of an AI solution for use in an automated robotic process, wherein the selection is based, at least in part, on the action parameter.

Abstract: Aspects discussed herein may relate to methods and techniques for embedding constrained and unconstrained optimization programs as layers in a neural network architecture. Systems are provided that implement a method of solving a particular optimization problem by a neural network architecture. Prior systems required use of external software to pre-solve optimization programs so that previously determined parameters could be used as fixed input in the neural network architecture. Aspects described herein may transform the structure of common optimization problems/programs into forms suitable for use in a neural network. This transformation may be invertible, allowing the system to learn the solution to the optimization program using gradient descent techniques via backpropagation of errors through the neural network architecture. Thus these optimization layers may be solved via operation of the neural network itself.

Abstract: A homeostatic circuit for neural networks includes a feedback circuit, a first electronic switch, a synapse circuit, a second electronic switch, a third electronic switch and a first capacitor. The feedback circuit is configured to receive the total synaptic driving current and output a feedback voltage which varies with the total synaptic driving current. The first electronic switch is connected with the synapse circuit and the second electronic switch and configured to receive the feedback voltage and output a current control signal according to the feedback voltage. The second electronic switch is connected with the synapse circuit and the third electronic switch and configured to output a first voltage signal according to the current control signal. The third electronic switch is configured to adjust the total synaptic driving current in a direction opposite to variation tendency of the total synaptic driving current according to the first voltage signal.

Abstract: A processor-implemented neural network method includes calculating individual update values for a weight assigned to a connection relationship between nodes included in a neural network; generating an accumulated update value by accumulating the individual update values in an accumulation buffer; and training the neural network by updating the weight using the accumulated update value in response to the accumulated update value being equal to or greater than a threshold value.

Abstract: A discrete 3-D processor comprises first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.

Abstract: A processor partitions a deep neural network having a plurality of exit points and at least one partition point in a branch corresponding to each of the exit points, for distributed processing in an edge device and a cloud. The processor sets environmental variables and training variables for training, selects an action to move at least one of an exit point and a partition point from a combination of the exit point and the partition point corresponding to a current state, performs the training by accumulating experience data using a reward according to the selected action and then moves to a next state, and outputs a combination of an optimal exit point and a partition point as a result of the training.

Abstract: A neural network computing engine having an array of charge-trap-transistor (CTT) elements which are utilized as analog multipliers with all weight values preprogrammed into each CTT element as a CTT threshold voltage, with multiplicator values received from the neural network inference mode. The CTT elements perform computations of a fully connected (FC) neural network with each CTT element representing a neuron. Row resistors for each row of CTT element sum output currents as partial summation results. Counted pulse generators write weight values under control of a pulse generator controller. A sequential analog fabric (SAF) feeds multiple drain voltages in parallel to the CTT array to enable parallel analog computations of neurons. Partial summation results are read by an analog-to-digital converter (ADC).

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: A method for diagnosing a problematic noise source based on big data information include: measuring noise data of a powertrain of a vehicle by using a real-time noise measurement device, and converting the noise data into a signal that can be input to a portable device for diagnosing the problematic noise source through an interface device; analyzing a noise through a deep learning algorithm of an artificial intelligence on a converted signal, and diagnosing the problematic noise source as a cause of the noise; and displaying the cause of the noise by outputting a diagnostic result as the problematic noise source, and transmitting the diagnostic result to the portable device.

Abstract: One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.

Abstract: A device includes first wires, second wires, resistors, and a processor. Input signals are transmitted from the first wires through the resistors to the second wires. The processor receives a sum value of the input signals from one of the second wires, and shifts the sum value by a nonlinear activation function to generate a shifted sum value. The processor calculates a backpropagation value based on the shifted sum value and a target value, and generates a pulse number based on a corresponding input signal of the input signal and the backpropagation value. Each of a value of the corresponding input signal and the backpropagation value is higher than or equal to a threshold value. The processor applies a voltage pulse to one of the resistors related to the corresponding input signal based on the pulse number.

Abstract: Systems and processes for operating an intelligent automated assistant are provided. In one example, a method includes receiving mixed speech data representing utterances of a target speaker and utterances of one or more interfering audio sources. The method further includes obtaining a target speaker representation, which represents speech characteristics of the target speaker; and determining, using a learning network, probability distributions of phonetic elements directly from the mixed speech data. The inputs of the learning network include the mixed speech data and the target speaker representation. An output of the learning network includes the probability distributions of phonetic elements. The method further includes generating text corresponding to the utterances of the target speaker based on the probability distributions of the phonetic elements; and providing a response to the target speaker based on the text corresponding to the utterances of the target speaker.

Abstract: A fluxonic processor includes processes photonic synapse events and includes a transmitter that receives neuron signal and produces output photons; a neuron that receives a dendrite signal and produces the neuron signal from the dendrite signal; a dendrite that receives a synapse signal, and produces the dendrite signal from the synapse signal, the dendrite including: a dendritic receiver loop; a dendritic Josephson isolator; and a dendritic integration loop; and the synapse in electrical communication with the dendrite and that receives an input photon and produces the synapse signal from the input photon, the synapse including: a synaptic receiver; a synaptic Josephson isolator in communication with the synaptic receiver; and a synaptic integration loop that receives the synaptic receiver fluxons and produces the synapse signal from the synaptic receiver fluxons.

Abstract: In one aspect, A method for computing neural network computation includes the step of, providing plurality of neurons, coupled with a plurality of inputs, through a plurality of synapses. Each neuron output is given by an equation ?(Xi*Yi)+b. Xi*Yi comprises the ith synapse of the neuron. Xi comprises a set of Xi input vectors. Each Xi input vector is translated into an equivalent electrical signal for an ith corresponding synapse of the plurality of neurons, Yi comprises a set of Yi weight vectors, wherein each Yi weight vector comprises a parameter for the ith corresponding synapse of the plurality of neurons. Each synapse is a sub-system and the sub-system comprises a negative vector neural circuit, a positive vector neural circuit, and a set of four non-volatile memory weight cells for computation. The method includes the step of identifying the input vector x as a positive input vector or a negative input vector.

Abstract: A computing system is disclosed including a convolutional neural configured to receive an input that describes a facial image and generate a facial object recognition output that describes one or more facial feature locations with respect to the facial image. The convolutional neural network can include a plurality of convolutional blocks. At least one of the convolutional blocks can include one or more separable convolutional layers configured to apply a depthwise convolution and a pointwise convolution during processing of an input to generate an output. The depthwise convolution can be applied with a kernel size that is greater than 3×3. At least one of the convolutional blocks can include a residual shortcut connection from its input to its output.

Abstract: A synapse array of a neuromorphic device is provided. The synapse array may include a pre-synaptic neuron; a row line extending from the pre-synaptic neuron in a row direction; a post synaptic neuron; a column line extending from the post-synaptic neuron in a column direction; and a synapse disposed at an intersection region between the row line and the column line. The synapse may include an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a gate electrode and a body; a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a gate electrode and a body; and a resistive element having a first node electrically connected to the source electrode of the n-FeFET and electrically connected to the source electrode of the p-FeFET, and the n-FeFET and the p-FeFET are electrically connected in series.

Abstract: A system, article, and method of deep supervision object detection for reducing resource usage is provided for image processing and that uses depth-wise dense blocks.

Abstract: A processing device and related products are disclosed. The processing device includes a main unit and a plurality of basic units in communication with the main unit. The main unit is configured to perform a first set of operations in a neural network in series, and transmit data to the plurality of basic units. The plurality of basic units are configured to receive the data transmitted from the main unit, perform a second set of operations in the neural network in parallel based on the data received from the main unit, and return operation results to the main unit.

Abstract: A non-volatile memory structure capable of storing layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. A stack of bonded die pairs is connected by through silicon vias. Each bonded die pair includes a memory die, having one or more memory arrays onto which layers of the neural network are mapped, and a peripheral circuitry die, including the control circuits for performing the convolution or multiplication for the bonded die pair. The multiplications can either be done in-array on the memory die or in-logic on the peripheral circuitry die. The arrays can be formed into columns along the vias, allowing an inferencing operation to be performed by propagating an input up and down the columns, with the output of one level being the input of the subsequent layer.

Abstract: Embodiments of the present application disclose a deep learning-based face identification method and a related product. The method is applied to an electronic apparatus. The method includes: acquiring an aligned face image, and scaling the face image at a preset ratio to obtain a target image; extracting a pixel matrix of the target image, inputting the pixel matrix to the neural network model, and executing multilayer computing to obtain a computing result; and calculating a cosine similarity degree between the computing result and a facial template vector, wherein comparison is successful if the cosine similarity degree is greater than a preset threshold. The embodiments of the present application help improve the identification success rate and the identification speed.

Abstract: Computer systems and computer-implemented methods train and/or operate, once trained, a machine-learning system that comprises a plurality of generator-detector pairs. The machine-learning computer system comprises a set of processor cores and computer memory that stores software. When executed by the set of processor cores, the software causes the set of processor cores to implement a plurality of generator-detector pairs, in which: (i) each generator-detector pair comprises a machine-learning data generator and a machine-learning data detector; and (ii) each generator-detector pair is for a corresponding cluster of data examples respectively, such that, for each generator-detector pair, the generator is for generating data examples in the corresponding cluster and the detector is for detecting whether data examples are within the corresponding cluster.