Architecture Patents (Class 706/27)
  • Patent number: 12367374
    Abstract: A harmonic densely connecting method includes an input step, a plurality of layer operation steps and an output step. The input step is for storing an original input tensor of the block into a memory. Each of the layer operation steps includes a layer-input tensor concatenating step and a convolution operation step. The layer-input tensor concatenating step is for selecting at least one layer-input element tensor of a layer-input set from the memory according to an input connection rule. When a number of the at least one layer-input element tensor is greater than 1, concatenating all of the layer-input element tensors and producing a layer-input tensor. The convolution operation step is for calculating a convolution operation to produce at least one result tensor and then storing the at least one result tensor into the memory. The output step is for outputting a block output.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: July 22, 2025
    Assignee: NEUCHIPS CORPORATION
    Inventors: Ping Chao, Chao-Yang Kao, Youn-Long Lin
  • Patent number: 12346665
    Abstract: A neural architecture search method, system, and computer program product that determines, by a computing device, a best fit language model of a plurality of language models that is a best fit for interpretation of a corpus of natural language and interprets, by the computing device, the corpus of natural language using the best fit language model.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: July 1, 2025
    Assignee: International Business Machines Corporation
    Inventors: Michele Merler, Aashka Trivedi, Rameswar Panda, Bishwaranjan Bhattacharjee, Taesun Moon, Avirup Sil
  • Patent number: 12346824
    Abstract: Aspects discussed herein may relate to methods and techniques for embedding constrained and unconstrained optimization programs as layers in a neural network architecture. Systems are provided that implement a method of solving a particular optimization problem by a neural network architecture. Prior systems required use of external software to pre-solve optimization programs so that previously determined parameters could be used as fixed input in the neural network architecture. Aspects described herein may transform the structure of common optimization problems/programs into forms suitable for use in a neural network. This transformation may be invertible, allowing the system to learn the solution to the optimization program using gradient descent techniques via backpropagation of errors through the neural network architecture. Thus these optimization layers may be solved via operation of the neural network itself.
    Type: Grant
    Filed: April 22, 2024
    Date of Patent: July 1, 2025
    Assignee: Capital One Services, LLC
    Inventors: Tarek Aziz Lahlou, Christopher Larson, Oluwatobi Olabiyi
  • Patent number: 12346462
    Abstract: Systems and methods for securing content using unidirectional encryption. A method includes obtaining a first transformed array created by applying a transformation process to an inference array, wherein the inference array is a reduced representation of media content created by embedding the media content, wherein the first transformed array preserves a dot product result of the inference array, wherein the transformation process is a unidirectional process such that attempting to reconstruct the media content using the first transformed array will result in different media content; determining a dot product result between the first transformed array and a second transformed array created using the transformation process; checking conditions using the dot product result between the first transformed array and the second transformed array; and determining a relationship between the first transformed array and the second transformed array based on the checking of the conditions.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: July 1, 2025
    Assignee: NACRE CAPITAL HOLDINGS LTD.
    Inventors: Tomer Saar, Yoni Donner, Aviram Bar-Haim
  • Patent number: 12333626
    Abstract: A processor, method and non-transitory computer-readable storage medium for handling data, by obtaining task data describing a task to be executed in the form of a plurality of operations on data, the task data further defining an operation space of said data, analyzing each of the operations to define transformation data comprising transformation instruction representing a transform into an associated operation-specific local spaces. In case transformation instructions to get to the operation-specific local space for an operation are producing less dimensions compared to the operation space, one or more operation-specific arguments are stored in a data field corresponding to a dimension not produced by the transformation instructions in the transformation data corresponding to the operation.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: June 17, 2025
    Assignee: Arm Limited
    Inventors: Rune Holm, Elliot Maurice Simon Rosemarine
  • Patent number: 12288157
    Abstract: A system and method are disclosed for providing an artificial intelligence platform. An example method includes examining part of a global neural network to locate a split layer in the global neural network, creating an equivalent model to the part of the global neural network of a same size but having opposite operations, generating smashed data based on an operation on input data by the part of the global neural network, training the equivalent model by inputting the smashed data to generate a second a mirrored copy of the input data, quantifying a distance between the input data and the second generated set of mirrored data to yield a value and, when the value is below a threshold, determining that a current location of the split layer in the global neural network is safe for a training process.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: April 29, 2025
    Assignee: Selfiee Corporation
    Inventors: Gharib Gharibi, Andrew Rademacher, Greg Storm, Riddhiman Das
  • Patent number: 12273374
    Abstract: Systems and methods herein describe a malware visualization system that is configured to access a computer file, generate a first image of the computer file, determine a frequency count of bi-grams in the computer file, compute a discrete cosine transform (DCT) of the frequency count of bi-grams, generate a second image of the computer file based on the DCT of the frequency count of bi-grams, analyze the first image and the second image using an image classification neural network and generate a classification of the computer file.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 8, 2025
    Assignee: Mayachitra, Inc.
    Inventors: Tajuddin Manhar Mohammed, Lakshmanan Nataraj, Bangalore S. Manjunath, Shivkumar Chandrasekaran
  • Patent number: 12216647
    Abstract: Provided are a method, system, and device for a neural architecture search (NAS) pipeline for performing an optimized neural architecture search (NAS). The method may include obtaining a first search space comprising a plurality of candidate layers for a neural network architecture; performing a training-free NAS in the first search space to obtain a first set of architectures; obtaining a second search space based on the first set of architectures; performing a gradient-based search in the second search space to obtain a second set of architectures; performing a sampling method search utilizing the second set of architectures as an initial sample; and obtaining an output architecture as an output of the sampling method search.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: February 4, 2025
    Assignee: WOVEN BY TOYOTA, INC.
    Inventor: Koichiro Yamaguchi
  • Patent number: 12217092
    Abstract: An electronic apparatus includes a memory configured to store data corresponding to a neural network model, a neural network accelerator including a buffer configured to temporarily store the data corresponding to the neural network model, and a core configured to perform a computation on the neural network model based on the data stored in the buffer, and a processor configured to determine a plurality of combinations including fused layers and non-fused layers based on a method of selecting and fusing adjacent layers of the neural network model, based on a capacity of the buffer, determine a size of a tile capable of being processed in one computation in the core to acquire feature values output by the fused layers and the non-fused layers, and based on a first memory usage and computation time for storing the feature values in the buffer, determine whether to store the feature values in the memory.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: February 4, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyukjin Jeong, Jihwan Yeo
  • Patent number: 12198036
    Abstract: A resistance variable type synapse array apparatus that can perform STDP writing using a positive potential is provided. The synapse array apparatus includes a writing unit writing to a selected resistance variable type memory element in a crossbar array. The writing unit includes a driver generating a positive pulse signal corresponding to a positive part of a spike signal generated by a presynaptic neuron, a driver generating a positive pulse signal corresponding to a negative part of a spike signal generated by a postsynaptic neuron, a driver generating a positive pulse signal corresponding to a positive part of the spike signal generated by the postsynaptic neuron, and a driver generating a positive pulse signal corresponding to a negative part of the spike signal generated by the presynaptic neuron.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: January 14, 2025
    Assignee: Winbond Electronics Corp.
    Inventors: Yasuhiro Tomita, Masaru Yano
  • Patent number: 12182686
    Abstract: Networks and encodings therefor are provided that are adapted to provide increased energy efficiency and speed for convolutional operations. In various embodiments, a neural network comprises a plurality of neural cores. Each of the plurality of neural cores comprises a memory. A network interconnects the plurality of neural cores. The memory of each of the plurality of neural cores comprises at least a portion of a weight tensor. The weight tensor comprising a plurality of weights. Each neural core is adapted to retrieve locally or receive a portion of an input image, apply the portion of the weight tensor thereto, and store locally or send a result therefrom via the network to other of the plurality of neural cores.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 31, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Dharmendra S. Modha
  • Patent number: 12182687
    Abstract: Systems for neural network computation are provided. A neural network processor comprises a plurality of neural cores. The neural network processor has one or more processor precisions per activation. The processor is configured to accept data having a processor feature dimension. A transformation circuit is coupled to the neural network processor, and is adapted to: receive an input data tensor having an input precision per channel at one or more features; transform the input data tensor from the input precision to the processor precision; divide the input data into a plurality of blocks, each block conforming to one of the processor feature dimensions; provide each of the plurality of blocks to one of the plurality of neural cores. The neural network processor is adapted to compute, by the plurality of neural cores, output of one or more neural network layers.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 31, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John V. Arthur, Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy, Jun Sawada, Dharmendra S. Modha, Steven K. Esser, Brian Taba, Jennifer Klamo
  • Patent number: 12175359
    Abstract: An apparatus for training and inferencing a neural network includes circuitry that is configured to generate a first weight having a first format including a first number of bits based at least in part on a second weight having a second format including a second number of bits and a residual having a third format including a third number of bits. The second number of bits and the third number of bits are each less than the first number of bits. The circuitry is further configured to update the second weight based at least in part on the first weight and to update the residual based at least in part on the updated second weight and the first weight. The circuitry is further configured to update the first weight based at least in part on the updated second weight and the updated residual.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: December 24, 2024
    Assignee: International Business Machines Corporation
    Inventors: Xiao Sun, Jungwook Choi, Naigang Wang, Chia-Yu Chen, Kailash Gopalakrishnan
  • Patent number: 12169643
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that increase data reuse for multiply and accumulate (MAC) operations. An example apparatus includes a MAC circuit to process a first context of a set of a first type of contexts stored in a first buffer and a first context of a set of a second type of contexts stored in a second buffer. The example apparatus also includes control logic circuitry to, in response to determining that there is an additional context of the second type to be processed in the set of the second type of contexts, maintain the first context of the first type in the first buffer. The control logic circuitry is also to, in response to determining that there is an additional context of the first type to be processed in the set of the first type of contexts maintain the first context of the second type in the second buffer and iterate a pointer of the second buffer from a first position to a next position in the second buffer.
    Type: Grant
    Filed: September 12, 2023
    Date of Patent: December 17, 2024
    Assignee: Intel Corporation
    Inventors: Niall Hanrahan, Martin Power, Kevin Brady, Martin-Thomas Grymel, David Bernard, Gary Baugh, Cormac Brick
  • Patent number: 12130756
    Abstract: An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: October 29, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hanmin Park, Hyung-Dal Kwon, Jaehyeong Sim, Seungwook Lee, Jae-Eon Jo
  • Patent number: 12106551
    Abstract: The present application discloses a visual enhancement method and a system based on fusion of spatially aligned features of multiple networked vehicles. The method utilizes the visual features of networked vehicles themselves and their surroundings within a certain range, and performs feature fusion after spatial alignment to realize visual expansion and enhancement. After receiving the compressed intermediate feature map of the networked vehicles in a certain range around, the decompressed intermediate feature map is subjected to affine transformation, and the transformed aligned feature map is subjected to feature fusion based on a designed multi-feature self-learning network, so as to realize the complementation and enhancement among features while removing redundant features. The fused intermediate features are used to detect the target obstacles from the perspective of the networked vehicle itself and partially or completely blocked, thus improving the safety of driving connected vehicles.
    Type: Grant
    Filed: October 25, 2023
    Date of Patent: October 1, 2024
    Assignee: ZHEJIANG LAB
    Inventors: Qian Huang, Zhifeng Zhao, Yongdong Zhu, Yuntao Liu
  • Patent number: 12079727
    Abstract: Input data having multiple channels may be received and passed through a convolutional neural network model to generate output data. Passing the input data through the convolutional neural network model may include passing the input data through a depth-wise convolutional layer configured to perform a convolution on the input data for each channel of the input data to generate first data. The first data is passed from the depth-wise convolutional layer through a butterfly transform layer comprising multiple sub-layers configured to perform a linear transformation of the first data to fuse the channels of the first data and generate second data, wherein the output data is based on the generated second data. The output data may be provided for further processing on a computing device.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 3, 2024
    Assignee: Apple Inc.
    Inventors: Ali Farhadi, Mohammad Rastegari, Keivan Alizadeh Vahid
  • Patent number: 12079158
    Abstract: An integrated circuit includes a plurality of kernels and a virtual machine coupled to the plurality of kernels. The virtual machine is configured to interpret instructions directed to different ones of the plurality of kernels. The virtual machine is configured to control operation of the different ones of the plurality of kernels responsive to the instructions.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 3, 2024
    Assignee: Xilinx, Inc.
    Inventors: Sanket Pandit, Jorn Tuyls, Xiao Teng, Rajeev Patwari, Ehsan Ghasemi, Elliott Delaye, Aaron Ng
  • Patent number: 12062227
    Abstract: Systems and methods of the present disclosure can include a computer-implemented method for efficient machine-learned model training. The method can include obtaining a plurality of training samples for a machine-learned model. The method can include, for one or more first training iterations, training, based at least in part on a first regularization magnitude configured to control a relative effect of one or more regularization techniques, the machine-learned model using one or more respective first training samples of the plurality of training samples. The method can include, for one or more second training iterations, training, based at least in part on a second regularization magnitude greater than the first regularization magnitude, the machine-learned model using one or more respective second training samples of the plurality of training samples.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: August 13, 2024
    Assignee: GOOGLE LLC
    Inventors: Mingxing Tan, Quoc V. Le
  • Patent number: 12008461
    Abstract: A method for operating an artificial neuron and an apparatus for performing the method are provided. The artificial neuron may calculate a change amount of an activation based on an input signal received via an input synapse, determine whether an event occurs in response to the calculated change amount of the activation, and transmit, to an output synapse, an output signal that corresponds to the event in response to an occurrence of the event.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: June 11, 2024
    Assignees: SAMSUNG ELECTRONICS CO., LTD., UNIVERSITAET ZUERICH
    Inventors: Jun Haeng Lee, Daniel Neil, Shih-Chii Liu, Tobi Delbruck
  • Patent number: 12008460
    Abstract: Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 11, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Dmitri Yudanov, Sean S. Eilert, Hernan A. Castro, Ameen D. Akel
  • Patent number: 11989414
    Abstract: Embodiments of the present disclosure include a digital circuit and method for multi-stage compression. Digital data values are compressed using a multi-stage compression algorithm and stored in a memory. A decompression circuit receives the values and performs a partial decompression. The partially compressed values are provided to a processor, which performs the final decompression. In one embodiment, a vector of N length compressed values are decompressed using a first bit mask into two N length sets having non-zero values. The two N length sets are further decompressed using two M length bit masks into M length sparse vectors, each having non-zero values.
    Type: Grant
    Filed: June 23, 2023
    Date of Patent: May 21, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mattheus C. Heddes, Ankit More, Nishit Shah, Torsten Hoefler
  • Patent number: 11907098
    Abstract: A method for measuring performance of neural processing devices and devices for measuring performance are provided. The method for measuring performance of neural processing devices comprises receiving hardware information of a neural processing device, modeling hardware components according to the hardware information as agents, dividing a calculation task by events for the agents and modeling the calculation task, thereby generating an event model which includes nodes corresponding to the agents and edges corresponding to the events and measuring a total duration of the calculation task through simulation of the event model.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: February 20, 2024
    Assignee: Rebellions Inc.
    Inventor: Jinseok Kim
  • Patent number: 11886976
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating output sequences using auto-regressive decoder neural networks. In particular, during generation, adaptive early exiting is used to reduce the time required to generate the output sequence.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: January 30, 2024
    Assignee: Google LLC
    Inventors: Tal Schuster, Adam Joshua Fisch, Jai Prakash Gupta, Mostafa Dehghani, Dara Bahri, Vinh Quoc Tran, Yi Tay, Donald Arthur Metzler, Jr.
  • Patent number: 11868868
    Abstract: Disclosed is a method for implementing an adaptive stochastic spiking neuron based on a ferroelectric field effect transistor, relating to the technical field of spiking neurons in neuromorphic computing. Hardware in the method includes a ferroelectric field effect transistor (fefet), an n-type mosfet, and an l-fefet formed by enhancing a polarization degradation characteristic of a ferroelectric material for the ferroelectric field-effect transistor, wherein a series structure of the fefet and the n-type mosfet adaptively modulates a voltage pulse signal transmitted from a synapse. The l-fefet has a gate terminal connected to a source terminal of the fefet to receive the modulated pulse signal, and simulates integration, leakage, and stochastic spike firing characteristics of a biological neuron, thereby implementing an advanced function of adaptive stochastic spike firing of the neuron.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: January 9, 2024
    Assignee: Peking University
    Inventors: Ru Huang, Jin Luo, Tianyi Liu, Qianqian Huang
  • Patent number: 11847554
    Abstract: The present disclosure discloses a data processing method and related products, in which the data processing method includes: generating, by a general-purpose processor, a binary instruction according to device information of an AI processor, and generating an AI learning task according to the binary instruction; transmitting, by the general-purpose processor, the AI learning task to the cloud AI processor for running; receiving, by the general-purpose processor, a running result corresponding to the AI learning task; and determining, by the general-purpose processor, an offline running file according to the running result, where the offline running file is generated according to the device information of the AI processor and the binary instruction when the running result satisfies a preset requirement. By implementing the present disclosure, the debugging between the AI algorithm model and the AI processor can be achieved in advance.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: December 19, 2023
    Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITED
    Inventors: Yao Zhang, Xiaofu Meng, Shaoli Liu
  • Patent number: 11797280
    Abstract: Techniques to partition a neural network model for serial execution on multiple processing integrated circuit devices are described. An initial partitioning of the model into multiple partitions each corresponding to a processing integrated circuit device is performed. For each partition, an execution latency is calculated by aggregating compute clock cycles to perform computations in the partition, and weight loading clock cycles determined based on a number of weights used in the partition. The amount of data being outputted from the partition is also determined. The partitions can be adjusted by moving computations from a source partition to a target partition to change execution latencies of the partitions and the amount of data being transferred between partitions.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: October 24, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Parivallal Kannan, Fabio Nonato de Paula, Preston Pengra Briggs
  • Patent number: 11790033
    Abstract: A computer implemented method for speeding up execution of a convex optimization operation one or more quadratic complexity operations to be performed by an analog crossbar hardware switch, and identifying one or more linear complexity operations to be performed by a CPU. At least one of the quadratic complexity operations is performed by the analog crossbar hardware, and at least one of the linear complexity operations is performed by the CPU. An iteration of an approximation of a solution to the convex optimization operation is updated by the CPU.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: October 17, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vasileios Kalantzis, Shashanka Ubaru, Lior Horesh, Haim Avron, Oguzhan Murat Onen
  • Patent number: 11783160
    Abstract: Various systems, devices, and methods for operating on a data sequence. A system includes a set of circuits that form an input layer to receive a data sequence; first hardware computing units to transform the data sequence, the first hardware computing units connected using a set of randomly selected weights, a first hardware computing unit to: receive an input from a second hardware computing unit, determine a weight of a connection between the first and second hardware computing units using an identifier of the second hardware computing unit and a fixed random weight generator, and operate on the input using the weight to determine a state of the first hardware computing unit; and second hardware computing units to operate on states of the first computing units to generate an output based on the data sequence.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Phil Knag, Gregory Kengho Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Ram Kumar Krishnamurthy
  • Patent number: 11762690
    Abstract: The present disclosure discloses a data processing method and related products, in which the data processing method includes: generating, by a general-purpose processor, a binary instruction according to device information of an AI processor, and generating an AI learning task according to the binary instruction; transmitting, by the general-purpose processor, the AI learning task to the cloud AI processor for running; receiving, by the general-purpose processor, a running result corresponding to the AI learning task; and determining, by the general-purpose processor, an offline running file according to the running result, where the offline running file is generated according to the device information of the AI processor and the binary instruction when the running result satisfies a preset requirement. By implementing the present disclosure, the debugging between the AI algorithm model and the AI processor can be achieved in advance.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: September 19, 2023
    Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITED
    Inventors: Yao Zhang, Xiaofu Meng, Shaoli Liu
  • Patent number: 11741364
    Abstract: A promotion value model uses deep neural networks to learn to calculate the promotion value of a commercial brand. The model determines and reports the promotion value of a plurality of electronic media files each containing at least one commercial brand indicator. The learned model identifies the electronic media files and determines at least one context for each of the at least one commercial brand indicators. Promotion value is modeled with a deep neural network that maps the context for each of the commercial brand indicators to feature vectors mapped to an input layer of the neural network. Network parameters are learned to indicate relative weighted values between transitions of the layers of the neural network.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: August 29, 2023
    Assignee: HOOKIT, LLC
    Inventors: Scott Tilton, Robert J. Kraus, Adam Smith, Michael Robinson, Esther Walker, Garrison Hess
  • Patent number: 11727253
    Abstract: A neural network system includes an array circuit and a gate circuit. The array circuit generates output data based on first input data, by a plurality of memory cells. The gate circuit outputs a select signal, based on defect information which is obtained based on the output data. A target memory cell, which is activated in response to the select signal, from among the plurality of memory cells is trained based on second input data, and the defect information is associated with a defect included in the plurality of memory cells.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 15, 2023
    Assignee: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION
    Inventor: Kyeong Sik Min
  • Patent number: 11687762
    Abstract: Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has at least one input and at least one output. The at least one input is arranged to receive streaming data passed through the reconfigurable stream switch, and the at least one output is arranged to stream resultant data through the reconfigurable stream switch. The arithmetic unit also has a plurality of data paths. At least one of the plurality of data paths is solely dedicated to performance of operations that accelerate an activation function represented in the form of a piece-wise second order polynomial approximation.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: June 27, 2023
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Surinder Pal Singh, Thomas Boesch, Giuseppe Desoli
  • Patent number: 11681899
    Abstract: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: June 20, 2023
    Assignees: Samsong Electronics Co., Ltd., POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Sungho Kim, Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim, Jinseok Kim
  • Patent number: 11657279
    Abstract: An electronic device and a method for document segmentation are provided. The method includes: obtaining a first feature map and a second feature map corresponding to an original document; performing a first upsampling on the second feature map to generate a third feature map; concatenating the first feature map and the third feature map to generate a fourth feature map; inputting the fourth feature map to a first inverted residual block (IRB) and performing a first atrous convolution operation based on a first dilation rate to generate a fifth feature map; inputting the fourth feature map to a second IRB and performing a second atrous convolution operation based on a second dilation rate to generate a sixth feature map; concatenating the fifth feature map and the sixth feature map to generate a seventh feature map; performing a convolution operation on the seventh feature map to generate a segmented document.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: May 23, 2023
    Assignee: National Taiwan University of Science and Technology
    Inventors: Jing-Ming Guo, Li-Ying Chang
  • Patent number: 11657282
    Abstract: Embodiments described herein relate to a method, comprising: receiving input data at a convolutional neural network (CNN) model; generating a factorized computation network comprising a plurality of connections between a first layer of the CNN model and a second layer of the CNN model, wherein: the factorized computation network comprises N inputs, the factorized computation network comprises M outputs, and the factorized computation network comprises at least one path from every input of the N inputs to every output of the M outputs; setting a connection weight for a plurality of connections in the factorized computation network to 1 so that a weight density for the factorized computation network is <100%; performing fast pointwise convolution using the factorized computation network to generate fast pointwise convolution output; and providing the fast pointwise convolution output to the second layer of the CNN model.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 23, 2023
    Assignee: Qualcomm Incorporated
    Inventors: Jamie Menjay Lin, Yang Yang, Jilei Hou
  • Patent number: 11651221
    Abstract: A method, device and computer program product for deep learning are provided. According to one example, a parameter related to a deep learning model for a training dataset allocated to a server is obtained at a client; a transmission state of the parameter is determined, the transmission state indicating whether the parameter has been transmitted to the server; and information associated with the parameter to be sent to the server is determined based on the transmission state to update the deep learning model. Therefore, the performance of deep learning may be improved, and the network load of deep leaning may be reduced.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: May 16, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Wei Cui, Kun Wang
  • Patent number: 11645501
    Abstract: Systems for distributed, event-based computation are provided. In various embodiments, the systems include a plurality of neurosynaptic processors and a network interconnecting the plurality of neurosynaptic processors. Each neurosynaptic processor includes a clock uncoupled from the clock of each other neurosynaptic processor. Each neurosynaptic processor is adapted to receive an input stream, the input stream comprising a plurality of inputs and a clock value associated with each of the plurality of inputs. Each neurosynaptic processor is adapted to compute, for each clock value, an output based on the inputs associated with that clock value. Each neurosynaptic processor is adapted to send to another of the plurality of neurosynaptic processors, via the network, the output and an associated clock value.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: May 9, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arnon Amir, David Berg, Pallab Datta, Jeffrey A. Kusnitz, Hartmut Penner
  • Patent number: 11640552
    Abstract: A computer-implemented method, a computer program product, and a computer system for efficient use of computing resources in two stage training of a deep learning model. A computer executes a first first-stage training job to train a deep learning model. The computer finishes the first first-stage training job by using early stopping and then registers a first second-stage training job to train a deep learning model that has been trained in the first first-stage training job. The computer executes the first second-stage training job with a small number of epochs. The computer interrupts the first second-stage training job and executes a second first-stage training job, in response to receiving a registration of the second first-stage training job. The computer interrupts the first second-stage training job and executes a second second-stage training job that has a higher priority, in response to receiving a registration of the second second-stage training job.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 2, 2023
    Assignee: International Business Machines Corporation
    Inventors: Shingo Nagai, Kohhei Nomura
  • Patent number: 11625614
    Abstract: A method, a system, and a computer program product for fast training and/or execution of neural networks. A description of a neural network architecture is received. Based on the received description, a graph representation of the neural network architecture is generated. The graph representation includes one or more nodes connected by one or more connections. At least one connection is modified. Based on the generated graph representation, a new graph representation is generated using the modified at least one connection. The new graph representation has a small-world property. The new graph representation is transformed into a new neural network architecture.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 11, 2023
    Assignee: The Regents of the University of California
    Inventors: Mojan Javaheripi, Farinaz Koushanfar, Bita Darvish Rouhani
  • Patent number: 11620500
    Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 4, 2023
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Chih-Cheng Fu, Ming-Che Lin, Yu-Ting Chen, Seow-Fong (Dennis) Lim
  • Patent number: 11615069
    Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 28, 2023
    Assignee: International Business Machines Corporation
    Inventors: Sameh W. Asaad, Robert J. Halstead, Bharat Sukhwani
  • Patent number: 11604509
    Abstract: Methods and systems for sensing physical quantities are provided. In one example, an apparatus comprises: a plurality of sensing elements, each sensing element being configured to measure a physical quantity and to generate a measurement result; and a controller configured to: receive first measurement results from at least a subset of the plurality of sensing elements, each of the first measurement results corresponding to an event based at least in part on satisfying a relationship with a threshold; populate an event matrix based in part on the first measurement results; populate a change matrix based in part on the threshold; and generate information related to a distribution of the measurement results among the plurality of sensing elements based at least in part on the event matrix and the change matrix.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: March 14, 2023
    Assignee: Meta Platforms Technologies, LLC
    Inventor: Xinqiao Liu
  • Patent number: 11593613
    Abstract: Non-limiting examples of the present disclosure describe a convolutional neural network (CNN) architecture configured to evaluate conversational relevance of query-response pairs. A CNN model is provided that can include a first branch, a second branch, and multilayer perceptron (MLP) layers. The first branch includes convolutional layers with dynamic pooling to process a query. The second branch includes convolutional layers with dynamic pooling to process candidate responses for the query. The query and the candidate responses are processed in parallel using the CNN model. The MLP layers are configured to rank query-response pairs based on conversational relevance.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: February 28, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Bowen Wu, Baoxun Wang, Shuang Peng, Min Zeng, Li Zhou
  • Patent number: 11586893
    Abstract: Core utilization optimization by dividing computational blocks across neurosynaptic cores is provided. In some embodiments, a neural network description describing a neural network is read. The neural network comprises a plurality of functional units on a plurality of cores. A functional unit is selected from the plurality of functional units. The functional unit is divided into a plurality of subunits. The plurality of subunits are connected to the neural network in place of the functional unit. The plurality of functional units and the plurality of subunits are reallocated between the plurality of cores. One or more unused cores are removed from the plurality of cores. An optimized neural network description is written based on the reallocation.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: February 21, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arnon Amir, Pallab Datta, Nimrod Megiddo, Dharmendra S. Modha
  • Patent number: 11586933
    Abstract: An information processing apparatus includes: a soma-related information storage unit in which two or more pieces of soma-related information having a soma identifier are stored; a connection information storage unit in which one or more pieces of connection information for specifying connection between two or more somas are stored; an information transfer unit that acquires soma identifiers of one or more somas that accept information based on accepted input information; an output information acquiring unit that acquires output information, which is information that is output, using the information accepted by each soma identified with the one or more soma identifiers acquired by the information transfer unit; an information output unit that outputs the output information; and a growth unit that performs soma generation processing for generating soma-related information and accumulating the information in the soma-related information storage unit.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: February 21, 2023
    Assignee: SOFTBANK CORP.
    Inventor: Yuko Ishiwaka
  • Patent number: 11586469
    Abstract: A method for processing overhead of memory access includes: applying for a memory configured to perform value padding on at least one convolution operation in a deep learning model; determining input data of the deep learning model; performing deep learning processing on the input data by using the deep learning model; and releasing the memory after performing the deep learning processing.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: February 21, 2023
    Assignee: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventors: Yin Li, Liangliang He
  • Patent number: 11575500
    Abstract: Systems and methods are provided for receiving input data to be processed by an encrypted neural network (NN) model, and encrypting the input data using a fully homomorphic encryption (FHE) public key associated with the encrypted NN model to generate encrypted input data. The systems and methods further provided for processing the encrypted input data to generate an encrypted inference output, using the encrypted NN model by, for each layer of a plurality of layers of the encrypted NN model, computing an encrypted weighted sum using encrypted parameters and a previous encrypted layer, the encrypted parameters comprising at least an encrypted weight and an encrypted bias, approximating an activation function for the level into a polynomial, and computing the approximated activation function on the encrypted weighted sum to generate an encrypted layer. The generated encrypted inference output is sent to a server system for decryption.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: February 7, 2023
    Assignee: SAP SE
    Inventors: Laurent Y. Gomez, Jose Marquez, Patrick Duverger
  • Patent number: 11574176
    Abstract: The present disclosure relates to a neuron for an artificial neural network. The neuron comprises a dot product engine operative to: receive a set of weights; receive a set of data inputs based on a set of input data signals; and calculate the dot product of the set of data inputs and the set of weights to generate a dot product engine output. The neuron further comprises an activation function module arranged to apply an activation function to a signal indicative of the dot product engine output to generate a neuron output; and gain control circuitry. The gain control circuitry is operative to control: an input gain applied to the input data signals to generate the set of data inputs; and an output gain applied to the dot product engine output or by the activation function module. The output gain is selected to compensate for the applied input gain.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: February 7, 2023
    Assignee: Cirrus Logic, Inc.
    Inventor: John Paul Lesso
  • Patent number: 11574095
    Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: February 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghoon Myung, Hyunjae Jang, In Huh, Hyeon Kyun Noh, Min-Chul Park, Changwook Jeong