Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.

Abstract: A computing device transmits, to a second node, first consensus voting information for a target block. The device receives, from the second node, second consensus voting information for the target block. The device determines a consensus result for the target block according to the first and second consensus voting information. In accordance with a determination that the consensus result is a consensus success result, the device activates an accounting duration window. The device performs accounting processing on the target block in the predetermined time duration of the accounting duration window. The device receives, from the second node, a first accounting completion message for the target block transmitted by the second node in the accounting duration window. In accordance with a determination that accounting processing on the target block is completed in the accounting duration window, the device transmits a second accounting completion message to the second node.

Abstract: In a general aspect, information is encoded in data qubits in a three-dimensional device lattice. The data qubits reside in multiple layers of the three-dimensional device lattice, and each layer includes a respective two-dimensional device lattice. A three-dimensional color code is applied in the three-dimensional device lattice to detect errors in the data qubits residing in the multiple layers. A two-dimensional color code is applied in the two-dimensional device lattice in each respective layer to detect errors in one or more of the data qubits residing in the respective layer.

Abstract: A memory programming circuit for programming a non-volatile memory device having an array structure includes a plurality of rows, each row having a row index and comprising one or more memory units, each memory unit being configured to receive one or more input signals and to deliver one or more output signals, the memory programming circuit comprising: a first source line connected to the top electrode of the memory units comprised at rows of odd row indices, and a second source line connected to the top electrodes of the memory units comprised at rows of even row indices.

Abstract: A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.

Abstract: A signal processing device and a signal processing method. The signal processing device includes a receiver, a memristor array and a classifier. The receiver is configured to receive a first signal. The memristor array includes a plurality of memristor units, each of the plurality of memristor units includes a memristor, and the memristor array is configured to apply the first signal that has been received to at least one memristor unit of the plurality of memristor units and output a second signal based on a memristor resistance value distribution of the memristor array. The classifier is configured to classify the second signal outputted from the memristor array to obtain a type of the first signal.

Abstract: A neural network circuit includes a memory device in which memristors being variable resistance elements are connected in a matrix and serve as memory elements of the memory device. The neural network circuit further includes a voltage application device arranged to apply a bias voltage to the memory device and current-voltage (I-V) conversion amplification circuits arranged to convert currents flowing via the memory elements into voltages and output the voltage. A feedback resistor of a respective I-V conversion amplification circuit includes a memristor. The feedback resistor of a respective I-V conversion amplification circuit and the memory elements acting as an input resistor of the I-V conversion amplification circuit are connected to align a polarity direction of the memristor of the feedback resistor and polarity directions of the memristors of the memory elements acting as the input resistor.

Abstract: A technology that can enhance the computing performance of a computing system using reservoir computing (RC), includes a computing system which performs computation using a recurrent neural network (RNN) including an input unit, a reservoir unit, and an output unit. The reservoir unit includes a plurality of nodes circularly connected to each other. The circular connection has a weight matrix for determining a weight between the nodes of the plurality of nodes, in which a weight between the nodes closely arranged on the circle is larger than a weight between the nodes arranged away from each other on the circle. The plurality of nodes each have a g value that is a parameter for designating nonlinearity of an activation function of each of the nodes, and that is set so as to periodically change in a direction on the circle.

Abstract: Memristive learning concepts for neuromorphic circuits are described. In one example case, a neuromorphic circuit includes a first oscillatory-based neuron that generates a first oscillatory signal, a diode that rectifies the first oscillatory signal, and a synapse coupled to the diode and including a long-term potentiation (LTP) memristor arranged in parallel with a long-term depression (LTD) memristor. The circuit further includes a difference amplifier coupled to the synapse that generates a difference signal based on a difference between output signals from the LTP and LTD memristors, and a second oscillatory-based neuron electrically coupled to the difference amplifier that generates a second oscillatory signal based on the difference signal. The circuit also includes a feedback circuit that provides a feedback signal to the LTP and LTD memristors based on a difference or error between a target signal and the second oscillatory signal.

Abstract: Accordingly the embodiments herein provide a method for fabricating a neuron oscillator (200a). The neuron oscillator (200a) includes a thermal insulating device connected with a resistor and a capacitor in series to produce self-sustained oscillations, where the resistor and the capacitor are arranged in parallel manner. The neuron oscillator (200a) eliminates a requirement of an additional compensation circuitry for a consistent performance over a time under heating issues. Additionally, an ON/OFF ratio of the neuron oscillator (200a) improves to a broader resistor range. Further, a presence of tunable synaptic memristor functionality of the neuron oscillator (200a) provides a reduced fabrication complexity to a large scale ONN. An input voltage required for the neuron oscillator (200a) is low (2-3 V) which makes it suitable to use with existing circuitries without using any additional converters.

Abstract: Embodiments of the invention provide a computer-readable medium of visual saliency estimation comprising receiving an input video of image frames. Each image frame has one or more channels, and each channel has one or more pixels. The computer-readable medium further comprises, for each channel of each image frame, generating corresponding neural spiking data based on a pixel intensity of each pixel of the channel, generating a corresponding multi-scale data structure based on the corresponding neural spiking data, and extracting a corresponding map of features from the corresponding multi-scale data structure. The multi-scale data structure comprises one or more data layers, wherein each data layer represents a spike representation of pixel intensities of a channel at a corresponding scale. The computer-readable medium further comprises encoding each map of features extracted as neural spikes.

Abstract: Hardware placement of neural networks is provided. In various embodiments, a network description is read. The network description describes a spiking neural network. The neural network is trained. An initial placement of the neural network on a plurality of cores is performed. The cores are located on a plurality of chips. Inter-chip communications are measured based on the initial placement. A final placement of the neural network on the plurality of cores is performed based on the inter-chip communications measurements and the initial placement. The final placement reduces inter-chip communication.

Abstract: Distributed state via cascades of tensor decompositions and neuron activation binding on neuromorphic hardware is provided. In various embodiments, a kernel is divided into a plurality of subkernels. Each subkernel has less than a predetermined size. The plurality of subkernels are distributed, each to one of a plurality of neurosynaptic processors. By each of the plurality of neurosynaptic processors, one of the subkernels is applied to an input to generate a partial convolution. The partial convolutions from each of the plurality of neurosynaptic processors are combined to determine an activation.

Abstract: Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.

Abstract: A device may receive a feature submission identifying a candidate feature for a software application. The device may pre-process the feature submission to reformat data associated with the candidate feature to match a data format associated with stored information regarding past feature submissions. The device may perform natural language processing on the data associated with the candidate feature to determine a semantic meaning of the candidate feature. The device may compare the semantic meaning of the candidate feature with an index of past feature submissions. The device may provide a response indicating whether the candidate feature matches the past feature submissions wherein the response comprises an indication that the candidate feature does not match any past feature submission or information identifying one or more past feature submissions associated with a threshold semantic similarity to the candidate feature.

Abstract: Apparatus and method for improving chemical process efficiency and promoting sharing of chemistry information for guiding and encouraging scientific researchers and institutions to develop and share more efficient chemical processes.

Abstract: Methods of encoding image data for loading into an artificial intelligence (AI) integrated circuit are provided. The AI integrated circuit may have an embedded cellular neural network for implementing AI tasks based on the loaded image data. An encoding method may apply image splitting, principal component analysis (PCA) or a combination thereof to an input image to generate a plurality of output images. Each output image has a size smaller than the size of the input image. The method may load the output images into the AI chip, execute programming instructions contained in the AI chip to generate an image recognition result based on the at least one of the plurality of output images, and output the image recognition result. The encoding method also trains a convolution neural network (CNN) and loads the weights of the CNN into the AI integrated circuit for implementing the AI tasks.

Abstract: Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first memory and second memory. The first memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.

Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.

Abstract: Apparatus for recognition of handwritten Chinese characters contains a bus, an input means connecting to the bus for receiving input imagery data created from a handwritten Chinese character, a Cellular Neural Networks or Cellular Nonlinear Networks (CNN) based integrated circuit operatively connecting to the bus for extracting features out of the input imagery data using pre-trained filter coefficients of a plurality of order convolutional layers stored therein, a memory connecting the bus, the memory being configured for storing weight coefficients of fully-connected (FC) layers, a processing unit connecting to the bus for performing computations of FC layers to classify the extracted features from the CNN based integrated circuit to a particular Chinese character in a predefined Chinese character set, and a display unit connecting to the bus for displaying the particular Chinese character.

Abstract: Systems, methods, and non-transitory computer-readable media can acquire video content for which video feature descriptors are to be determined. The video content can be processed based at least in part on a convolutional neural network including a set of two-dimensional convolutional layers and a set of three-dimensional convolutional layers. One or more outputs can be generated from the convolutional neural network. A plurality of video feature descriptors for the video content can be determined based at least in part on the one or more outputs from the convolutional neural network.

Abstract: Systems, methods, and non-transitory computer-readable media can obtain a set of video frames at a first resolution. Process the set of video frames using a convolutional neural network to output one or more signals, the convolutional neural network including (i) a set of two-dimensional convolutional layers and (ii) a set of three-dimensional convolutional layers, wherein the processing causes the set of video frames to be reduced to a second resolution. Process the one or more signals using a set of three-dimensional de-convolutional layers of the convolutional neural network. Obtain one or more outputs corresponding to the set of video frames from the convolutional neural network.

Abstract: The present invention provides a system comprising a neurosynaptic processing device including multiple neurosynaptic core circuits for parallel processing, and a serial processing device including at least one processor core for serial processing. Each neurosynaptic core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of synapse devices. The system further comprises an interconnect circuit for coupling the neurosynaptic processing device with the serial processing device. The interconnect circuit enables the exchange of data packets between the neurosynaptic processing device and the serial processing device.

Abstract: Example embodiments relate to a synapse circuit connecting neuron circuits by using two memristors so as to enhance symmetry, a neuromorphic circuit using the same, and a unit cell composing the neuromorphic circuit.

Abstract: Embodiments of the invention relate to distributed simulation frameworks that provide reciprocal communication. One embodiment comprises interconnecting neuron groups on different processors via a plurality of reciprocal communication pathways, and facilitating the exchange of reciprocal spiking communication between two different processors using at least one Ineuron module. Each processor includes at least one neuron group. Each neuron group includes at least one electronic neuron.

Abstract: In one embodiment, the present invention provides a method for interconnecting neurons in a neural network. At least one node among a first set of nodes is interconnected to at least one node among a second set of nodes, and nodes of the first and second set are arranged in a lattice. At least one node of the first set represents a sensory-motor modality of the neural network. At least one node of the second set is a union of at least two nodes of the first set. Each node in the lattice has an acyclic digraph comprising multiple vertices and directed edges. Each vertex represents a neuron population. Each directed edge comprises multiple synaptic connections. Vertices in different acyclic digraphs are interconnected using an acyclic bottom-up digraph. The bottom-up digraph has a corresponding acyclic top-down digraph. Vertices in the bottom-up digraph are interconnected to vertices in the top-down digraph.

Abstract: A plurality of chips arranged in a certain layout so as to face free space, and one or more optical elements are included. In the case where signal traffic for electrical communication with a given chip exceeds or is expected to exceed a certain threshold, a plurality of chips involved in communication routing of the excess signal traffic are identified, part of related signal traffic that crosses the plurality of identified chips is converted from an electric signal into an optical signal to re-route the excess signal traffic, and paths of the related signal traffic are dynamically adapted from fixed wired paths between the plurality of chips to optical communication paths formed in the free space.

Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

Abstract: In one embodiment, the present invention provides a method for interconnecting neurons in a neural network. At least one node among a first set of nodes is interconnected to at least one node among a second set of nodes, and nodes of the first and second set are arranged in a lattice. At least one node of the first set represents a sensory-motor modality of the neural network. At least one node of the second set is a union of at least two nodes of the first set. Each node in the lattice has an acyclic digraph comprising multiple vertices and directed edges. Each vertex represents a neuron population. Each directed edge comprises multiple synaptic connections. Vertices in different acyclic digraphs are interconnected using an acyclic bottom-up digraph. The bottom-up digraph has a corresponding acyclic top-down digraph. Vertices in the bottom-up digraph are interconnected to vertices in the top-down digraph.

Abstract: Embodiments of the invention relate to distributed simulation frameworks that provide reciprocal communication. One embodiment comprises interconnecting neuron groups on different processors via a plurality of reciprocal communication pathways, and facilitating the exchange of reciprocal spiking communication between two different processors using at least one Ineuron module. Each processor includes at least one neuron group. Each neuron group includes at least one electronic neuron.

Abstract: In one embodiment, the present invention provides a neural network comprising multiple modalities. Each modality comprises multiple neurons. The neural network further comprises an interconnection lattice for cross-associating signaling between the neurons in different modalities. The interconnection lattice includes a plurality of perception neuron populations along a number of bottom-up signaling pathways, and a plurality of action neuron populations along a number of top-down signaling pathways. Each perception neuron along a bottom-up signaling pathway has a corresponding action neuron along a reciprocal top-down signaling pathway. An input neuron population configured to receive sensory input drives perception neurons along a number of bottom-up signaling pathways. A first set of perception neurons along bottom-up signaling pathways drive a first set of action neurons along top-down signaling pathways.

Abstract: Neuronal networks of electronic neurons interconnected via electronic synapses with synaptic weight normalization. The synaptic weights are based on learning rules for the neuronal network, such that a synaptic weight for a synapse determines the effect of a spiking source neuron on a target neuron connected via the synapse. Each synaptic weight is maintained within a predetermined range by performing synaptic weight normalization for neural network stability.

Abstract: Methods for optimizing the cost of executing a set of tests including finding the optimal ordering of the tests for some important cases such as set of tests having series-parallel structure with no statistical dependencies, and near-optimal orderings for the rest of the cases, such that the resources required for executing the tests are minimized.

Abstract: Methods, apparatuses and systems directed to pattern identification and pattern recognition. In some particular implementations, the invention provides a flexible pattern recognition platform including pattern recognition engines that can be dynamically adjusted to implement specific pattern recognition configurations for individual pattern recognition applications. In some implementations, the present invention also provides for a partition configuration where knowledge elements can be grouped and pattern recognition operations can be individually configured and arranged to allow for multi-level pattern recognition schemes.

Abstract: A computer cluster arranged at a lattice point in a lattice-like interconnection network contains four nodes and an internal communication network. Two nodes can transmit packets to adjacent computer clusters located along the X direction, and the two other nodes can transmit packets to adjacent computer clusters located along the Y direction. Each node directly transmits a packet to an adjacent computer cluster in the direction in which the node can transmit packets, when the destination of the packet is located in the direction. When the destination of a packet to be transmitted from a node is not located in the direction in which the receiving node can transmit packets, the node transfers the packet to one of the other nodes through the internal communication network for transmitting the packet to the destination of the packet through the one of the other nodes.

Abstract: A neuronal network structure including a plurality of automata interconnected one with each other through synaptic links forming a connectivity matrix. The neural network structure acts as a machine that can be operated such that the machine shows different behaviours including periodic and non-periodic patterns, multistable patterns and more complex patterns such as spirals. A method to operate a neuronal network structure.

Abstract: Methods, apparatus, and business processes enabling individual chemists to design, order, and obtain data for multiple experiments or measurements in a timely and cost-effective manner. In particular implementations, the invention includes methods and apparatus for designing sets of custom experiments, ordering the execution of the experiments, communicating the order to a remote laboratory, executing the experiments at that laboratory using high-throughput technologies, and communicating the experimental results to the user.

Abstract: A system is described for matching lattices such as phoneme lattices generated by an automatic speech recognition unit. The system can be used to retrieve files from a database by comparing a query lattice with annotation lattices associated with the data files that can be retrieved, and by retrieving the data files having an annotation lattice most similar to the query lattice.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice. Various platforms can be used to physically implement such a quantum computer. Platforms include an optical lattice, a Josephson junction array, a quantum dot, and a crystal structure. Each platform comprises an appropriate array of associated sites that can be used to approximate a desired Kagome geometry. A charge controller is desirably electrically coupled to the platform so that the array may be manipulated as desired.

Abstract: Computer-readable media having computer-executable instructions and apparatuses categorize documents or corpus of documents. A Tensor Space Model (TSM), which models the text by a higher-order tensor, represents a document or a corpus of documents. Supported by techniques of multilinear algebra, TSM provides a framework for analyzing the multifactor structures. TSM is further supported by operations and presented tools, such as the High-Order Singular Value Decomposition (HOSVD) for a reduction of the dimensions of the higher-order tensor. The dimensionally reduced tensor is compared with tensors that represent possible categories. Consequently, a category is selected for the document or corpus of documents. Experimental results on the dataset for 20 Newsgroups suggest that TSM is advantageous to a Vector Space Model (VSM) for text classification.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such quantum computational systems may include quantum computers, quantum cryptography systems, quantum information processing systems, quantum storage media, and special purpose quantum simulators.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice. A topological quantum computer encodes information in the configurations of different braids. The computer physically weaves braids in the 2D+1 space-time of the lattice, and uses this braiding to carry out calculations. A pair of quasi-particles, such as non-abelian anyons, can be moved around each other in a braid-like path. The quasi-particles can be moved as a result of a magnetic or optical field being applied to them, for example.

Abstract: A method, device, and computer program product for ranking documents using link analysis, with remedies for sinks, including forming a metagraph from an original graph containing a link and a node; and one of reversing a link in the metagraph, and pumping a source in the metagraph.

Abstract: Methods and systems for modifying at least one synapse of a physicallelectromechanical neural network. A physical/electromechanical neural network implemented as an adaptive neural network can be provided, which includes one or more neurons and one or more synapses thereof, wherein the neurons and synapses are formed from a plurality of nanoparticles disposed within a dielectric solution in association with one or more pre-synaptic electrodes and one or more post-synaptic electrodes and an applied electric field. At least one pulse can be generated from one or more of the neurons to one or more of the pre-synaptic electrodes of a succeeding neuron and one or more post-synaptic electrodes of one or more of the neurons of the physical/electromechanical neural network, thereby strengthening at least one nanoparticle of a plurality of nanoparticles disposed within the dielectric solution and at least one synapse thereof.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: A data processor which comprises a line of unit cells of alternating type, each capable of adopting two distinguishable states. The states of the cells of each respective type can be transformed (e.g. switched from one state to the other) by respective stimulae (which act on all cells of that type simultaneously) in dependence upon whether the cells two nearest neighbours in the line are both in mutually the same state or in mutually different states. Binary data bits are each represented by a pattern of states of four adjacent cells, and data is loaded onto the cells so that each bit is spaced by four cells from an adjacent bit. Logical operations can be performed on the data by loading a control unit (a particular pattern of states of six adjacent cells) and then applying the stimulae to transform the states of the cells. The processor can be implemented on a conventional computer by implementing the cells as Boolean variables in an array with the stimulae being update rules applied to the array.

Abstract: A method for recognizing an object image comprises the steps of extracting a candidate for a predetermined object image from an image, and making a judgment as to whether the extracted candidate for the predetermined object image is or is not the predetermined object image. The candidate for the predetermined object image is extracted by causing the center point of a view window, which has a predetermined size, to travel to the position of the candidate for the predetermined object image, and determining an extraction area in accordance with the size and/or the shape of the candidate for the predetermined object image, the center point of the view window being taken as a reference during the determination of the extraction area.