Semiconductor Neural Network Patents (Class 706/33)
  • Patent number: 10726337
    Abstract: In a method for emulation of neuromorphic hardware on a computer processor, the neuromorphic hardware including computing circuits, the computing circuits including neurons and synapses connecting the neurons, the neurons being configured to communicate to each other through the synapses via spikes, the computing circuits being configured to execute in parallel in increments of time, the method includes, for each said time increment, emulating processing of the synapses, emulating processing of the neurons, and recording by the processor the next ones of the spikes for a subset of the neurons on a non-transitory physical medium. The processing of the synapses includes receiving previous ones of the spikes at presynaptic ends of the synapses, and transmitting the received previous ones of the spikes to postsynaptic ends of the synapses. The processing of the neurons includes receiving current ones of the spikes and generating next ones of the spikes.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: July 28, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Corey M. Thibeault, Narayan Srinivasa
  • Patent number: 10726895
    Abstract: A system, comprising: a memory that stores computer-executable components; a processor, operably coupled to the memory, that executes the computer-executable components stored in the memory, wherein the computer-executable components comprise: an expression component that expresses the read current range in an RPU as read current Iwmin and Iwmax, a constant current source component that generates a reference current I, a computing component that subtracts the reference current value within from the read current value to generate an active net current read value that is negative, positive or null; a weighting component that analyzes the active current value and assigns it to a negative, positive or null weight.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seyoung Kim, Tayfun Gokmen, Hyung-Min Lee, Wilfried Haensch
  • Patent number: 10713562
    Abstract: A neuromorphic memory circuit including a programmable resistive memory element, an axon LIF pulse generator to generate an axon LIF pulse, a back propagation pulse generator to generate a back propagation pulse, a postsynaptic capacitor configured to build up a forward propagation LIF charge over time, and a presynaptic capacitor configured to build up a back propagation LIF charge over time. A first transistor activates a first discharge path from the postsynaptic capacitor through the programmable resistive memory element when the axon LIF pulse generator generates the axon LIF pulse. A second transistor activates a second discharge path from the presynaptic capacitor through the programmable resistive memory element when the back propagation pulse generator generates the back propagation pulse.
    Type: Grant
    Filed: June 18, 2016
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: SangBum Kim, Chung H. Lam
  • Patent number: 10698754
    Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 30, 2020
    Assignee: Syntiant
    Inventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
  • Patent number: 10684833
    Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Ruchira Sasanka, Karthik Raman, Konstantinos Krommydas
  • Patent number: 10670749
    Abstract: The transmission system combines a self-contained, wireless seismic acquisition unit and a wireless, line of site, communications unit to form a plurality of individual short-range transmission networks and also a mid-range, line of sight transmission network. Each seismic unit has a power source, a short-range transmitter/receiver disposed within a casing and a geophone disposed within the casing. Each wireless communications unit is formed of an elongated support structure on which is mounted an independent power source, mid-range radio transmitter/receiver; and a short-range transmitter/receiver configured to wirelessly communicate with the short-range transmitter/receiver of the acquisition unit. Preferably, when deployed, the acquisition unit is buried under the surface of the ground, while the wireless communications unit is positioned in the near vicinity of the buried unit so as to vertically protrude above the ground.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 2, 2020
    Assignee: Magseis FF LLC
    Inventors: Clifford H. Ray, Glenn D. Fisseler
  • Patent number: 10672464
    Abstract: A method for achieving a feedforward operation and/or a recurrent operation in an artificial neural network having a self-training learning function. The forgoing artificial neural network (ANN) comprises M×N numbers nonvolatile memory cells that are arranged to form a memory array, and the nonvolatile memory cell can be a non-overlapped implementation (NOI) MOSFET, a RRAM element, a PCM element, a MRAM element, or a SONOS element. By applying this novel method to the ANN, it is able to perform the feedforward and recurrent operations in the M×N numbers of nonvolatile memory cells storing with different bit weights that are formed by injected electrons through the self-training learning function of the ANN.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: June 2, 2020
    Assignee: Chung Yuan Christian University
    Inventors: Syang-Ywan Jeng, Shang-Wei Chou
  • Patent number: 10664747
    Abstract: A synthetic neuronal structure makes use of a semiconductor-metal phase transition material having material regions separated by discontinuities. The discontinuities represent interfaces such that different phases in two adjacent regions result in a metal-semiconductor interface. The interface supports a charge accumulation and a discharge of accumulated charge when an activation energy provided, for example, by electrical current, localized heating or optical energy, reaches a threshold necessary for breakdown of a potential barrier presented by the interface, and thus mimics a leaky integrate-and-fire neuron. With many such interfaces distributed through the structure, the local inputs to a neuron become a weighted sum of energy from neighboring neurons. Thus, different combinations of signals at one or more inputs connected to the structure will favor different neural pathways through the structure, thereby resulting in a neural network.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 26, 2020
    Inventors: Dominic Lepage, Mohamed Chaker
  • Patent number: 10657439
    Abstract: The application provides an operation method and device. Quantized data is looked up to realize an operation, which simplifies the structure and reduces the computation energy consumption of the data, meanwhile, a plurality of operations are realized.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 19, 2020
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD
    Inventors: Shaoli Liu, Xuda Zhou, Zidong Du, Daofu Liu
  • Patent number: 10628732
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Patent number: 10623241
    Abstract: A network device includes a memory storing instructions, and a processor which is capable of executing the instructions causing the network device to receive an input of data including a setting value required for use of the network device in an environment in which the network device is arranged, activate a mode for participating in a mesh network identified by identification information specified previously, by using a wireless communication function, and distribute the input data to a network device other than the own network device via the mesh network.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 14, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Satoshi Takazawa
  • Patent number: 10608429
    Abstract: This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 31, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Tay-Her Tsaur, Cheng-Cheng Yen, Chien-Ming Wu, Cheng-Pang Chan
  • Patent number: 10572799
    Abstract: A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t1. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kohji Hosokawa, Masatoshi Ishii, SangBum Kim, Chung H. Lam, Scott C. Lewis
  • Patent number: 10558910
    Abstract: A neuromorphic device may include: a plurality of pre-synaptic neurons; row lines extending in a row direction from the plurality of pre-synaptic neurons; a plurality of post-synaptic neurons; column lines extended in a column direction from the plurality of post-synaptic neurons; a plurality of synapses arranged at intersections between the row lines and the column lines; a plurality of first control blocks; and first control lines extending from the control blocks. The first control lines may be electrically connected to the plurality of synapses.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Patent number: 10528959
    Abstract: A computer-implemented method for determining a micro-moment value that indicates an optimal time for a customer to receive a targeted advertisement. The method includes receiving, via a network, customer data associated with behavior of a plurality of customers. The method includes determining, via one or more processors, a micro-moment value predicting an optimal time and network location to engage a customer based on the customer data.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 7, 2020
    Assignee: MMS USA HOLDINGS INC.
    Inventor: Samih Fadli
  • Patent number: 10514716
    Abstract: Existing proportional to absolute temperature (PTAT)/complementary-to-absolute-temperature (CTAT) reference voltage circuit requires a large components count and foot print, precise device matching for accuracy and unsatisfactory sensitivity error or variation to temperature and humidity. The present invention relates to a novel approach for such reference voltage circuit based on a self-biased complementary pair of n-type and p-type current field-effect transistors, which provides rail PTAT, rail CTAT and analog reference voltages.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: December 24, 2019
    Assignee: Circuit Seed, LLC
    Inventors: Susan Marya Schober, Robert C. Schober
  • Patent number: 10509999
    Abstract: A neuromorphic device may include: a pre-synaptic neuron; a plurality of post-synaptic neurons; and a plurality of synapses electrically connected to the pre-synaptic neuron and electrically connected to the plurality of post-synaptic neurons. Each of the post-synaptic neurons may include: an integrator; a main comparator having a first input port connected to an output port of the integrator; and a first sub comparator having a first input port connected to the output port of the integrator.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: December 17, 2019
    Assignee: SK HYNIX INC.
    Inventor: Hyung-Dong Lee
  • Patent number: 10489483
    Abstract: A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: November 26, 2019
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Matthew Marinella, Sapan Agarwal
  • Patent number: 10490273
    Abstract: A neuromorphic circuit, chip, and method are provided. The neuromorphic circuit includes a crossbar synaptic array cell. The crossbar synaptic array cell includes a Complimentary Metal-Oxide-Semiconductor (CMOS) transistor having an on-resistance controlled by a gate voltage of the CMOS transistor to update a weight of the crossbar synaptic array cell. The neuromorphic circuit further includes a set of row-lines respectively connecting the synaptic array cell in series to a plurality of pre-synaptic neurons at first ends thereof. The neuromorphic circuit also includes a set of column-lines respectively connecting the synaptic array cell in series to a plurality of post-synaptic neurons at second ends thereof. The gate voltage of the CMOS transistor is controlled by performing a charge sharing technique that updates the weight of the crossbar synaptic array cell using non-overlapping pulses on control lines that are aligned with the set of row lines and the set of column lines.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: November 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Masatoshi Ishii, Kohji Hosokawa, Atsuya Okazaki, Akiyo Iwashina
  • Patent number: 10395165
    Abstract: N processing units (PU) each have an arithmetic unit (AU) that performs an operation on first, second and third inputs to generate a result to store in an accumulator having an output provided to the first input. A weight input is received by the AU second input. A multiplexed register has first, second, third and fourth data inputs and an output received by the third AU input. A first memory provides N weight words to the N weight inputs. A second memory provides N data words to the multiplexed register first data inputs. The multiplexed register output is also received by the second, third, and fourth data input of the multiplexed register one, 2{circumflex over (?)}J, and 2{circumflex over (?)}K PUs away, respectively. The N multiplexed registers collectively operate as an N-word rotater that rotates by one, 2{circumflex over (?)}J, or 2{circumflex over (?)}K words when the control input specifies the second, third, or fourth data input, respectively.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: August 27, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: G. Glenn Henry, Kim C. Houck
  • Patent number: 10360502
    Abstract: A computing device may include a memory to store data that describes a state machine model that includes destination states and source states. The source states may be associated with conditions upon which the state machine model is to transition from a corresponding source state to one of the destination states. The device may also include a processor configured to generate data to describe a state diagram from the data that describes the state machine model. The state diagram may include the graphical symbols and lines. Each of the graphical symbols may represent one of the source states or one of the destination states. The lines may represent transitions and include one or more vertical lines to represent transitions to one of the destination states from more than one of the source states. The graphical symbol may represent the one of the destination states is not adjacent to the graphical symbols to represent the more than one of the source states.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: July 23, 2019
    Assignee: The MathWorks, Inc.
    Inventors: Siddhartha Shankar, Srinath Avadhanula, Vijaya Raghavan, Ebrahim Mehran Mestchian, Yao Ren
  • Patent number: 10318882
    Abstract: An indication of a data source to be used to train a linear prediction model is obtained. The model is to generate predictions using respective parameters assigned to a plurality of features derived from observation records of the data source. The parameter values are stored in a parameter vector. During a particular learning iteration of the training phase of the model, one or more features for which parameters are to be added to the parameter vector are identified. In response to a triggering condition, parameters for one or more features are removed from the parameter vector based on an analysis of relative contributions of the features represented in the parameter vector to the model's predictions. After the parameters are removed, at least one parameter is added to the parameter vector.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: June 11, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Michael Brueckner, Daniel Blick
  • Patent number: 10282001
    Abstract: A conductive film may be provided that includes a base member, a first hard coating layer formed on a surface of the base member, and a conductive layer formed on the first hard coating layer. The conductive layer may include conductors composed of a nano-material forming a network structure.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 7, 2019
    Assignee: LG Electronics Inc.
    Inventors: Yuhee Kim, Yangwook Hur, Jinyoung Choi, Munsu Lee
  • Patent number: 10248675
    Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element may be digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension a second destination neuron may be connected to the first neuron by a second synapse in a second dimension to form linked columns and rows of neuron/synapse circuit elements. In one embodiment, the rows and columns of circuit elements have read registers that are linked together by signal lines and clocked and controlled so as to output columnar data to an output register when a neuron/synapse data value is stored in the read register.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: April 2, 2019
    Assignee: University of Tennessee Research Foundation
    Inventors: J. Douglas Birdwell, Mark E. Dean, Catherine Schuman
  • Patent number: 10224903
    Abstract: A method includes receiving a series of radio frequency (RF) signals, where, from RF signal to RF signal of the series of RF signals, a carrier frequency is changed in accordance with a frequency hopping pattern. The method further includes, while receiving the series of RF signals, sensing an environmental condition by, for a frequency hop of at least some frequency hops of the frequency hopping pattern, adjusting a characteristic of a wireless sensor to maintain proximal alignment of a resonant frequency of the wireless sensor with the carrier frequency corresponding to a present frequency of the at least some frequency hops and generating a value to represent the adjustment of the characteristic, where a set of values is generated for the at least some frequency hops and where the set of values is used to determine a sensed value of the environmental condition.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 5, 2019
    Assignee: RFMicron, Inc.
    Inventors: Shahriar Rokhsaz, Greg Pitner
  • Patent number: 10217046
    Abstract: A neuromorphic processing device has a device input, for receiving an input data signal, and an assemblage of neuron circuits. Each neuron circuit comprises a resistive memory cell which is arranged to store a neuron state, indicated by cell resistance, and to receive neuron input signals for programming cell resistance to vary the neuron state, and a neuron output circuit for supplying a neuron output signal in response to cell resistance traversing a threshold. The device includes an input signal generator, connected to the device input and the assemblage of neuron circuits, for generating neuron input signals for the assemblage in dependence on the input data signal. The device further includes a device output circuit, connected to neuron output circuits of the assemblage, for producing a device output signal dependent on neuron output signals of the assemblage, whereby the processing device exploits stochasticity of resistive memory cells of the assemblage.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evangelos S. Eleftheriou, Manuel Le Gallo, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10164611
    Abstract: A wireless sensor includes a radio frequency (RF) receiving circuit including a plurality of components, where impedances of the plurality of components establish a resonant frequency of the RF receiving circuit. The wireless sensor further includes a sensing element that when exposed to an environmental condition, affects the resonant frequency of the RF receiving circuit. The wireless sensor further includes a processing module that is operable to determine a first value for an adjustable element of a plurality of elements for a known environmental condition based on the resonant frequency and the carrier frequency, determine a second value for the adjustable element for an unknown environmental condition based on the resonant frequency and the carrier frequency, and determine a difference between the first and second values that corresponds to a change between the known environmental condition and the unknown environmental condition.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 25, 2018
    Assignee: RFMicron, Inc.
    Inventor: Shahriar Rokhsaz
  • Patent number: 10141069
    Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: November 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Yoshiyuki Kurokawa
  • Patent number: 10102691
    Abstract: This disclosure relates to a distributed data center that includes resources carried by a fleet of vehicles. The system includes sensors configured to generate output signals conveying information related to the vehicles. The system may detect vehicle events based on the information conveyed by the output signals. The system includes a remote computing server configured to present a user interface to a user. Through the user interface, the user may query information from one or more vehicles in the fleet. The distributed query is transmitted to individual vehicles, and results are locally processed in accordance with response constraints and subsequently transmitted back to the remote computing server for presentation to the user.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: October 16, 2018
    Assignee: SmartDrive Systems, Inc.
    Inventors: Reza Ghanbari, Nicholas Shayne Brookins, David Forney, Mark Freitas, Daniel Andrew Deninger, Jeffrey Griswold, Jason Palmer
  • Patent number: 10095718
    Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element or component thereof may be analog or digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse. The DANNA may thus form multiple levels of neuron and synapse circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the circuit element selectively functioning as one of a neuron and a synapse.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: October 9, 2018
    Assignee: University of Tennessee Research Foundation
    Inventors: J. Douglas Birdwell, Mark E. Dean, Catherine Schuman
  • Patent number: 10055434
    Abstract: A digital circuit element of a two dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the digital circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such digital circuit elements, a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse thus forming multiple levels of neuron and synapse digital circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the digital circuit element selectively functioning as one of a neuron and a synapse.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: August 21, 2018
    Assignee: University of Tennessee Research Foundation
    Inventors: J. Douglas Birdwell, Mark E. Dean, Catherine Schuman
  • Patent number: 10044224
    Abstract: An object is to provide a power feeding device, a power feeding system, and a power feeding method which are more convenient for a power feeding user at the power receiving end. The power feeding device includes a means of controlling a frequency of a power signal transmitted to a power receiver, based on a proportion of signals, among power signals output to an antenna circuit, that return from the power receiver to the antenna circuit without feeding power to the power receiver.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Kamata, Misako Sato, Shuhei Maeda
  • Patent number: 9888081
    Abstract: Automation is effected for various remote circuits. As may be implemented in accordance with one or more embodiments, environmental characteristics are monitored at each of a plurality of remote systems located at different geographical regions (e.g., remote agricultural systems, or other equipment) and controlled by one or more local/master systems. Data indicative of the monitored environmental characteristic is communicated and used for controlling operational equipment, based upon operational instructions communicated from the master system. These communications are carried out by monitoring communication characteristics of communications paths between the master system and the remote systems, with some communication paths including one or more of the remote systems via which communications are passed (e.g., relayed). One of the communication paths is selected based upon the monitored communication characteristics, and used for communicating the operational instructions with the remote systems.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: February 6, 2018
    Assignee: Smart Farm Systems, Inc.
    Inventors: Robert P. Farinelli, Jr., Steve Christensen, James J. Suchora, Ryan Heringer, Brandon Finch, Gary Sterling
  • Patent number: 9847126
    Abstract: A method of increasing a read margin in a memory cell may include sensing an input current created from the application of a read voltage across a memristive device, squaring the input current, and comparing the squared input current to a reference current. A memristive device may include a memristor and a sense amplifier communicatively coupled to the memristor wherein a sensed input current created from the application of a reference voltage across a memristor is squared and wherein the sense amplifier compares the squared input current to a reference current.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: December 19, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, R. Stanley Williams
  • Patent number: 9830981
    Abstract: A neuromorphic memory circuit including a programmable resistive memory element, an axon LIF line to transmit an axon LIF pulse, and a dendrite LIF line to build up a dendrite LIF charge over time. A first transistor provides a discharge path for the dendrite LIF charge through the programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. An axon STDP line transmits an axon STDP pulse. The axon STDP pulse is longer than the axon LIF pulse. A dendrite STDP line is configured to transmit a dendrite STDP pulse after voltage at the dendrite LIF line falls below a threshold voltage. A second transistor is coupled to the axon STDP line and the programmable resistive memory element. The second transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: SangBum Kim, Chung H. Lam
  • Patent number: 9830982
    Abstract: A method for operating a neuromorphic memory circuit. The method includes accumulating a dendrite LIF charge over time on a conductive dendrite LIF line. A first transmitting operation transmits an axon LIF pulse on a conductive axon LIF line. A first switching operation switches on a LIF transistor by the axon LIF pulse such that the LIF transistor provides a discharge path for the dendrite LIF charge through a programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. A second transmitting operation transmits a dendrite STDP pulse if the dendrite LIF charge falls below a threshold voltage. A third transmitting operation transmits an axon STDP pulse on a conductive axon STDP line. A second switching operation switches on a STDP transistor by the axon STDP pulse. The STDP transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: SangBum Kim, Chung H. Lam
  • Patent number: 9773204
    Abstract: A neuromorphic device having synapses may include: a top electrode; a bottom electrode; and a variable resistive layer disposed between the top electrode and the bottom electrode. The variable resistive layer may include a plurality of carrier traps distributed at multiple energy levels.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 26, 2017
    Assignee: SK HYNIX INC.
    Inventor: Hyung-Dong Lee
  • Patent number: 9712154
    Abstract: A voltage generation circuit includes a voltage generator initialized in response to a first power on reset signal, and generates an internal voltage on an output node using an external voltage; and a pull-down driving unit which pull-down drives the output node in response to a second power on reset signal delayed from the first power on reset signal.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 18, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jung-Ung Kim
  • Patent number: 9712895
    Abstract: A device comprising: at least one input sensor, at least one output transducer, a wireless communication module, and a processor configured to receive a local control parameter from the input sensor or a remote control parameter from a remote module communicating with the processor via the wireless communication module, and selecting one a of a plurality of operational configurations de-pending on the local and remote control parameters, each of the plurality of operational configurations including a predetermined threshold for a sensing parameter received from the input sensor, and an output response if the sensing parameter breaches the threshold.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 18, 2017
    Assignee: Singapore University of Technology and Design
    Inventors: Kian Peen Yeo, Suranga Chandima Nanayakkara
  • Patent number: 9547819
    Abstract: A synapse for a neuromorphic network is provided. The synapse includes a time-delay portion having a first end and a second end, a first actuator located at the first end and in operational contact with the time-delay portion, and a second actuator located at the second end and in operational contact with the time-delay portion. The time-delay portion is formed from a phase change material wherein a change in the material of the time-delay portion alters a propagation time of a signal transmitted from the first actuator to the second actuator.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: January 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bernd W. Gotsmann, Siegfried F. Karg, Volker Schmidt
  • Patent number: 9479392
    Abstract: A system of using a drone for network connectivity, the system may comprise: a connectivity module to: detect an error associated with network traffic on a network connection utilized by a user device; query a connection datastore to retrieve at least one access point location that at least one device of the user has utilized within a predetermined period; a drone coordination module to: transmit configuration settings to a drone, the configuration settings including the at least one access point location and a mode of operation for the drone; and route at least a portion of the network traffic of the user device to the drone for transmission according to the configuration settings.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Glen J. Anderson, Kathy Yuen, Jamie Sherman, Lenitra M. Durham, Richard Beckwith
  • Patent number: 9412064
    Abstract: Apparatus and methods for event based communication in a spiking neuron network. The network may comprise units communicating by spikes via synapses. The spikes may communicate a payload data. The data may comprise one or more bits. The payload may be stored in a buffer of a pre-synaptic unit and be configured to accessed by the post-synaptic unit. Spikes of different payload may cause different actions by the recipient unit. Sensory input spikes may cause postsynaptic response and trigger connection efficacy update. Teaching input spikes trigger the efficacy update without causing the post-synaptic response.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: August 9, 2016
    Assignee: QUALCOMM TECHNOLOGIES INC.
    Inventors: Botond Szatmary, Micah Richert, Oleg Sinyavskiy, Eugene Izhikevich
  • Patent number: 9165242
    Abstract: Disclosed is a semiconductor device used to embody a neuromorphic computation system and operation method thereof. By comprising a floating body as a short-term memory means electrically isolated from the surroundings and a long-term memory means formed at one side of the floating body not formed of a source, a drain and a gate, a low power synaptic semiconductor device is provided, which can be mimic not only the short-term memory in a nervous system of a living body by an impact ionization, but also the short- and long-term memory transition property and the causal inference property of a living body due to the time difference of signals of the pre- and post-synaptic neurons.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: October 20, 2015
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Byung-Gook Park, Hyungjin Kim, Garam Kim, Jung Han Lee, Min-Woo Kwon
  • Patent number: 9147156
    Abstract: Apparatus and methods for efficient synaptic update in a network such as a spiking neural network. In one embodiment, the post-synaptic updates, in response to generation of a post-synaptic pulse by a post-synaptic unit, are delayed until a subsequent pre-synaptic pulse is received by the unit. Pre-synaptic updates are performed first following by the post-synaptic update, thus ensuring synaptic connection status is up-to-date. The delay update mechanism is used in conjunction with system “flush” events in order to ensure accurate network operation, and prevent loss of information under a variety of pre-synaptic and post-synaptic unit firing rates. A large network partition mechanism is used in one variant with network processing apparatus in order to enable processing of network signals in a limited functionality embedded hardware environment.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 29, 2015
    Assignee: QUALCOMM TECHNOLOGIES INC.
    Inventors: Eugene M. Izhikevich, Filip Piekniewski, Jayram Moorkanikara Nageswaran, Jeffrey Alexander Levin, Venkat Rangan, Erik Christopher Malone
  • Patent number: 9015094
    Abstract: A delay generator comprises at least one programmable resistor RPCM made of a chalcogenide-based phase-change material, said resistor RPCM being initialized, so as to generate a delay, in a way such that the resistance of the resistor RPCM equals a pre-set initial value R0 and such that the chalcogenide is in the amorphous phase, and a comparator comparing a reference electrical quantity that is stable over time with a variable electrical quantity representative of the resistance of the programmable resistor RPCM, the comparator generating a singularity signal s, said singularity being generated when the difference between the two electrical quantities changes sign.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 21, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Manan Suri, Barbara De Salvo
  • Publication number: 20150106316
    Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element may be digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension a second destination neuron may be connected to the first neuron by a second synapse in a second dimension to form linked columns and rows of neuron/synapse circuit elements. In one embodiment, the rows and columns of circuit elements have read registers that are linked together by signal lines and clocked and controlled so as to output columnar data to an output register when a neuron/synapse data value is stored in the read register.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 16, 2015
    Inventors: J. Douglas Birdwell, Mark E. Dean, Catherine Schuman
  • Publication number: 20150100532
    Abstract: A plurality of synapse determination circuits are provided on a one-to-one basis for a plurality of gate electrodes of a multi-input gate electrode in a neuron element. With respect to first image regions where “1” is repeatedly inputted in correspondence with group information, the synapse determination circuits corresponding to the first image regions are excitatory synapses. With respect to second image regions where “0” is repeatedly inputted in correspondence with the group information, the synapse determination circuits corresponding to the second image regions are inhibitory synapses.
    Type: Application
    Filed: August 11, 2014
    Publication date: April 9, 2015
    Inventor: Hitoshi YAMAGUCHI
  • Publication number: 20150049938
    Abstract: Provided us a visual cortical circuit apparatus comprising: a current mirror unit which uses a transistor as a current source to generate a current having the same size as that of a reaction; a transconductance unit which takes, as an input, the current generated by the current mirror unit and outputs a voltage using a transconductance; and a buffer unit for converting the voltage output from the transconductance unit into a current and buffering the current.
    Type: Application
    Filed: January 24, 2013
    Publication date: February 19, 2015
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Il Song Han, Woo Joon Han
  • Patent number: 8909577
    Abstract: A neuromorphic data processing device comprising a plurality of spiking neurons, with each of these neurons comprising: an integrator designed to receive successive analog pulses each having a certain value, and accumulate the values of the pulses received in a recorded value, referred to as accumulation value, and a discharger designed to emit a pulse, referred to as discharge pulse, according to the accumulation value, and a silicon support having two surfaces, the neurons being carried out on at least one of the two surfaces, the integrator of each neuron comprising a metal via of the TSV type between the two surfaces of the silicon support, the metal via of the TSV type forming a capacitor with the silicon support and having an electric potential forming the accumulation value wherein the values of the pulses received are accumulated and according to which the discharge pulse is emitted.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: December 9, 2014
    Assignee: Commissariat à l'énergie et aux énergies alternatives
    Inventors: Rodolphe Heliot, Marc Duranton, Antoine Joubert
  • Patent number: 8898097
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno