Semiconductor Neural Network Patents (Class 706/33)
  • Patent number: 10360502
    Abstract: A computing device may include a memory to store data that describes a state machine model that includes destination states and source states. The source states may be associated with conditions upon which the state machine model is to transition from a corresponding source state to one of the destination states. The device may also include a processor configured to generate data to describe a state diagram from the data that describes the state machine model. The state diagram may include the graphical symbols and lines. Each of the graphical symbols may represent one of the source states or one of the destination states. The lines may represent transitions and include one or more vertical lines to represent transitions to one of the destination states from more than one of the source states. The graphical symbol may represent the one of the destination states is not adjacent to the graphical symbols to represent the more than one of the source states.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: July 23, 2019
    Assignee: The MathWorks, Inc.
    Inventors: Siddhartha Shankar, Srinath Avadhanula, Vijaya Raghavan, Ebrahim Mehran Mestchian, Yao Ren
  • Patent number: 10318882
    Abstract: An indication of a data source to be used to train a linear prediction model is obtained. The model is to generate predictions using respective parameters assigned to a plurality of features derived from observation records of the data source. The parameter values are stored in a parameter vector. During a particular learning iteration of the training phase of the model, one or more features for which parameters are to be added to the parameter vector are identified. In response to a triggering condition, parameters for one or more features are removed from the parameter vector based on an analysis of relative contributions of the features represented in the parameter vector to the model's predictions. After the parameters are removed, at least one parameter is added to the parameter vector.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: June 11, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Michael Brueckner, Daniel Blick
  • Patent number: 10282001
    Abstract: A conductive film may be provided that includes a base member, a first hard coating layer formed on a surface of the base member, and a conductive layer formed on the first hard coating layer. The conductive layer may include conductors composed of a nano-material forming a network structure.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 7, 2019
    Assignee: LG Electronics Inc.
    Inventors: Yuhee Kim, Yangwook Hur, Jinyoung Choi, Munsu Lee
  • Patent number: 10248675
    Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element may be digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension a second destination neuron may be connected to the first neuron by a second synapse in a second dimension to form linked columns and rows of neuron/synapse circuit elements. In one embodiment, the rows and columns of circuit elements have read registers that are linked together by signal lines and clocked and controlled so as to output columnar data to an output register when a neuron/synapse data value is stored in the read register.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: April 2, 2019
    Assignee: University of Tennessee Research Foundation
    Inventors: J. Douglas Birdwell, Mark E. Dean, Catherine Schuman
  • Patent number: 10224903
    Abstract: A method includes receiving a series of radio frequency (RF) signals, where, from RF signal to RF signal of the series of RF signals, a carrier frequency is changed in accordance with a frequency hopping pattern. The method further includes, while receiving the series of RF signals, sensing an environmental condition by, for a frequency hop of at least some frequency hops of the frequency hopping pattern, adjusting a characteristic of a wireless sensor to maintain proximal alignment of a resonant frequency of the wireless sensor with the carrier frequency corresponding to a present frequency of the at least some frequency hops and generating a value to represent the adjustment of the characteristic, where a set of values is generated for the at least some frequency hops and where the set of values is used to determine a sensed value of the environmental condition.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 5, 2019
    Assignee: RFMicron, Inc.
    Inventors: Shahriar Rokhsaz, Greg Pitner
  • Patent number: 10217046
    Abstract: A neuromorphic processing device has a device input, for receiving an input data signal, and an assemblage of neuron circuits. Each neuron circuit comprises a resistive memory cell which is arranged to store a neuron state, indicated by cell resistance, and to receive neuron input signals for programming cell resistance to vary the neuron state, and a neuron output circuit for supplying a neuron output signal in response to cell resistance traversing a threshold. The device includes an input signal generator, connected to the device input and the assemblage of neuron circuits, for generating neuron input signals for the assemblage in dependence on the input data signal. The device further includes a device output circuit, connected to neuron output circuits of the assemblage, for producing a device output signal dependent on neuron output signals of the assemblage, whereby the processing device exploits stochasticity of resistive memory cells of the assemblage.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evangelos S. Eleftheriou, Manuel Le Gallo, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10164611
    Abstract: A wireless sensor includes a radio frequency (RF) receiving circuit including a plurality of components, where impedances of the plurality of components establish a resonant frequency of the RF receiving circuit. The wireless sensor further includes a sensing element that when exposed to an environmental condition, affects the resonant frequency of the RF receiving circuit. The wireless sensor further includes a processing module that is operable to determine a first value for an adjustable element of a plurality of elements for a known environmental condition based on the resonant frequency and the carrier frequency, determine a second value for the adjustable element for an unknown environmental condition based on the resonant frequency and the carrier frequency, and determine a difference between the first and second values that corresponds to a change between the known environmental condition and the unknown environmental condition.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 25, 2018
    Assignee: RFMicron, Inc.
    Inventor: Shahriar Rokhsaz
  • Patent number: 10141069
    Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: November 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Yoshiyuki Kurokawa
  • Patent number: 10102691
    Abstract: This disclosure relates to a distributed data center that includes resources carried by a fleet of vehicles. The system includes sensors configured to generate output signals conveying information related to the vehicles. The system may detect vehicle events based on the information conveyed by the output signals. The system includes a remote computing server configured to present a user interface to a user. Through the user interface, the user may query information from one or more vehicles in the fleet. The distributed query is transmitted to individual vehicles, and results are locally processed in accordance with response constraints and subsequently transmitted back to the remote computing server for presentation to the user.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: October 16, 2018
    Assignee: SmartDrive Systems, Inc.
    Inventors: Reza Ghanbari, Nicholas Shayne Brookins, David Forney, Mark Freitas, Daniel Andrew Deninger, Jeffrey Griswold, Jason Palmer
  • Patent number: 10095718
    Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element or component thereof may be analog or digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse. The DANNA may thus form multiple levels of neuron and synapse circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the circuit element selectively functioning as one of a neuron and a synapse.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: October 9, 2018
    Assignee: University of Tennessee Research Foundation
    Inventors: J. Douglas Birdwell, Mark E. Dean, Catherine Schuman
  • Patent number: 10055434
    Abstract: A digital circuit element of a two dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the digital circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such digital circuit elements, a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse thus forming multiple levels of neuron and synapse digital circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the digital circuit element selectively functioning as one of a neuron and a synapse.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: August 21, 2018
    Assignee: University of Tennessee Research Foundation
    Inventors: J. Douglas Birdwell, Mark E. Dean, Catherine Schuman
  • Patent number: 10044224
    Abstract: An object is to provide a power feeding device, a power feeding system, and a power feeding method which are more convenient for a power feeding user at the power receiving end. The power feeding device includes a means of controlling a frequency of a power signal transmitted to a power receiver, based on a proportion of signals, among power signals output to an antenna circuit, that return from the power receiver to the antenna circuit without feeding power to the power receiver.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Kamata, Misako Sato, Shuhei Maeda
  • Patent number: 9888081
    Abstract: Automation is effected for various remote circuits. As may be implemented in accordance with one or more embodiments, environmental characteristics are monitored at each of a plurality of remote systems located at different geographical regions (e.g., remote agricultural systems, or other equipment) and controlled by one or more local/master systems. Data indicative of the monitored environmental characteristic is communicated and used for controlling operational equipment, based upon operational instructions communicated from the master system. These communications are carried out by monitoring communication characteristics of communications paths between the master system and the remote systems, with some communication paths including one or more of the remote systems via which communications are passed (e.g., relayed). One of the communication paths is selected based upon the monitored communication characteristics, and used for communicating the operational instructions with the remote systems.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: February 6, 2018
    Assignee: Smart Farm Systems, Inc.
    Inventors: Robert P. Farinelli, Jr., Steve Christensen, James J. Suchora, Ryan Heringer, Brandon Finch, Gary Sterling
  • Patent number: 9847126
    Abstract: A method of increasing a read margin in a memory cell may include sensing an input current created from the application of a read voltage across a memristive device, squaring the input current, and comparing the squared input current to a reference current. A memristive device may include a memristor and a sense amplifier communicatively coupled to the memristor wherein a sensed input current created from the application of a reference voltage across a memristor is squared and wherein the sense amplifier compares the squared input current to a reference current.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: December 19, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, R. Stanley Williams
  • Patent number: 9830981
    Abstract: A neuromorphic memory circuit including a programmable resistive memory element, an axon LIF line to transmit an axon LIF pulse, and a dendrite LIF line to build up a dendrite LIF charge over time. A first transistor provides a discharge path for the dendrite LIF charge through the programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. An axon STDP line transmits an axon STDP pulse. The axon STDP pulse is longer than the axon LIF pulse. A dendrite STDP line is configured to transmit a dendrite STDP pulse after voltage at the dendrite LIF line falls below a threshold voltage. A second transistor is coupled to the axon STDP line and the programmable resistive memory element. The second transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: SangBum Kim, Chung H. Lam
  • Patent number: 9830982
    Abstract: A method for operating a neuromorphic memory circuit. The method includes accumulating a dendrite LIF charge over time on a conductive dendrite LIF line. A first transmitting operation transmits an axon LIF pulse on a conductive axon LIF line. A first switching operation switches on a LIF transistor by the axon LIF pulse such that the LIF transistor provides a discharge path for the dendrite LIF charge through a programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. A second transmitting operation transmits a dendrite STDP pulse if the dendrite LIF charge falls below a threshold voltage. A third transmitting operation transmits an axon STDP pulse on a conductive axon STDP line. A second switching operation switches on a STDP transistor by the axon STDP pulse. The STDP transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: SangBum Kim, Chung H. Lam
  • Patent number: 9773204
    Abstract: A neuromorphic device having synapses may include: a top electrode; a bottom electrode; and a variable resistive layer disposed between the top electrode and the bottom electrode. The variable resistive layer may include a plurality of carrier traps distributed at multiple energy levels.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 26, 2017
    Assignee: SK HYNIX INC.
    Inventor: Hyung-Dong Lee
  • Patent number: 9712154
    Abstract: A voltage generation circuit includes a voltage generator initialized in response to a first power on reset signal, and generates an internal voltage on an output node using an external voltage; and a pull-down driving unit which pull-down drives the output node in response to a second power on reset signal delayed from the first power on reset signal.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 18, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jung-Ung Kim
  • Patent number: 9712895
    Abstract: A device comprising: at least one input sensor, at least one output transducer, a wireless communication module, and a processor configured to receive a local control parameter from the input sensor or a remote control parameter from a remote module communicating with the processor via the wireless communication module, and selecting one a of a plurality of operational configurations de-pending on the local and remote control parameters, each of the plurality of operational configurations including a predetermined threshold for a sensing parameter received from the input sensor, and an output response if the sensing parameter breaches the threshold.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 18, 2017
    Assignee: Singapore University of Technology and Design
    Inventors: Kian Peen Yeo, Suranga Chandima Nanayakkara
  • Patent number: 9547819
    Abstract: A synapse for a neuromorphic network is provided. The synapse includes a time-delay portion having a first end and a second end, a first actuator located at the first end and in operational contact with the time-delay portion, and a second actuator located at the second end and in operational contact with the time-delay portion. The time-delay portion is formed from a phase change material wherein a change in the material of the time-delay portion alters a propagation time of a signal transmitted from the first actuator to the second actuator.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: January 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bernd W. Gotsmann, Siegfried F. Karg, Volker Schmidt
  • Patent number: 9479392
    Abstract: A system of using a drone for network connectivity, the system may comprise: a connectivity module to: detect an error associated with network traffic on a network connection utilized by a user device; query a connection datastore to retrieve at least one access point location that at least one device of the user has utilized within a predetermined period; a drone coordination module to: transmit configuration settings to a drone, the configuration settings including the at least one access point location and a mode of operation for the drone; and route at least a portion of the network traffic of the user device to the drone for transmission according to the configuration settings.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Glen J. Anderson, Kathy Yuen, Jamie Sherman, Lenitra M. Durham, Richard Beckwith
  • Patent number: 9412064
    Abstract: Apparatus and methods for event based communication in a spiking neuron network. The network may comprise units communicating by spikes via synapses. The spikes may communicate a payload data. The data may comprise one or more bits. The payload may be stored in a buffer of a pre-synaptic unit and be configured to accessed by the post-synaptic unit. Spikes of different payload may cause different actions by the recipient unit. Sensory input spikes may cause postsynaptic response and trigger connection efficacy update. Teaching input spikes trigger the efficacy update without causing the post-synaptic response.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: August 9, 2016
    Assignee: QUALCOMM TECHNOLOGIES INC.
    Inventors: Botond Szatmary, Micah Richert, Oleg Sinyavskiy, Eugene Izhikevich
  • Patent number: 9165242
    Abstract: Disclosed is a semiconductor device used to embody a neuromorphic computation system and operation method thereof. By comprising a floating body as a short-term memory means electrically isolated from the surroundings and a long-term memory means formed at one side of the floating body not formed of a source, a drain and a gate, a low power synaptic semiconductor device is provided, which can be mimic not only the short-term memory in a nervous system of a living body by an impact ionization, but also the short- and long-term memory transition property and the causal inference property of a living body due to the time difference of signals of the pre- and post-synaptic neurons.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: October 20, 2015
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Byung-Gook Park, Hyungjin Kim, Garam Kim, Jung Han Lee, Min-Woo Kwon
  • Patent number: 9147156
    Abstract: Apparatus and methods for efficient synaptic update in a network such as a spiking neural network. In one embodiment, the post-synaptic updates, in response to generation of a post-synaptic pulse by a post-synaptic unit, are delayed until a subsequent pre-synaptic pulse is received by the unit. Pre-synaptic updates are performed first following by the post-synaptic update, thus ensuring synaptic connection status is up-to-date. The delay update mechanism is used in conjunction with system “flush” events in order to ensure accurate network operation, and prevent loss of information under a variety of pre-synaptic and post-synaptic unit firing rates. A large network partition mechanism is used in one variant with network processing apparatus in order to enable processing of network signals in a limited functionality embedded hardware environment.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 29, 2015
    Assignee: QUALCOMM TECHNOLOGIES INC.
    Inventors: Eugene M. Izhikevich, Filip Piekniewski, Jayram Moorkanikara Nageswaran, Jeffrey Alexander Levin, Venkat Rangan, Erik Christopher Malone
  • Patent number: 9015094
    Abstract: A delay generator comprises at least one programmable resistor RPCM made of a chalcogenide-based phase-change material, said resistor RPCM being initialized, so as to generate a delay, in a way such that the resistance of the resistor RPCM equals a pre-set initial value R0 and such that the chalcogenide is in the amorphous phase, and a comparator comparing a reference electrical quantity that is stable over time with a variable electrical quantity representative of the resistance of the programmable resistor RPCM, the comparator generating a singularity signal s, said singularity being generated when the difference between the two electrical quantities changes sign.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 21, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Manan Suri, Barbara De Salvo
  • Publication number: 20150106316
    Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element may be digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension a second destination neuron may be connected to the first neuron by a second synapse in a second dimension to form linked columns and rows of neuron/synapse circuit elements. In one embodiment, the rows and columns of circuit elements have read registers that are linked together by signal lines and clocked and controlled so as to output columnar data to an output register when a neuron/synapse data value is stored in the read register.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 16, 2015
    Inventors: J. Douglas Birdwell, Mark E. Dean, Catherine Schuman
  • Publication number: 20150100532
    Abstract: A plurality of synapse determination circuits are provided on a one-to-one basis for a plurality of gate electrodes of a multi-input gate electrode in a neuron element. With respect to first image regions where “1” is repeatedly inputted in correspondence with group information, the synapse determination circuits corresponding to the first image regions are excitatory synapses. With respect to second image regions where “0” is repeatedly inputted in correspondence with the group information, the synapse determination circuits corresponding to the second image regions are inhibitory synapses.
    Type: Application
    Filed: August 11, 2014
    Publication date: April 9, 2015
    Inventor: Hitoshi YAMAGUCHI
  • Publication number: 20150049938
    Abstract: Provided us a visual cortical circuit apparatus comprising: a current mirror unit which uses a transistor as a current source to generate a current having the same size as that of a reaction; a transconductance unit which takes, as an input, the current generated by the current mirror unit and outputs a voltage using a transconductance; and a buffer unit for converting the voltage output from the transconductance unit into a current and buffering the current.
    Type: Application
    Filed: January 24, 2013
    Publication date: February 19, 2015
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Il Song Han, Woo Joon Han
  • Patent number: 8909577
    Abstract: A neuromorphic data processing device comprising a plurality of spiking neurons, with each of these neurons comprising: an integrator designed to receive successive analog pulses each having a certain value, and accumulate the values of the pulses received in a recorded value, referred to as accumulation value, and a discharger designed to emit a pulse, referred to as discharge pulse, according to the accumulation value, and a silicon support having two surfaces, the neurons being carried out on at least one of the two surfaces, the integrator of each neuron comprising a metal via of the TSV type between the two surfaces of the silicon support, the metal via of the TSV type forming a capacitor with the silicon support and having an electric potential forming the accumulation value wherein the values of the pulses received are accumulated and according to which the discharge pulse is emitted.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: December 9, 2014
    Assignee: Commissariat à l'énergie et aux énergies alternatives
    Inventors: Rodolphe Heliot, Marc Duranton, Antoine Joubert
  • Patent number: 8898097
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20140344200
    Abstract: A method for creating on chip analog mathematical engines is provided utilizing a neural network with a switched capacitor structure to implement coefficients for weighted connections and error functions for the neural network. The neural networks are capable of any transfer function, learning, doing pattern recognition, clustering, control or many other functions. The switched capacitor charge controls allow for nodal control of charge transfer based switched capacitor circuits. The method reduces reliance on passive component programmable arrays to produce programmable switched capacitor circuit coefficients. The switched capacitor circuits are dynamically scaled without having to rely on switched in unit passives, such as unit capacitors, and the complexities of switching these capacitors into and out of circuit.
    Type: Application
    Filed: March 15, 2014
    Publication date: November 20, 2014
    Inventor: DAVID SCHIE
  • Patent number: 8868477
    Abstract: Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Coproration
    Inventors: Steven K. Esser, Dharmendra S. Modha
  • Patent number: 8856055
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Patent number: 8843426
    Abstract: Certain aspects of the present disclosure present a technique for primary visual cortex (V1) cell training and operation. The present disclosure proposes a model structure of V1 cells and retinal ganglion cells (RGCs), and an efficient method of training connectivity between these two layers of cells such that the proposed method leads to an autonomous formation of feature detectors within the V1 layer. The proposed approach enables a hardware-efficient and biological-plausible implementation of image recognition and motion detection systems.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: September 23, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Vladimir Aparin
  • Patent number: 8832009
    Abstract: CMOS-memristor circuit is constructed to behave as a trainable artificial synapse for neuromorphic hardware systems. The invention relies on the memristance of a memristor at the input side of the device to act as a reconfigurable weight that is adjusted to realize a desired function. The invention relies on charge sharing at the output to enable the summation of signals from multiple synapses at the input node of a neuron circuit, implemented using a CMOS amplifier circuit. The combination of several memristive synapses and a neuron circuit constitute a neuromorphic circuit capable of learning and implementing a multitude of possible functionalities.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: September 9, 2014
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Garrett S. Rose, Robinson E. Pino, Qing Wu
  • Publication number: 20140172763
    Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.
    Type: Application
    Filed: December 31, 2013
    Publication date: June 19, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Douglas A. Palmer, Michael Florea
  • Patent number: 8669785
    Abstract: Logic circuits using neuristors is described. In an example, a circuit includes a plurality of neuristors each producing an output voltage spike in response to a super-threshold input voltage. A plurality of impedances couple the plurality of neuristors to form at least one input and an output, the output selectively providing an output voltage spike based on a logical operation of at least one input voltage at the at least one input.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: March 11, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Matthew D. Pickett
  • Publication number: 20140067743
    Abstract: Disclosed is a semiconductor device used to embody a neuromorphic computation system and operation method thereof. By comprising a floating body as a short-term memory means electrically isolated from the surroundings and a long-term memory means formed at one side of the floating body not formed of a source, a drain and a gate, a low power synaptic semiconductor device is provided, which can be mimic not only the short-term memory in a nervous system of a living body by an impact ionization, but also the short- and long-term memory transition property and the causal inference property of a living body due to the time difference of signals of the pre- and post-synaptic neurons.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 6, 2014
    Applicant: Seoul National University R&DB FOUNDATION
    Inventors: Byung-Gook PARK, Hyungjin KIM, Garam KIM, Jung Han LEE, Min-Woo KWON
  • Patent number: 8600919
    Abstract: A neuromorphic circuit performs functions representative of spiking timing dependent plasticity of a synapse.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: December 3, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Chi-Sang Poon, Joshua Jen Choa Monzon, Kuan Zhou
  • Publication number: 20130311414
    Abstract: A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a predetermined pulse voltage, and a first input signal has a waveform of the predetermined pulse voltage. For a period having a predetermined duration of the predetermined pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element, the first input signal is permitted to be input to the control electrode of the variable resistance element, to change the resistance value of the variable resistance element due to an electric potential difference generated between the first electrode and the control electrode which occurs depending on an input timing of the first input signal with respect to the period during which the first input signal is permitted to be input to the control electrode.
    Type: Application
    Filed: July 25, 2013
    Publication date: November 21, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Yu Nishitani, Yukihiro KANEKO, Michihito UEDA
  • Patent number: 8504503
    Abstract: A pulse modulated neural integrator circuit is comprised of discrete analog electronic components and has a plurality of discrete stable states. In some embodiments, the pulse modulated neural integrator circuit is fabricated in whole or in part on an integrated circuit substrate using analog VLSI techniques. A phase locked loop circuit can use the pulse modulated neural integrator circuit in place of some conventional phase locked loop circuits.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: August 6, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Chi-Sang Poon, Joshua Jen Monzon, Guy Rachmuth, Kuan Zhou
  • Publication number: 20130185237
    Abstract: A neuromorphic data processing device comprising a plurality of spiking neurons, with each of these neurons comprising: an integrator designed to receive successive analogue pulses each having a certain value, and accumulate the values of the pulses received in a recorded value, referred to as accumulation value, and a discharger designed to emit a pulse, referred to as discharge pulse, according to the accumulation value, and a silicon support having two surfaces, the neurons being carried out on at least one of the two surfaces, the integrator of each neuron comprising a metal via of the TSV type between the two surfaces of the silicon support, the metal via of the TSV type forming a capacitor with the silicon support and having an electric potential forming the accumulation value wherein the values of the pulses received are accumulated and according to which the discharge pulse is emitted.
    Type: Application
    Filed: July 16, 2012
    Publication date: July 18, 2013
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Rodolphe HELIOT, Marc Duranton, Antoine Joubert
  • Publication number: 20130173516
    Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bipin Rajendran, Mark B. Ritter
  • Patent number: 8463723
    Abstract: An electronic synapse device is provided. One embodiment of the invention includes a metastable switching synaptic device. Changing conductance of the metastable switching synaptic device occurs by receiving opposite signed first and second voltage pulses at the metastable switching synaptic device where magnitude of the first voltage pulse and the second voltage pulse each are below a switching voltage magnitude threshold. A magnitude difference between the first voltage pulse and the second voltage pulse exceeds the switching voltage magnitude threshold by an amount, wherein the amount is a function of a relative timing between the first voltage pulse and the second voltage pulse.
    Type: Grant
    Filed: March 1, 2009
    Date of Patent: June 11, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dharmendra S. Modha, Chandrasekhar Narayan, John C. Scott
  • Patent number: 8447714
    Abstract: A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Matthew Joseph Breitwisch, Roger W Cheek, Chung Hon Lam, Dharmendra Shantilal Modha, Bipin Rajendran
  • Patent number: 8433665
    Abstract: The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: April 30, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Yi Tang, Jeffrey A. Levin, Vladimir Aparin, Venkat Rangan
  • Publication number: 20130073501
    Abstract: Certain aspects of the present disclosure relate to a technique for adaptive structural delay plasticity applied in spiking neural networks. With the proposed method of structural delay plasticity, the requirement of modeling multiple synapses with different delays can be avoided. In this case, far fewer potential synapses should be modeled for learning.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 21, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Jason Frank Hunzinger, Victor Hokkiu Chan, Jeffrey Alexander Levin
  • Publication number: 20120310871
    Abstract: A spike domain circuit responsive to analog and/or spike domain input signals. The spike domain circuit has a hysteresis quantizer for generating a spike domain output signal z(t); a one bit DAC having an input which is coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and having an output which is coupled to a current summing node; and a second order filter stage having two inputs, one of said two inputs being coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and the other of the two inputs being coupled to receive current summed at said current summing node. The second order filter stage has an output coupled to an input of the hysteresis quantizer. The current summing node also receives signals related to the analog and/or spike domain input signals to which the circuit is responsive. The circuit may serve as a neural node and many such circuits may be utilized together to model neurons with complex biological dynamics.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 6, 2012
    Applicant: HRL LABORATORIES, LLC
    Inventors: Jose Cruz-Albrecht, Peter Petre, Narayan Srinivasa
  • Patent number: 8326782
    Abstract: A special purpose processor (SPP) can use a Field Programmable Gate Array (FPGA) to model a large number of neural elements. The FPGAs or similar programmable device can have multiple cores doing presynaptic, postsynaptic, and plasticity calculations in parallel. Each core can implement multiple neural elements of the neural model.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 4, 2012
    Assignee: Neurosciences Research Foundation, Inc.
    Inventors: James A. Snook, Richard W. Schermerhorn
  • Publication number: 20120303567
    Abstract: Certain aspects of the present disclosure present a technique for primary visual cortex (V1) cell training and operation. The present disclosure proposes a model structure of V1 cells and retinal ganglion cells (RGCs), and an efficient method of training connectivity between these two layers of cells such that the proposed method leads to an autonomous formation of feature detectors within the V1 layer. The proposed approach enables a hardware-efficient and biological-plausible implementation of image recognition and motion detection systems.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Applicant: QUALCOMM Incorporated
    Inventor: Vladimir Aparin