Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element may be digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension a second destination neuron may be connected to the first neuron by a second synapse in a second dimension to form linked columns and rows of neuron/synapse circuit elements. In one embodiment, the rows and columns of circuit elements have read registers that are linked together by signal lines and clocked and controlled so as to output columnar data to an output register when a neuron/synapse data value is stored in the read register.

Abstract: A plurality of synapse determination circuits are provided on a one-to-one basis for a plurality of gate electrodes of a multi-input gate electrode in a neuron element. With respect to first image regions where “1” is repeatedly inputted in correspondence with group information, the synapse determination circuits corresponding to the first image regions are excitatory synapses. With respect to second image regions where “0” is repeatedly inputted in correspondence with the group information, the synapse determination circuits corresponding to the second image regions are inhibitory synapses.

Abstract: Provided us a visual cortical circuit apparatus comprising: a current mirror unit which uses a transistor as a current source to generate a current having the same size as that of a reaction; a transconductance unit which takes, as an input, the current generated by the current mirror unit and outputs a voltage using a transconductance; and a buffer unit for converting the voltage output from the transconductance unit into a current and buffering the current.

Abstract: A neuromorphic data processing device comprising a plurality of spiking neurons, with each of these neurons comprising: an integrator designed to receive successive analog pulses each having a certain value, and accumulate the values of the pulses received in a recorded value, referred to as accumulation value, and a discharger designed to emit a pulse, referred to as discharge pulse, according to the accumulation value, and a silicon support having two surfaces, the neurons being carried out on at least one of the two surfaces, the integrator of each neuron comprising a metal via of the TSV type between the two surfaces of the silicon support, the metal via of the TSV type forming a capacitor with the silicon support and having an electric potential forming the accumulation value wherein the values of the pulses received are accumulated and according to which the discharge pulse is emitted.

Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Abstract: A method for creating on chip analog mathematical engines is provided utilizing a neural network with a switched capacitor structure to implement coefficients for weighted connections and error functions for the neural network. The neural networks are capable of any transfer function, learning, doing pattern recognition, clustering, control or many other functions. The switched capacitor charge controls allow for nodal control of charge transfer based switched capacitor circuits. The method reduces reliance on passive component programmable arrays to produce programmable switched capacitor circuit coefficients. The switched capacitor circuits are dynamically scaled without having to rely on switched in unit passives, such as unit capacitors, and the complexities of switching these capacitors into and out of circuit.

Abstract: Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.

Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Abstract: Certain aspects of the present disclosure present a technique for primary visual cortex (V1) cell training and operation. The present disclosure proposes a model structure of V1 cells and retinal ganglion cells (RGCs), and an efficient method of training connectivity between these two layers of cells such that the proposed method leads to an autonomous formation of feature detectors within the V1 layer. The proposed approach enables a hardware-efficient and biological-plausible implementation of image recognition and motion detection systems.

Abstract: CMOS-memristor circuit is constructed to behave as a trainable artificial synapse for neuromorphic hardware systems. The invention relies on the memristance of a memristor at the input side of the device to act as a reconfigurable weight that is adjusted to realize a desired function. The invention relies on charge sharing at the output to enable the summation of signals from multiple synapses at the input node of a neuron circuit, implemented using a CMOS amplifier circuit. The combination of several memristive synapses and a neuron circuit constitute a neuromorphic circuit capable of learning and implementing a multitude of possible functionalities.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: Logic circuits using neuristors is described. In an example, a circuit includes a plurality of neuristors each producing an output voltage spike in response to a super-threshold input voltage. A plurality of impedances couple the plurality of neuristors to form at least one input and an output, the output selectively providing an output voltage spike based on a logical operation of at least one input voltage at the at least one input.

Abstract: Disclosed is a semiconductor device used to embody a neuromorphic computation system and operation method thereof. By comprising a floating body as a short-term memory means electrically isolated from the surroundings and a long-term memory means formed at one side of the floating body not formed of a source, a drain and a gate, a low power synaptic semiconductor device is provided, which can be mimic not only the short-term memory in a nervous system of a living body by an impact ionization, but also the short- and long-term memory transition property and the causal inference property of a living body due to the time difference of signals of the pre- and post-synaptic neurons.

Abstract: A neuromorphic circuit performs functions representative of spiking timing dependent plasticity of a synapse.

Abstract: A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a predetermined pulse voltage, and a first input signal has a waveform of the predetermined pulse voltage. For a period having a predetermined duration of the predetermined pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element, the first input signal is permitted to be input to the control electrode of the variable resistance element, to change the resistance value of the variable resistance element due to an electric potential difference generated between the first electrode and the control electrode which occurs depending on an input timing of the first input signal with respect to the period during which the first input signal is permitted to be input to the control electrode.

Abstract: A pulse modulated neural integrator circuit is comprised of discrete analog electronic components and has a plurality of discrete stable states. In some embodiments, the pulse modulated neural integrator circuit is fabricated in whole or in part on an integrated circuit substrate using analog VLSI techniques. A phase locked loop circuit can use the pulse modulated neural integrator circuit in place of some conventional phase locked loop circuits.

Abstract: A neuromorphic data processing device comprising a plurality of spiking neurons, with each of these neurons comprising: an integrator designed to receive successive analogue pulses each having a certain value, and accumulate the values of the pulses received in a recorded value, referred to as accumulation value, and a discharger designed to emit a pulse, referred to as discharge pulse, according to the accumulation value, and a silicon support having two surfaces, the neurons being carried out on at least one of the two surfaces, the integrator of each neuron comprising a metal via of the TSV type between the two surfaces of the silicon support, the metal via of the TSV type forming a capacitor with the silicon support and having an electric potential forming the accumulation value wherein the values of the pulses received are accumulated and according to which the discharge pulse is emitted.

Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.

Abstract: An electronic synapse device is provided. One embodiment of the invention includes a metastable switching synaptic device. Changing conductance of the metastable switching synaptic device occurs by receiving opposite signed first and second voltage pulses at the metastable switching synaptic device where magnitude of the first voltage pulse and the second voltage pulse each are below a switching voltage magnitude threshold. A magnitude difference between the first voltage pulse and the second voltage pulse exceeds the switching voltage magnitude threshold by an amount, wherein the amount is a function of a relative timing between the first voltage pulse and the second voltage pulse.

Abstract: A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse.

Abstract: The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling.

Abstract: Certain aspects of the present disclosure relate to a technique for adaptive structural delay plasticity applied in spiking neural networks. With the proposed method of structural delay plasticity, the requirement of modeling multiple synapses with different delays can be avoided. In this case, far fewer potential synapses should be modeled for learning.

Abstract: A spike domain circuit responsive to analog and/or spike domain input signals. The spike domain circuit has a hysteresis quantizer for generating a spike domain output signal z(t); a one bit DAC having an input which is coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and having an output which is coupled to a current summing node; and a second order filter stage having two inputs, one of said two inputs being coupled to receive the spike domain output signal z(t) output by the hysteresis quantizer and the other of the two inputs being coupled to receive current summed at said current summing node. The second order filter stage has an output coupled to an input of the hysteresis quantizer. The current summing node also receives signals related to the analog and/or spike domain input signals to which the circuit is responsive. The circuit may serve as a neural node and many such circuits may be utilized together to model neurons with complex biological dynamics.

Abstract: A special purpose processor (SPP) can use a Field Programmable Gate Array (FPGA) to model a large number of neural elements. The FPGAs or similar programmable device can have multiple cores doing presynaptic, postsynaptic, and plasticity calculations in parallel. Each core can implement multiple neural elements of the neural model.

Abstract: Certain aspects of the present disclosure present a technique for primary visual cortex (V1) cell training and operation. The present disclosure proposes a model structure of V1 cells and retinal ganglion cells (RGCs), and an efficient method of training connectivity between these two layers of cells such that the proposed method leads to an autonomous formation of feature detectors within the V1 layer. The proposed approach enables a hardware-efficient and biological-plausible implementation of image recognition and motion detection systems.

Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Abstract: A neuromorphic computing device utilizing electronics to perform the function of neurons and synaptic connections. The invention provides variable resistance circuits to represent interconnection strength between neurons and a positive and negative output circuit to represent excitatory and inhibitory responses, respectively. The invention provides advantages over software-based neuromorphic computing methods.

Abstract: A physical neural network includes at least one neuron-like node that sums at least one input signal and generates at least one output signal based on a threshold associated with the at least one input signal, at least one connection network associated with the at least one neuron-like node wherein the at least one connection network comprises a plurality of interconnected connections, such that each connection of the plurality of interconnected connections is strengthened or weakened according to an application of an electric field. In some cases, the threshold can include a threshold below which the at least one output signal is not generated and above which the at least one output signal is generated.

Abstract: Certain embodiments of the present disclosure support techniques for training of synapses in biologically inspired networks. Only one device based on a memristor can be used as a synaptic connection between a pair of neurons. The training of synaptic weights can be achieved with a low current consumption. A proposed synapse training circuit may be shared by a plurality of incoming/outgoing connections, while only one digitally implemented pulse-width modulation (PWM) generator can be utilized per neuron circuit for generating synapse-training pulses. Only up to three phases of a slow clock can be used for both the neuron-to-neuron communications and synapse training. Some special control signals can be also generated for setting up synapse training events. By means of these signals, the synapse training circuit can be in a high-impedance state outside the training events, thus the synaptic resistance (i.e., the synaptic weight) is not affected outside the training process.

Abstract: Certain embodiments of the present disclosure support implementation of a neural processor with synaptic weights, wherein training of the synapse weights is based on encouraging a specific output neuron to generate a spike. The implemented neural processor can be applied for classification of images and other patterns.

Abstract: Certain embodiments of the present disclosure support techniques for designing neuron circuits based on memristors. Bulky capacitors as electrical current integrators can be eliminated and nanometer scale memristors can be utilized instead. Using the nanometer feature-sized memristors, the neuron hardware area can be substantially reduced.

Abstract: Certain embodiments of the present disclosure support techniques for power efficient implementation of neuron synapses with positive and/or negative synaptic weights.

Abstract: Certain embodiments of the present disclosure support implementation of a digital neural processor with discrete-level synapses and probabilistic synapse weight training.

Abstract: The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling.

Abstract: Four stochastic resonators 20-1 to 20-4 outputting a pulse signal in accordance with a stochastic resonance phenomenon are unidirectionally coupled in a ring-like form to constitute a fluctuation oscillator 10. When a signal output from each of the stochastic resonators 20-1 to 20-4 is successively transmitted in the stochastic resonators 20-1 to 20-4 coupled in a ring-like form, the output timings at each stochastic resonator 20 are synchronized with each other due to a cooperation phenomenon between the stochastic resonators 20-1 to 20-4, so that each stochastic resonator 20 is self-excited to oscillate at a constant period of time.

Abstract: A special purpose processor (SPP) can use a Field Programmable Gate Array (FPGA) to model a large number of neural elements. The FPGAs or similar programmable device can have multiple cores doing presynaptic, postsynaptic, and plasticity calculations in parallel. Each core can implement multiple neural elements of the neural model.

Abstract: A neuromorphic circuit performs functions representative of spiking timing dependent plasticity of a synapse.

Abstract: A neuromorphic circuit includes a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor. The neuromorphic circuit also includes a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor. The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value. The neuromorphic circuit additionally includes a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit, and a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit.

Abstract: A neuromorphic computing device utilizing electronics to perform the function of neurons and synaptic connections. The invention provides variable resistance circuits to represent interconnection strength between neurons and a positive and negative output circuit to represent excitatory and inhibitory responses, respectively. The invention provides advantages over software-based neuromorphic computing methods.

Abstract: A neural network comprising artificial neurons interconnected by connections, wherein each artificial neuron is configured to receive an input signal from and send an output signal to one or more of the other artificial neurons through one of the connections; each input and output signal is either positive or negative valued; and each artificial neuron has an activation at a time point, the activation being determined by at least input signals received by the artificial neuron, output signals sent by the artificial neuron, and a plurality of weights, wherein at least one weight is self-tuned at the time point. Also provided are methods of tuning neural networks.

Abstract: An input layer outputs light having a relatively narrow emission angle distribution to a middle layer as an output signal if the signal level of input signal is relatively high and outputs light having a relatively broad emission angle distribution to the middle layer as the output signal if the signal level of input signal is relatively low. The middle layer outputs light having a relatively narrow emission angle distribution as an output signal to an output layer if the signal level of the output signal from input layer is relatively high and outputs light having a relatively broad emission angle distribution to the output layer as an output signal if the signal level of the output signal from the input layer is relatively low.

Abstract: According to embodiments of the invention, a system, method and computer program product producing spike-dependent plasticity in an artificial synapse.

Abstract: A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse.

Abstract: Methods and systems are presented for constructing biological-scale hierarchically structured cortical statistical memory systems using currently available fabrication technology and meta-stable switching devices. Learning content-addressable memory and statistical random access memory circuits are detailed. Additionally, local and global signal modulation of bottom-up and top-down processing for the initiation and direction of behavior is disclosed.

Abstract: A physical neural network synapse chip and a method for forming such a synapse chip. The synapse chip can be configured to include an input layer comprising a plurality of input electrodes and an output layer comprising a plurality of output electrodes, such that the output electrodes are located perpendicular to the input electrodes. A gap is generally formed between the input layer and the output layer. A solution can then be provided which is prepared from a plurality of nanoconductors and a dielectric solvent. The solution is located within the gap, such that an electric field is applied across the gap from the input layer to the output layer to form nanoconnections of a physical neural network implemented by the synapse chip. Such a gap can thus be configured as an electrode gap. The input electrodes can be configured as an array of input electrodes, while the output electrodes can be configured as an array of output electrodes.

Abstract: Fractal memory systems and methods include a fractal tree that includes one or more fractal trunks. One or more object circuits are associated with the fractal tree. The object circuit(s) can be configured from a plurality of nanotechnology-based components to provide a scalable distributed computing architecture for fractal computing. Additionally, a plurality of router circuits is associated with the fractal tree, wherein one or more fractal addresses output from a recognition circuit can be provided at a fractal trunk by the router circuits.

Abstract: An electronic synapse device is provided. One embodiment of the invention includes a metastable switching synaptic device. Changing conductance of the metastable switching synaptic device occurs by receiving opposite signed first and second voltage pulses at the metastable switching synaptic device where magnitude of the first voltage pulse and the second voltage pulse each are below a switching voltage magnitude threshold. A magnitude difference between the first voltage pulse and the second voltage pulse exceeds the switching voltage magnitude threshold by an amount, wherein the amount is a function of a relative timing between the first voltage pulse and the second voltage pulse.

Abstract: A programmable logic unit (e.g., an ASIC or FPGA) having a feedforward linear associative memory (LAM) neural network checking circuit which classifies input vectors to a faulty hardware block as either good or not good and, when a new input vector is classified as not good, blocks a corresponding output vector of the faulty hardware block, enables a software work-around for the new input vector, and accepts the software work-around input as the output vector of the programmable logic circuit. The feedforward LAM neural network checking circuit has a weight matrix whose elements are based on a set of known bad input vectors for said faulty hardware block. The feedforward LAM neural network checking circuit may update the weight matrix online using one or more additional bad input vectors. A discrete Hopfield algorithm is used to calculate the weight matrix W.

Abstract: A method for and system for training a connection network located between neuron layers within a multi-layer physical neural network. A multi-layer physical neural network can be formed having a plurality of inputs and a plurality outputs thereof, wherein the multi-layer physical neural network comprises a plurality of layers, wherein each layer comprises one or more connection networks and associated neurons. Thereafter, a training wave can be initiated across the connection networks associated with an initial layer of the multi-layer physical neural network which propagates thereafter through succeeding connection networks of succeeding layers of the neural network by successively closing and opening switches associated with each layer. One or more feedback signals thereof can be automatically provided to strengthen or weaken nanoconnections associated with each connection network.

Abstract: An apparatus includes a substrate with a planar surface, a multilayer of semiconductor layers located on the planar surface, a plurality of electrodes located over the multilayer, and a dielectric layer located between the electrodes and the multilayer. The multilayer includes a 2D quantum well. A first set of the electrodes is located to substantially surround a lateral area of the 2D quantum well. A second set of the electrodes is controllable to vary a lateral width of a non-depleted channel between the substantially surrounded lateral area of the 2D quantum well and another area of the 2D quantum well. A third set of the electrodes is controllable to vary an area of a non-depleted portion of the lateral area.