Abstract: An arithmetic device includes N product-sum-operation circuits, a control circuit, and an output circuit. Each product-sum-operation circuit outputs intermediate signals obtained by binarizing a product-sum-operation value obtained by product-sum-operation of M input values of M input signals and M weight values. The control circuit inverts positive/negative of each M weight value at determining-timing when a given time elapses from input timing. Based on a delay time from the determination-timing to logic finalization of the intermediate signal for each N product-sum-operation circuit, the output circuit outputs an output signal representing a winner-product-sum-operation circuit for which the product-sum-operation value having a sign and the largest absolute value is calculated.

Abstract: Systems and methods for quality monitoring and hidden quantization in artificial neural network (ANN) computations are provided. An example method may include receiving a description of an ANN and input data associated with the ANN, performing, based on a quantization scheme, quantization of the ANN to obtain a quantized ANN, performing, based on the set of input data, ANN computations of the quantized ANN to obtain a result of the ANN computation for the input data, while performing the ANN computations, monitoring, a measure of quality of the ANN computations of the quantized ANN, determining that the measure of quality does not satisfy quality requirements, and in response to the determination, informing a user of an external system of the measure of quality, and adjusting, based on the measure of quality, the quantization scheme to be used in the ANN computations for further input data.

Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

Abstract: The present disclosure provides a brain-like computing chip and a computing device. The brain-like computing chip includes is a many-core system composed of one or more functional cores, and data transmission is performed between the functional cores by means of a network-on-chip. The functional core includes at least one neuron processor configured to compute various neuron models, and at least one coprocessor coupled to the neuron processor and configured to perform an integral operation and/or a multiply-add-type operation; and the neuron processor is capable of calling the coprocessor to perform the multiply-add-type operation.

Abstract: A read-only memory (ROM) computing unit utilized in matrix operations of a neural network comprising a unit element including one or more connections, wherein a weight associated with the computing unit is responsive to either a connection or lack of connection internal to the unit cell or between the unit element and a wordline and a bitline utilized to form an array of rows and columns in the ROM computing unit, and one or more passive or active electrical elements located in the unit element, wherein the passive or active electrical elements are configured to adjust the weight associated with the compute unit, wherein the ROM computing unit is configured to receive an input and output a value associated with the matrix operation, wherein the value is responsive to the input and weight.

Abstract: A neuron circuit performing synapse learning on weight values includes a first sub-circuit, a second sub-circuit, and a third sub-circuit. The first sub-circuit is configured to receive an input signal from a pre-synaptic neuron circuit and determine whether the received input signal is an active signal having an active synapse value. The second sub-circuit is configured to compare a first cumulative reception counter of active input signals with a learning threshold value based on results of the determination. The third sub-circuit is configured to perform a potentiating learning process based on a first probability value to set a synaptic weight value of at least one previously received input signal to an active value, upon the first cumulative reception counter reaching the learning threshold value, and perform a depressing learning process based on a second probability value to set each of the synaptic weight values to an inactive value.

Abstract: Systems and methods for a capacitor based resistive processing unit with symmetrical weight updating include a first capacitor that stores a charge corresponding to a weight value. A readout circuit reads the charge stored in the first capacitor to apply a weight to an input value corresponding to an input signal using the weight value to produce an output. An update circuit updates the weight value stored in the first capacitor, including a second capacitor in communication with the first capacitor to transfer an amount of charge to the first capacitor according to an error of the output by changing a voltage difference across the first capacitor by a voltage change corresponding to the amount of charge, the voltage difference corresponding to the charge stored in the first capacitor.

Abstract: Controllable resistance elements and methods of setting the same include a junction field effect transistor configured to provide a resistance on a signal line. A first pass transistor is configured to apply a charge increment or decrement to the junction field effect transistor responsive to a control pulse, such that the resistance on the signal line changes.

Abstract: Methods of training a neural network include applying an input signal to an array of weights to generate weighted output signals based on resistances of respective weights in the array of weights. A difference between the weighted output signals and a predetermined expected output is determined. Weights in the array of weights are set by applying a pulse to a controllable resistance element in each weight. The pulse increments or decrements a charge on a junction field effect transistor in the respective controllable resistance element.

Abstract: Neural networks include neuron layers arranged in order from an input neuron layer to an output neuron layer, with at least one hidden layer between them. Weight arrays between respective pairs of neuron layers each include controllable resistance elements and AND gates configured to control addressing of the plurality of controllable resistance elements. Each controllable resistance element includes a junction field effect transistor configured to provide a resistance on a signal line and a first pass transistor configured to apply a charge increment or decrement to the junction field effect transistor responsive to a control pulse, such that the resistance on the signal line changes. The control pulse is only passed to a controllable resistance element when a respective AND gate is triggered. A training module is configured to train the neural network by adjusting resistances of the plurality of controllable resistance elements in each of the weight arrays.

Abstract: A cognitive learning device includes inputs with each including an input path having a transistor device having a storage capacity. A circuit is responsive to the inputs and selects an input set in accordance with a current task, wherein the input set selected modifies a characteristic of the transistor device of one or more corresponding input paths to bias the input set for selection for subsequent accesses.

Abstract: A cognitive learning device includes inputs with each including an input path having a transistor device having a storage capacity. A circuit is responsive to the inputs and selects an input set in accordance with a current task, wherein the input set selected modifies a characteristic of the transistor device of one or more corresponding input paths to bias the input set for selection for subsequent accesses.

Abstract: The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.

Abstract: Embodiments of the invention provide a system for scaling multi-core neurosynaptic networks. The system comprises multiple network circuits. Each network circuit comprises a plurality of neurosynaptic core circuits. Each core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of electronic synapse devices. An interconnect fabric couples the network circuits. Each network circuit has at least one network interface. Each network interface for each network circuit enables data exchange between the network circuit and another network circuit by tagging each data packet from the network circuit with corresponding routing information.

Abstract: A method for improving neural dynamics includes obtaining prototypical neuron dynamics. The method also includes modifying parameters of a neuron model so that the neuron model matches the prototypical neuron dynamics. The neuron dynamics comprise membrane voltages and/or spike timing.

Abstract: A neural network has an array of interconnected processors, at least a first processor in the array operating in a pulse domain and at least a second processor in the array operating in a spike domain, and each said processor having: first inputs selectively coupled to other processors in the array of interconnected processors, each first input having an associated VCCS (a 1 bit DAC) coupled to a summing node, second inputs selectively coupled to inputs of the neural network, the second inputs having current generators associated therewith coupled to said summing node, a filter/integrator for generating an analog signal corresponding to current arriving at the summing node, and for processors operating in the pulse domain, an analog-to-pulse converter for converting an analog signal derived either directly from the filter/integrator or via a non-linear element, to the pulse domain, and providing the converted analog signal as an unquantized pulse domain signal at an output of each processor operating in the p

Abstract: An integrate and fire electronic neuron is disclosed. Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated.

Abstract: Systems and methods for processing image signals are described. One method comprises obtaining a generator signal based on an image signal and determining relative latencies associated with two or more pulses in a pulsed signal using a function of the generator signal that can comprise a logarithmic function. The function of the generator signal can be the absolute value of its argument. Information can be encoded in the pattern of relative latencies. Latencies can be determined using a scaling parameter that is calculated from a history of the image signal. The pulsed signal is typically received from a plurality of channels and the scaling parameter corresponds to at least one of the channels. The scaling parameter may be adaptively calculated such that the latency of the next pulse falls within one or more of a desired interval and an optimal interval.

Abstract: An integrate and fire electronic neuron is disclosed. Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated.

Abstract: A method and system for processing a parameter for an item in an electronic order processing system is provided. The method has a first step of associating a calculation code with the item. The second step of the method is applying the calculation rule to the item to produce an amount. The third step of the method is providing the amount to an output device. Each operation within each of the first step, the second step and the third step may be modified and flow of execution amongst the first step, the second step and the third step remains the same.

Abstract: In general, the invention is directed to a technique for selection of parameter configurations for a neurostimulator using neural networks. The technique may be employed by a programming device to allow a clinician to select parameter configurations, and then program an implantable neurostimulator to deliver therapy using the selected parameter configurations. The parameter configurations may include one or more of a variety of parameters, such as electrode configurations defining electrode combinations and polarities for an electrode set implanted in a patient. The electrode set may be carried by one or more implanted leads that are electrically coupled to the neurostimulator. In operation, the programming device executes a parameter configuration search algorithm to guide the clinician in the selection of parameter configurations. The search algorithm relies on a neural network that identifies potential optimum parameter configurations.

Abstract: A neural network has an array of interconnected processors, each processor operating either the pulse domain or spike domain.

Abstract: A pulse signal processing circuit, a parallel processing circuit, and a pattern recognition system including a plurality of arithmetic elements for outputting pulse signals and at least one modulation circuit, synaptic connection element(s), or synaptic connection means for modulating the pulse signals, the modulated pulse signals then being separately or exclusively output to corresponding signal lines.

Abstract: We develop a system consisting of a neural architecture resulting in classifying regions corresponding to users' keystroke patterns. We extend the adaptation properties to classification phase resulting in learning of changes over time. Classification results on login attempts of 43 users (216 valid, 657 impersonation samples) show considerable improvements over existing methods.

Abstract: A neural network component includes a plurality of inputs, at least one processing element, at least one output, and a digital memory storing values at addresses respectively corresponding to the at least one processing element, wherein the at least one processing element is arranged to receive a value from the digital memory in response to an input signal, and is instructed to execute one of a plurality of operations by the value that is received from the digital memory.

Abstract: An information processing system having neuron-like signal processors that are interconnected by synapse-like processing junctions that simulates and extends capabilities of biological neural networks. The information processing systems uses integrate-and-fire neurons and Temporally Asymmetric Hebbian learning (spike timing-dependent learning) to adapt the synaptic strengths. The synaptic strengths of each neuron are guaranteed to become optimal during the course of learning either for estimating the parameters of a dynamic system (system identification) or for computing the first principal component. This neural network is well-suited for hardware implementations, since the learning rule for the synaptic strengths only requires computing either spike-time differences or correlations. Such hardware implementation may be used for predicting and recognizing audiovisual information or for improving cortical processing by a prosthetic device.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0–11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract: A synaptic connection element for connecting neuron elements inputs a plurality of pulsed signals from different neuron elements N1 through N4, effects a common modulation (time window integration or pulse phase/width modulation) on a plurality of predetermined signals among the plurality of pulse signals, and outputs the modulated pulse signals to different signal lines to a neuron element M1. A neural network for representing and processing pattern information by the pulse modulation is thereby downsized in scale.

Abstract: A voltage-mode pulse width modulation (PWM) VLSI implementation of neural networks, comprising: a voltage-pulse converter for converting an input voltage into a neuron-state pulse; a synapse multiplier, including a multiplier cell for multiplying the neuron-state pulse by an input weight voltage and an integral and summation cell for integrating and summing up the multiplied output and producing a first output voltage; and a sigmoid circuit for converting the first output voltage into a second output voltage with the non-linear activation function of neuron.

Abstract: An information processing system having signal processors that are interconnected by processing junctions that simulate and extend biological neural networks. Each processing junction receives signals from one signal processor and generates a new signal to another signal processor. The response of each processing junction is determined by internal junction processes and is continuously changed with temporal variation in the received signal. Different processing junctions connected to receive a common signal from a signal processor respond differently to produce different signals to downstream signal processors. This transforms a temporal pattern of a signal train of spikes into a spatio-temporal pattern of junction events and provides an exponential computational power to signal processors. Each signal processing junction can receive a feedback signal from a downstream signal processor so that an internal junction process can be adjusted to learn certain characteristics embedded in received signals.

Abstract: A process and apparatus that enable continual self-adaptation of dynamic transmission devices (saSTDs), allow “smart” filtering of information for transmission from one element to another within a network of interacting elements, such as a “neural network”. An adaptation algorithm (MapSA) incorporated in STDs allows multiple parameters of STDs (which determine its filtering properties) to continuously adapt simultaneously and interdependently. In this manner, complex correlations can be established between the parameters in all STDs within a network of interacting elements. The process according to the invention therefore establishes unique patterns of connection parameters within the network which in turn dictates a novel sequence of information processing steps by the network.

Abstract: There is provided a neuron which is capable of expressing an excitative coupling and a suppressive coupling by one signal by devising signals processed in the neuron to reduce a circuit area of a neural network in constructing the neural network by a digital electronic circuit. A multiplying block calculates a numerical value following a normal distribution N(wx, 1) by using a corresponding link weight w under the supposition that delay time of each pulse of an input signal follows a normal distribution of N(x, 1). Next, an adding block adds the numerical values calculated by the respective multiplying blocks one after another and a non-linear operating block counts a number of positive values within the added value obtained by the adding block. A pulse delaying block delays output pulse following a normal distribution in which delay time is 0 in average generated by a basic pulse generating block based on the result of operation of the non-linear operating block to output as an output signal.

Abstract: A semiconductor arithmetic circuit which compares the magnitudes of a plurality of data with each other in real time by using a simple circuit. The semiconductor arithmetic circuit containing one or more neuron MOS transistors each having a plurality of input gate electrodes has an inverter circuit group of a plurality of inverter circuit each of which is constituted of neuron MOS transistors and a means for applying a prescribed signal voltage to at least one first input gate of the inverter circuit.

Abstract: The invention provides a pulse width modulation operation circuit for processing an m-bit pulse width modulation signal which is represented by a number n of sub pulse width modulation signals, where n is a divisor of m, characterized by comprising at least two equivalent pulse modulation operation circuits for individually processing the number n of sub pulse width modulation signals and outputting the processing results in the form of binary digital signals, and means for adding the binary digital signals from the pulse modulation operation circuits. The pulse modulation operation circuits include current pulse generating means for generating current pulses corresponding to the sub pulse width modulation signals, a current bus for transmitting the generated current pulses, and means for integrating the current pulses and converting the integrated current pulses into charges, and means for digitizing the sum of the charges to obtain digitized data.

Abstract: Dental restorative compositions containing a mixture of Ca.sub.4 (PO.sub.4).sub.2 O and at least one different calcium phosphate.