Hybrid Network (i.e., Analog And Digital) Patents (Class 706/34)
  • Patent number: 10650308
    Abstract: A synaptic circuit performing spike-timing dependent plasticity STDP interposed between a pre-synaptic neuron and a post-synapse neuron includes a memristor having a variable resistance value configured to receive a first signal from the pre-synaptic neuron. The circuit has an intermediate unit connected in series with the memristor for receiving a second signal from the pre-synaptic neuron and provides an output signal to the post-synaptic neuron. The intermediate unit receives a retroaction signal generated from the post-synaptic neuron and the memristor modifies the resistance value based on a delay between two at least partially overlapped input pulses, a spike event of the first signal and a pulse of the retroaction signal, in order to induct a potentiated state STP or a depressed state STD at the memristor. An electronic neuromorphic system having synaptic circuits and a method of performing spike timing dependent plasticity STDP by a synaptic circuit are also provided.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 12, 2020
    Inventors: Daniele Ielmini, Simone Balatti, Stefano Ambrogio, Zhongqiang Wang
  • Patent number: 10476487
    Abstract: An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: November 12, 2019
    Assignee: Purdue Research Foundation
    Inventors: Kaushik Roy, Mrigank Sharad
  • Patent number: 10389519
    Abstract: A method of controlling transistors includes receiving a control signal, and controlling the top and bottom gate biases of the transistors according to the control signal to normalize or randomize power drawn as observed outside of a core. A device for controlling transistors includes a core performing computational instructions, and a bias circuit receiving a control signal, the bias circuit controlling the top and bottom gate biases of the transistors according to the control signal to normalize or randomize power drawn as observed outside of the core.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 20, 2019
    Inventors: Kangguo Cheng, Shawn P. Fetterolf, Ali Khakifirooz
  • Patent number: 10250617
    Abstract: A computer-implemented method for detecting malware using machine learning may include (1) identifying data to be analyzed for malware, (2) classifying, using a classifier created by a combination of at least one deep learning neural network and at least one supervised data mining method, the data to be analyzed for malware, (3) determining, based on a predefined threshold, that the classification of the data indicates potential malware on the computing device, and (4) performing a security action based on the determination of potential malware on the computing device. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: November 22, 2015
    Date of Patent: April 2, 2019
    Assignee: Symantec Corporation
    Inventors: Andrew Gardner, Walter Bogorad, Jun Mao
  • Patent number: 10249360
    Abstract: A method and a circuit for generating a reference voltage are provided. The circuit includes: a first column of dummy neurons with weight 0 and a second column of dummy neurons with weight 1, wherein the plurality word-lines are connected to the dummy neurons in the first and second columns, respectively; a bit-line connected to a voltage source and the first column of dummy neurons; a complementary bit-line is connected to the voltage source and the second column of dummy neurons, wherein when the artificial neural network system is operated to sense the neurons of the memory cell array, one or more of the plurality of word-lines are activated, and the corresponding dummy neurons of the first column and the second column are activated to generate the reference voltage at the output end for sensing the neurons of the memory cell array.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 2, 2019
    Inventors: Meng-Fan Chang, Win-San Khwa, Jia-Jing Chen
  • Patent number: 9779355
    Abstract: Technical solutions are described for implementing a neural network. An example system includes a crosspoint array including a plurality of nodes, each node representing a weight assigned to a neuron of the neural network. The system also includes a capacitor associated with a set of nodes from the plurality of nodes, where the capacitor is configured to store a current value corresponding to a sum of outputs from each respective node from the set of nodes. The system also includes a clocking circuit that initiates a forward pass to propagate the current value stored in the capacitor to a subsequent layer of the neural network. The clocking circuit further initiates a backward pass to propagate the current value stored in the capacitor to a preceding layer of the neural network. The clocking circuit further initiates a weight-update pass to update the weights in the neural network.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: October 3, 2017
    Inventor: Effendi Leobandung
  • Patent number: 9215322
    Abstract: A communications routing system, and method, for representing a plurality of predicted characteristics of a plurality of communications sources, each having an economic utility; representing a plurality of predicted characteristics of a plurality of communications targets each having an economic utility; and determining an optimal routing between the plurality of communications sources and the plurality of communications targets, by maximizing an aggregate utility with respect to the respective predicted characteristics of communications source and communications destination represented by linkages.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 15, 2015
    Inventors: Wai Wu, Steven M. Hoffberg
  • Patent number: 8566265
    Abstract: A neural network has an array of interconnected processors, at least a first processor in the array operating in a pulse domain and at least a second processor in the array operating in a spike domain, and each said processor having: first inputs selectively coupled to other processors in the array of interconnected processors, each first input having an associated VCCS (a 1 bit DAC) coupled to a summing node, second inputs selectively coupled to inputs of the neural network, the second inputs having current generators associated therewith coupled to said summing node, a filter/integrator for generating an analog signal corresponding to current arriving at the summing node, and for processors operating in the pulse domain, an analog-to-pulse converter for converting an analog signal derived either directly from the filter/integrator or via a non-linear element, to the pulse domain, and providing the converted analog signal as an unquantized pulse domain signal at an output of each processor operating in the p
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: October 22, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Jose Cruz-Albrecht, Peter Petre
  • Patent number: 8433665
    Abstract: The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: April 30, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Yi Tang, Jeffrey A. Levin, Vladimir Aparin, Venkat Rangan
  • Patent number: 8275727
    Abstract: An analog-digital crosspoint-network includes a plurality of rows and columns, a plurality of synaptic nodes, each synaptic node of the plurality of synaptic nodes disposed at an intersection of a row and column of the plurality of rows and columns, wherein each synaptic node of the plurality of synaptic nodes includes a weight associated therewith, a column controller associated with each column of the plurality of columns, wherein each column controller is disposed to enable a weight change at a synaptic node in communication with said column controller, and a row controller associated with each row of the plurality of rows, wherein each row controller is disposed to control a weight change at a synaptic node in communication with said row controller.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bruce G. Elmegreen, Ralph Linsker, Dennis M. Newns, Bipin Rajendran, Roger D. Traub
  • Patent number: 7853323
    Abstract: In general, the invention is directed to a technique for selection of parameter configurations for a neurostimulator using neural networks. The technique may be employed by a programming device to allow a clinician to select parameter configurations, and then program an implantable neurostimulator to deliver therapy using the selected parameter configurations. The parameter configurations may include one or more of a variety of parameters, such as electrode configurations defining electrode combinations and polarities for an electrode set implanted in a patient. The electrode set may be carried by one or more implanted leads that are electrically coupled to the neurostimulator. In operation, the programming device executes a parameter configuration search algorithm to guide the clinician in the selection of parameter configurations. The search algorithm relies on a neural network that identifies potential optimum parameter configurations.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: December 14, 2010
    Assignee: Medtronic, Inc.
    Inventor: Steven M. Goetz
  • Patent number: 7822698
    Abstract: A neural network has an array of interconnected processors, each processor operating either the pulse domain or spike domain.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: October 26, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Jose Cruz-Albrecht, Peter Petre
  • Publication number: 20100257130
    Abstract: A timestamp neural network comprised of sensor elements, internal elements, and motor elements is responsive to timestamps. Sensor elements transform a wide variety of signals into events that trigger the updating of timestamps. Internal elements are responsive to timestamps. Motor elements convert timestamps into useful output signals. A real time video pattern recognition system is implemented.
    Type: Application
    Filed: April 1, 2009
    Publication date: October 7, 2010
    Inventor: Brad Smallridge
  • Patent number: 7743004
    Abstract: A pulse signal processing circuit, a parallel processing circuit, and a pattern recognition system including a plurality of arithmetic elements for outputting pulse signals and at least one modulation circuit, synaptic connection element(s), or synaptic connection means for modulating the pulse signals, the modulated pulse signals then being separately or exclusively output to corresponding signal lines.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: June 22, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masakazu Matsugu
  • Patent number: 7620819
    Abstract: We develop a system consisting of a neural architecture resulting in classifying regions corresponding to users' keystroke patterns. We extend the adaptation properties to classification phase resulting in learning of changes over time. Classification results on login attempts of 43 users (216 valid, 657 impersonation samples) show considerable improvements over existing methods.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: November 17, 2009
    Assignees: The Penn State Research Foundation, Louisiana Tech University Foundation, Inc.
    Inventors: Vir V. Phoha, Sunil Babu, Asok Ray, Shashi P. Phoba
  • Patent number: 7272585
    Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: September 18, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Osamu Nomura, Takashi Morie, Teppei Nakano
  • Patent number: 7035835
    Abstract: A current-mode pulse-width-modulation (PWM) circuit converts analog current signals into pulse signals. The PWM circuit includes a first I-V converter and one or more second I-V converters, each of the one or more second I-V converters being coupled to one of the current signals. Each of the first and second I-V converters is also coupled to a current generator which generates a current that linearly changes with time. For each of the first and second I-V converters, when a polarity of the input current thereof changes, an output changes between a high voltage level and a low voltage level. A logic circuit is coupled to the first and each second I-V converter to obtain a pulse signal that has a pulse width linearly proportional to the current level of the respective current signal.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: April 25, 2006
    Assignee: Winbond Electronics Corporation
    Inventors: Bingxue Shi, Lu Chen, Chun Lu
  • Patent number: 6671678
    Abstract: A multi-functional arithmetic apparatus with multi value-states comprise a gating array, which is composed of gating elements arranged in n row by m column. Each gating element has at least two input terminals and one output terminal, and has input value-states and output value-states. There is operational relationship between the input value-state and the output value-state according to the model of self-organizing principle of integer cluster. The output value-states determine the output based on the gating of the gating element, i.e. the mathematical manipulation is completed by the structure operation. The mathematical manipulation may be addition operation, subtract operation, mixed mode operation and bidirectional logic reversible operation implemented by one add operation and two subtract operations.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: December 30, 2003
    Inventor: Dixing Wang
  • Patent number: 6625588
    Abstract: An associative artificial neuron and method of forming output signals of an associative artificial neuron includes receiving a number of auxiliary input signals; forming from the auxiliary input signals a sum weighted by coefficients and applying a non-linear function to the weighted sum to generate a non-linear signal. The neuron and method further include receiving a main input signal and forming, based on the main signal and the non-linear signal, the function S OR V, which is used to generate a main output signal, and at lest one of three logical functions S AND V, NOT S AND V, and S AND NOT V. The at least one logical function is used to generate an additional output signal for the associative artificial neuron.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: September 23, 2003
    Assignee: Nokia OYJ
    Inventor: Pentti Haikonen
  • Patent number: 6539368
    Abstract: The present invention relates to the field of computer science and can be used for neural network emulation and digital signal processing. Increasing of the neural processor performance is achieved using the ability to change word lengths of results in program mode. The neural processor includes six registers, a shift register, a AND gate, two FIFOs, a switch, a multiplexer, two saturation units, a calculation unit and a adder circuit to execute operations over vectors of programmable word length data. Increasing of the saturation unit performance is achieved using the ability to process vector of input operands with programmable word length at a time. Increasing of the adder circuit performance is achieved using ability to sum two vectors of input operands of programmable word lengths.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: March 25, 2003
    Assignee: Joint-Stock Company Research Centre “Module”
    Inventors: Vladimir Mikhailovich Chernikov, Pavel Evgenjevich Viksne, Dmitriy Viktorovich Fomin, Pavel Aleksandrovich Shevchenko, Mikhail Fedorovich Yafrakov
  • Patent number: 6523018
    Abstract: The neural semiconductor chip first includes: a global register and control logic circuit block, a R/W memory block and a plurality of neurons fed by buses transporting data such as the input vector data, set-up parameters, etc., and signals such as the feed back and control signals. The R/W memory block, typically a RAM, is common to all neurons to avoid circuit duplication, increasing thereby the number of neurons integrated in the chip. The R/W memory stores the prototype components. Each neuron comprises a computation block, a register block, an evaluation block and a daisy chain block to chain the neurons. All these blocks (except the computation block) have a symmetric structure and are designed so that each neuron may operate in a dual manner, i.e. either as a single neuron (single mode) or as two independent neurons (dual mode). Each neuron generates local signals.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: February 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Didier Louis, Pascal Tannhof, André Steimle
  • Patent number: 6513023
    Abstract: A neural network circuit is provided having a plurality of circuits capable of charge storage. Also provided is a plurality of circuits each coupled to at least one of the plurality of charge storage circuits and constructed to generate an output in accordance with a neuron transfer function. Each of a plurality of circuits is coupled to one of the plurality of neuron transfer function circuits and constructed to generate a derivative of the output. A weight update circuit updates the charge storage circuits based upon output from the plurality of transfer function circuits and output from the plurality of derivative circuits. In preferred embodiments, separate training and validation networks share the same set of charge storage circuits and may operate concurrently.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: January 28, 2003
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: Tuan A. Duong
  • Patent number: 6507828
    Abstract: A neuron circuit including means for synaptic modification is described. The circuit emulates the electrical behaviors of the neuron membrane, dendrite, and synapse, using principles based on the actual biology. In one embodiment, the circuit is implemented as an analog very large scale integrated (VLSI) circuit which utilizes CMOS integrated circuit technology. The analog VLSI circuit includes a synapse circuit having a circuit portion which models a mechanism for the modification of the synaptic conductance.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: January 14, 2003
    Inventors: Jason Leonard, Chi-Sang Poon
  • Patent number: 6505182
    Abstract: Detection is implemented by a multiplier, a lookup table or other apparatus with two inputs, one of which typically receives an input signal from a sensor, and the other a reference or weighting factor W stored or generated locally. The detected value is added to the contents of a memory location A after the previous contents of memory locations A have been modified by a loss or gain factor Q. Memory location A is one of several such memory locations in a shared memory simultaneously accessible by an external user. In a neural engine the memory locations represent neurons. For each cycle of operation of the neural engine a new value of W, Q and A are provided.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: January 7, 2003
    Inventor: Raymond C. Van den Heuvel
  • Patent number: 6456992
    Abstract: A semiconductor arithmetic circuit which compares the magnitudes of a plurality of data with each other in real time by using a simple circuit. The semiconductor arithmetic circuit containing one or more neuron MOS transistors each having a plurality of input gate electrodes has an inverter circuit group of a plurality of inverter circuit each of which is constituted of neuron MOS transistors and a means for applying a prescribed signal voltage to at least one first input gate of the inverter circuit.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: September 24, 2002
    Inventors: Tadashi Shibata, Tadahiro Ohmi, Tatsuo Morimoto, Ryu Kaiwara
  • Patent number: 6405184
    Abstract: A method for generating fault classification signals which identify faulty loops which develop in a multiphase energy supply network observed in the event of a fault from a protective device with a starting arrangement. To be able to generate such fault classification signals in a relatively simple manner, a neural network is used which is trained using input variables simulating faulty loops in the form of normalized resistance and reactance variables formed taking into consideration the starting characteristic of the starting arrangement. In the case of a fault, normalized resistance and reactance measured variables network for generating fault classification signals.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: June 11, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventors: Klaus Böhme, Andreas Jurisch
  • Patent number: 5956702
    Abstract: Each neural element of a column-structured recurrent neural network generates an output from input data and recurrent data provided from a context layer of a corresponding column. One or more candidates for an estimated value is obtained, and an occurrence probability is computed using an internal state by solving an estimation equation determined by the internal state output from the neural network. A candidate having the highest occurrence probability is an estimated value for unknown data. Thus, the internal state of the recurrent neural network is explicitly associated with the estimated value for data, and a data change can be efficiently estimated.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: September 21, 1999
    Assignee: Fujitsu Limited
    Inventors: Masahiro Matsuoka, Mostefa Golea