Abstract: Systems and methods for automatic classification of loan refinancing interactions and outcomes are disclosed. An example system may include a data collection circuit to collect a training set of loan interactions between entities, wherein the training set of loan interactions comprises a set of loan refinancing activities and a set of loan refinancing outcomes; an artificial intelligence circuit to classify the set of loan refinancing activities, wherein the artificial intelligence circuit is trained on the training set of loan interactions; and a robotic process automation circuit to perform a second loan refinancing activity on behalf of a party to a second loan, wherein the robotic process automation circuit is trained on the set of loan refinancing activities and the set of loan refinancing outcomes.

Abstract: Embodiments relate to a neural processor that includes one or more neural engine circuits and planar engine circuits. The neural engine circuits can perform convolution operations of input data with one or more kernels to generate outputs. The planar engine circuit is coupled to the plurality of neural engine circuits. A planar engine circuit can be configured to multiple modes. In a reduction mode, the planar engine circuit may process values arranged in one or more dimensions of input to generate a reduced value. The reduced values across multiple input data may be accumulated. The planar engine circuit may program a filter circuit as a reduction tree to gradually reduce the data into a reduced value. The reduction operation reduces the size of one or more dimensions of a tensor.

Abstract: A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.

Abstract: Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.

Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.

Abstract: A memory includes a row decoder that receives an address of a row to be read and an operand. The memory includes a memory array of bitcells that can be configured to store N-bit weight values in which N is an integer greater than one. The row decoder is configured to, for a multiplication mode read operation at the selected word line, selectively activate the selected word line based on a bit value of the received operand to selectively read an N-bit weight value based on a bit value of the operand. Such an operation may in some embodiments, perform a multiplication operation of the bit value of the operand and the N-bit weight value.

Abstract: An apparatus that performs the mathematical matrix-vector multiplication approximation operations using crossbar arrays of resistive memory devices (e.g. memristor, resistive random-access memory, spintronics, etc.). A crossbar array formed by resistive memory devices serves as a memory array that stores the coefficients of a matrix. Combined with input and output analog circuits, the crossbar array system realizes the method of performing matrix-vector multiplication approximation operations with significant performance, area and energy advantages over existing methods and designs. This invention also includes an extended method that realizes the auto-associative neural network recall function using the resistive memory crossbar architecture.

Abstract: A digital-to-analogue converter, with application to electronic circuits with neuromorphic architecture, comprises: transistors of identical nominal geometrical characteristics, but of dispersed current-voltage characteristics, wherein when a constant gate-source voltage is applied to the different transistors, a current varying as a function of the dispersion circulates in the transistor; a digital table receiving a digital word and having a selection output selecting, as a function of the word to be converted, a transistor or transistors supplying a current of desired value representing this word in analogue form. The look-up table is loaded as a function of real measured current-voltage characteristics of different transistors of the set, to establish a look-up between words and current values.

Abstract: A wireless communication system (20) includes a base station controller (22) that receives timing information from a data set (26) that is generated by a neural network (28). The data set (26) allows for generating timing information based upon previous time information received from a GPS (24) and in one example, is capable of covering a time interval of up to two weeks during which effective communication with the GPS may be interrupted. In one example, the data set is continuously updated so that the base station controller (24) continuously has up to two weeks of future time information available.

Abstract: A neural network has an array of interconnected processors, each processor operating either the pulse domain or spike domain.

Abstract: A computer-implemented marketplace (16) for providing financial transaction services to participants (12, 14, 60, 62) in connection with commercial transactions involving the participants (12, 14, 60, 62) includes a database (22). The database (22) contains registration information for types of transactions available to participants (12, 14, 60, 62) and participation criteria for each participant (12, 14, 60, 62) that specifies types of transactions in which the participant (12, 14, 60, 62) is willing to participate. Processes (24) provide associated financial transaction services for the participants (12, 14, 60, 62) in connection with ongoing transactions involving the participants (12, 14, 60, 62).

Abstract: We develop a system consisting of a neural architecture resulting in classifying regions corresponding to users' keystroke patterns. We extend the adaptation properties to classification phase resulting in learning of changes over time. Classification results on login attempts of 43 users (216 valid, 657 impersonation samples) show considerable improvements over existing methods.

Abstract: A system and method for inquiry of option and/or stock status and for processing trades made pursuant to stock option and purchase plans is provided. Participant information is stored and transmitted to a finance system. Rules may be enforced for stock option and stock purchase plans with the finance system. Participants are provided with incentive compensation that can be utilized in a simplified, user friendly, streamlined process.

Abstract: A nonrecurrent version of the Neural Network Binary Code Recognizer is disclosed. This Nonrecurrent Binary Code Recognizer, which decodes an input vector of n analog components into a decoded binary word of n bits, comprises an analog-to-digital converter, an inverter circuit, a digital summing circuit and a comparator circuit.