Having Digital Weight Patents (Class 706/37)
  • Patent number: 11475101
    Abstract: A method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 18, 2022
    Assignee: Imec VZW
    Inventors: Francky Catthoor, Praveen Raghavan, Dimitrios Rodopoulos, Mohit Dandekar
  • Patent number: 11423290
    Abstract: A semiconductor device includes an operation control signal generation circuit and a neural network circuit. The operation control signal generation circuit generates an arithmetic signal and a core read signal based on a command. The neural network circuit outputs first core data and second core data from a core region based on the core read signal, a cell block selection signal, and a cell selection signal. The neural network circuit also performs an arithmetic operation of the first and second core data based on the arithmetic signal to generate arithmetic result data.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 23, 2022
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 11216723
    Abstract: Disclosed herein is a neuromorphic integrated circuit, including in many embodiments, a neural network disposed in a multiplier array in a memory sector of the integrated circuit, and a plurality of multipliers of the multiplier array, a multiplier thereof including at least one transistor-based cell configured to store a synaptic weight of the neural network, an input configured to accept digital input pulses for the multiplier, an output configured to provide digital output pulses of the multiplier, and a charge integrator, where the charge integrator is configured to integrate a current associated with an input pulse of the input pulses over an input pulse width thereof, and where the multiplier is configured to provide an output pulse of the output pulses with an output pulse width proportional to the input pulse width.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: January 4, 2022
    Assignee: SYNTIANT
    Inventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
  • Patent number: 11144824
    Abstract: Various algorithms are disclosed for verifying the stored weight in a non-volatile memory cell in a neural network following a multilevel programming operation of the non-volatile memory cell by converting the stored weight into a plurality of digital output bits. Circuity, such as an adjustable reference current source, for implementing the algorithms are disclosed.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 12, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
  • Patent number: 10726331
    Abstract: Neural network circuits providing early integration before ADC are described. Comparators are adapted to compare a plurality of output analog voltages from a first synaptic array to a predetermined threshold to generate a vector of bits indicating whether the plurality of analog voltages exceed the predetermined threshold, and transmit the vector of bits via a network. At least one ADC is configured to convert the plurality of analog voltages to a vector of digital values, and transmit the vector of digital values via the network. At least one modulator is configured to receive the vector of bits from the network, provide pulses to each of a plurality of input wires of a second synaptic array based on the vector of bits, receive the vector of digital values from the network, and provide pulses to each of the plurality of input wires based on the vector of digital values.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Geoffrey W. Burr
  • Patent number: 10614355
    Abstract: A method for updating a weight of a synapse of a neuromorphic device is provided. The synapse may include a transistor and a memristor. The memristor may have a first electrode coupled to a source electrode of the transistor. The method may include inputting a row spike to a drain electrode of the transistor at a first time; inputting a column spike to a second electrode of the memristor at a second time; inputting a row pulse to the drain electrode of the transistor at a third time that is delayed by a first delay time from the second time; inputting a column pulse to the second electrode of the memristor at a fourth time that is delayed by a second delay time from the second time; and inputting a gating pulse to a gate electrode of the transistor at a fifth time that is delayed by a third delay time from the fourth time.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Patent number: 10585643
    Abstract: A fine-grained analog memory device includes: 1) a charge-trapping transistor including a gate and a high-k gate dielectric; and 2) a pulse generator connected to the gate and configured to apply a positive or negative pulse to the gate to change an amount of charges trapped in the high-k gate dielectric.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 10, 2020
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xuefeng Gu, Subramanian S. Iyer
  • Publication number: 20110119215
    Abstract: An analog-digital crosspoint-network includes a plurality of rows and columns, a plurality of synaptic nodes, each synaptic node of the plurality of synaptic nodes disposed at an intersection of a row and column of the plurality of rows and columns, wherein each synaptic node of the plurality of synaptic nodes includes a weight associated therewith, a column controller associated with each column of the plurality of columns, wherein each column controller is disposed to enable a weight change at a synaptic node in communication with said column controller, and a row controller associated with each row of the plurality of rows, wherein each row controller is disposed to control a weight change at a synaptic node in communication with said row controller.
    Type: Application
    Filed: November 13, 2009
    Publication date: May 19, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce G. Elmegreen, Ralph Linsker, Dennis M. Newns, Bipin Rajendran
  • Patent number: 7729953
    Abstract: In an example embodiment, a method is provided. The method may comprise receiving an auction item identifier from a global positioning system (GPS) apparatus. Auction data associated with the auction item identifier is accessed and transmitted to a voice portal server. The voice portal server may call a telephone number and receive a request to acquire the auction item.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: June 1, 2010
    Assignee: eBay Inc.
    Inventor: Senthil K. Pandurangan
  • Patent number: 7620819
    Abstract: We develop a system consisting of a neural architecture resulting in classifying regions corresponding to users' keystroke patterns. We extend the adaptation properties to classification phase resulting in learning of changes over time. Classification results on login attempts of 43 users (216 valid, 657 impersonation samples) show considerable improvements over existing methods.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: November 17, 2009
    Assignees: The Penn State Research Foundation, Louisiana Tech University Foundation, Inc.
    Inventors: Vir V. Phoha, Sunil Babu, Asok Ray, Shashi P. Phoba
  • Publication number: 20080114711
    Abstract: Methods and apparatus for encoding data in a communication network. In an aspect, a method is provided for coding data. The method includes generating one or more permutations of the data, determining weights associated with each permutation, calculating one or more code packets from each permutation based on the associated weights, and multiplexing the data and the one or more code packets into a code packet stream. In an aspect, an apparatus is provided for coding data. The apparatus includes permutation logic configured to generate one or more permutations of the data, and weight logic configured to determine weights associated with each permutation. The apparatus also includes processing logic configured to calculate one or more code packets from each permutation based on the associated weights, and a multiplexer configured to multiplex the data and the one or more code packets into a code packet stream.
    Type: Application
    Filed: March 26, 2007
    Publication date: May 15, 2008
    Inventor: Thadi M. Nagaraj
  • Patent number: 7296006
    Abstract: Described are systems and methods for determining the gross weight of an aircraft. A flight regime is determined based on one or more inputs. A neural net is selected based on a flight regime. The neural net inputs may include derived values. A first estimate of the gross weight is produced by the selected neural net. The first estimate is used, along with other inputs, with a Kalman filter to produce a final gross weight estimate. The Kalman filter blends or fuses together its inputs to produce the final gross weight estimate.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: November 13, 2007
    Assignee: Simmonds Precision Products, Inc.
    Inventors: Timothy D. Flynn, Robert Alan Hess, Barbara Noble
  • Patent number: 7281001
    Abstract: A system (1) generates an output indicating scores for the extent of matching of pairs of data records. Thresholds may be set for the scores for decision-making or human review. A vector extraction module (12) measures similarity of pairs of fields in a pair of records to generate a vector. The vector is then processed to generate a score for the record pair.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: October 9, 2007
    Assignee: Informatica Corporation
    Inventors: Brian Caulfield, Garry Moroney, Padraig Cunningham, Ronan Pearce, Gary Ramsay, Sarah-Jane Delany
  • Patent number: 7272585
    Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: September 18, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Osamu Nomura, Takashi Morie, Teppei Nakano
  • Patent number: 7143073
    Abstract: The invention relates to generating a test suite of instructions for testing the operation of a processor. A fuzzy finite state machine with a plurality of states 2 and transitions 4 determined by weights W1, W2 . . . W10 is used to generate a sequence of instructions. The weights determine the next state as well as an instruction and operands for each state. The weights may be adapted based on the generated sequence and further sequences are generated.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: November 28, 2006
    Assignee: Broadcom Corporation
    Inventor: Geoff Barrett
  • Patent number: 6625588
    Abstract: An associative artificial neuron and method of forming output signals of an associative artificial neuron includes receiving a number of auxiliary input signals; forming from the auxiliary input signals a sum weighted by coefficients and applying a non-linear function to the weighted sum to generate a non-linear signal. The neuron and method further include receiving a main input signal and forming, based on the main signal and the non-linear signal, the function S OR V, which is used to generate a main output signal, and at lest one of three logical functions S AND V, NOT S AND V, and S AND NOT V. The at least one logical function is used to generate an additional output signal for the associative artificial neuron.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: September 23, 2003
    Assignee: Nokia OYJ
    Inventor: Pentti Haikonen
  • Patent number: 6424956
    Abstract: An artificial intelligence system is provided which makes use of a dual subroutine to adapt weights. Elastic Fuzzy Logic (“ELF”) System is provided in which classical neural network learning techniques are combined with fuzzy logic techniques in order to accomplish artificial intelligence tasks such as pattern recognition, expert cloning and trajectory control. The system may be implemented in a computer provided with multiplier means and storage means for storing a vector of weights to be used as multiplier factors in an apparatus for fuzzy control.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: July 23, 2002
    Inventor: Paul J. Werbos