Abstract: Disclosed is an accelerator and a method of operating the accelerator including determining whether any group shares weights of a first group from among groups, determining a presence of an idle processing element (PE) array, in response to no group sharing the weights of the first group, and selecting a second group having a memory time overlapping a computation time of the first group from among the groups, in response to the idle PE array being present.

Abstract: An efficient technique of machine learning is provided for training a plurality of convolutional neural networks (CNNs) with increased speed and accuracy using a genetic evolutionary model. A plurality of artificial chromosomes may be stored representing weights of artificial neuron connections of the plurality of respective CNNs. A plurality of pairs of the chromosomes may be recombined to generate, for each pair, a new chromosome (with a different set of weights than in either chromosome of the pair) by selecting entire filters as inseparable groups of a plurality of weights from each of the pair of chromosomes (e.g., “filter-by-filter” recombination). A plurality of weights of each of the new or original plurality of chromosomes may be mutated by propagating recursive error corrections incrementally throughout the CNN. A small random sampling of weights may optionally be further mutated to zero, random values, or a sum of current and random values.

Abstract: A method includes receiving a set of data. The set of data is divided into a plurality of data portions. The method includes transmitting the plurality of data portions to a plurality of processing tiles, wherein each data portion of the plurality of data portions is associated with a processing tile of a plurality of tiles. Each processing tile of the plurality of tiles performs at least one local operation on its respective data portion to form a local result. The method includes exchanging local results between the plurality of processing tiles. Moreover, the method includes calculating a global value based on the local results. The method further includes performing at least one local operation by each processing tile of the plurality of tiles on its respective data portion based on the global value to form a computed result.

Abstract: An inference device comprises a weight storage part that stores weights, an input data storage part that stores input data, and a PE (Processing Element) that executes convolution computation in convolutional neural network using the weights and input data. The PE adds up weight elements to be multiplied with elements of the input data for each of variable values of the elements of the input data. The PE multiplies each of the variable values of the elements of the input data with each cumulative sum value of weights corresponding to the variable values of the elements of the input data. The PE adds up a plurality of multiplication results obtained by the multiplications.

Abstract: There are increasing needs of searching on which data in a storage circuit is most similar to input information from the outside. Expectations for storage circuits having such memory techniques are high, and to enable a computer to handle information from the outside more flexibly is considered an essential technique. To achieve such techniques, a storage circuit needs to have a function of measuring a degree of similarity between stored data and input data. In an approximate-search-circuit, a memory matrix of a conventional storage circuit is caused to function as a data conversion circuit for calculating the inner-product distance between stored data and input data, by inputting the input data to the memory matrix in the form of a time series of pulse-signals, and the location of stored data with the highest inner-product is output from a circuit that calculates the inner-product in real time.

Abstract: Embodiments of serial neural network configuration and processing via a common serial bus are disclosed. In some embodiments, the input data and source identification data is sent to nodes of the neural network serially. The nodes can determine whether the source identification data matches with an address for the node. If the address matches, the node can store the input data in its register for further processing. In some embodiments, the serial neural network engine can include a common serial bus that can broadcast data across multiple processor chips or cores.

Abstract: Disclosed is a parallel processor. The parallel processor includes a processing element array including a plurality of processing elements arranged in rows and columns, a row memory group including row memories corresponding to rows of the processing elements, a column memory group including column memories corresponding to columns of the processing elements, and a controller to generate a first address and a second address, to send the first address to the row memory group, and to send the second address to the column memory group. The controller supports convolution operations having mutually different forms, by changing a scheme of generating the first address.

Abstract: Embodiments of the present disclosure implement a stochastic neural network (SNN) where nodes are selectively activated depending on the inputs and which can be trained on multiple objectives. A system can include one or more nodes and one or more synapses, wherein each synapse connects a respective pair of the plurality of nodes. The system can further include one or more processing elements, wherein each of the processing elements is embedded in a respective synapse, and wherein each of the processing elements is adapted to receive an input and generate an output based on the input. The system can be configured to operate such that, upon receipt of a first problem input, a first subset of the nodes in the system is selectively activated. Upon receipt of a second problem input, a second subset of the nodes is selectively activated. The second subset of nodes can be different from the first subset of nodes. In various embodiments, the first and second subsets of nodes can be selectively activated in parallel.

Abstract: Devices and methods for systolically processing data according to a neural network. In one aspect, a first arrangement of processing units includes at least first, second, third, and fourth processing units. The first and second processing units are connected to systolically pulse data to one another, and the third and fourth processing units are connected to systolically pulse data to one another. A second arrangement of processing units includes at least fifth, sixth, seventh, and eighth processing units. The fifth and sixth processing units are connected to systolically pulse data to one another, and the seventh and eighth processing units are connected to systolically pulse data to one another. The second processing unit is configured to systolically pulse data to the seventh processing unit along a first interconnect and the third processing unit is configured to systolically pulse data to the sixth processing unit along a second interconnect.

Abstract: A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.

Abstract: A neural network arithmetic processing device is capable of implementing a further increase in speed and efficiency of multiply-accumulate arithmetic operation, suppressing an increase in circuit scale, and performing multiply-accumulate arithmetic operation with simple design. A neural network arithmetic processing device includes a first multiply-accumulate arithmetic unit, a register connected to the first multiply-accumulate arithmetic unit, and a second multiply-accumulate arithmetic unit connected to the register. The first multiply-accumulate arithmetic unit has a first memory, a second memory, a first multiplier, a first adder, and a first output unit. The second multiply-accumulate arithmetic unit has an input unit, a third memory, second multipliers, second adders, and second output units.

Abstract: A neural network system includes an input layer, one or more hidden layers, and an output layer. A first layer circuit implements a first layer of the one or more hidden layers. The first layer includes a first weight space including one or more subgroups. A forward path circuit of the first layer circuit includes a multiply and accumulate circuit to receive an input from a layer preceding the first layer; and provide a first subgroup weighted sum using the input and a first plurality weights associated with a first subgroup. A scaling coefficient circuit provides a first scaling coefficient associated with the first subgroup, and applies the first scaling coefficient to the first subgroup weighted sum to generate a first subgroup scaled weighted sum. An activation circuit generates an activation based on the first subgroup scaled weighted sum and provide the activation to a layer following the first layer.

Abstract: Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. Each cell of the matrix multiply includes: a weight matrix register configured to receive a weight input from either a transposed or a non-transposed weight shift register; a transposed weight shift register configured to receive a weight input from a horizontal direction to be stored in the weight matrix register; a non-transposed weight shift register configured to receive a weight input from a vertical direction to be stored in the weight matrix register; and a multiply unit that is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.

Abstract: A system for applying a fluid to a substrate bearing a sample for analysis has an array of sensor plates positioned to sense the presence of fluid in contact with respective areas of the substrate. In a particular embodiment, fluid presence in different areas of the substrate is sensed by the effect of the fluid and its identity on the impedances of capacitors formed between sensor plates within the array. In a more particular embodiment, by polling the sensor array continually while fluid is applied to the substrate determine a coverage map, a fluid dispensing mechanism can be controlled to efficiently cover the entire substrate with fluid a minimal amount of fluid, thereby reducing waste.

Abstract: A shared database platform implements dynamic masking on data shared between users where specific data is masked, transformed, or otherwise modified based on preconfigured functions that are associated with user roles. The shared database platform can implement the masking at runtime dynamically in response to users requesting access to a database object that is associated with one or more masking policies.

Abstract: A method of performing computations of a neural network is disclosed comprising assigning a first processing unit to perform computations of a first node of a first layer of the neural network and assigning a second processing unit to perform computations of a second node of a second layer of the neural network. Computations of the first node are performed using the first processing unit to generate a first activation output that is transmitted to a first output systolic element of the first processing unit. The first activation output is systolically pulsed to a first input systolic element of the second processing unit and computations of the second node are performed by using the second processing unit to process at least the first activation output.

Abstract: A method of computer processing is disclosed comprising receiving a data packet at a processing node of a neural network, performing a calculation of the data packet at the processing node to create a processed data packet, attaching a tag to the processed data packet, transmitting the processed data packet from the processing node to a receiving node during a systolic pulse, receiving the processed data packet at the receiving node, performing a clockwise convolution on the processed data packet and a counter clockwise convolution on the processed data packet, performing an adding function and backpropagating results of the performed sigmoid function to each of the processing nodes that originally processed the data packet.

Abstract: A system to support a machine learning (ML) operation comprises a core configured to receive and interpret commands into a set of instructions for the ML operation and a memory unit configured to maintain data for the ML operation. The system further comprises an inference engine having a plurality of processing tiles, each comprising an on-chip memory (OCM) configured to maintain data for local access by components in the processing tile and one or more processing units configured to perform tasks of the ML operation on the data in the OCM. The system also comprises an instruction streaming engine configured to distribute the instructions to the processing tiles to control their operations and to synchronize data communication between the core and the inference engine so that data transmitted between them correctly reaches the corresponding processing tiles while ensuring coherence of data shared and distributed among the core and the OCMs.

Abstract: In one embodiment, a kernel of an operating system receives a request to store a message in a message buffer, which includes a plurality of chunks. Each chunk of the message buffer is associated with a message-occupancy indicator. The kernel determines a start and end position of the message when stored in the message buffer. The kernel determines, based on the start and end positions, whether the message, when stored, will occupy more than one chunk. Responsive to determining that the message will occupy more than one chunk, the kernel determines each chunk that will contain the message when stored. If a message occupancy-indicator associated with each chunk indicates that at least each chunk after a first chunk associated with the start position is unoccupied, the kernel stores the message in the message buffer and updates the message-occupancy indicator for each chunk containing the stored message.

Abstract: Implementing a neural network can include receiving a macro instruction for implementing the neural network within a control unit of a neural network processor. The macro instruction can indicate a first data set, a second data set, a macro operation for the neural network, and a mode of operation for performing the macro operation. The macro operation can be automatically initiated using a processing unit of the neural network processor by applying the second data set to the first data set based on the mode of operation.

Abstract: A machine learning system includes a coach machine learning system that uses machine learning to help a student machine learning system learn its system. By monitoring the student learning system, the coach machine learning system can learn (through machine learning techniques) “hyperparameters” for the student learning system that control the machine learning process for the student learning system. The machine learning coach could also determine structural modifications for the student learning system architecture. The learning coach can also control data flow to the student learning system.

Abstract: In one embodiment, a processor comprises a first neuro-synaptic core comprising first circuitry to configure the first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter.

Abstract: Systems and methods for neural network processing are provided. A method in a system comprising a plurality of nodes interconnected via a network, where each node includes a plurality of on-chip memory blocks and a plurality of compute units, is provided. The method includes upon service activation receiving an N by M matrix of coefficients corresponding to the neural network model. The method includes loading the coefficients corresponding to the neural network model into the plurality of the on-chip memory blocks for processing by the plurality of compute units. The method includes regardless of a utilization of the plurality of the on-chip memory blocks as part of an evaluation of the neural network model, maintaining the coefficients corresponding to the neural network model in the plurality of the on-chip memory blocks until the service is interrupted or the neural network model is modified or replaced.

Abstract: Processors and methods for neural network processing are provided. A method in a processor including a pipeline having a matrix vector unit (MVU), a first multifunction unit connected to receive an input from the matrix vector unit, a second multifunction unit connected to receive an output from the first multifunction unit, and a third multifunction unit connected to receive an output from the second multifunction unit is provided. The method includes decoding a chain of instructions received via an input queue, where the chain of instructions comprises a first instruction that can only be processed by the matrix vector unit and a sequence of instructions that can only be processed by a multifunction unit. The method includes processing the first instruction using the MVU and processing each of instructions in the sequence of instructions depending upon a position of the each of instructions in the sequence of instructions.

Abstract: The present application discloses a computing device and a neural network processor including the computing device. The computing device includes one or more columns of computing units arranged in an array, wherein at least one computing unit in each column comprises: an arithmetic parameter memory for storing one or more arithmetic parameters; an arithmetic logical unit (ALU) for receiving input data and performing computation on the input data using the one or more arithmetic parameters stored in the arithmetic parameter memory; and an address controller for providing an address control signal to the arithmetic parameter memory to control the storage and output of the one or more arithmetic parameters.

Abstract: Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a compute element and a routing element. Each compute element has memory. Each router enables communication via wavelets with at least nearest neighbors in a 2D mesh. Routing is controlled by respective virtual channel specifiers in each wavelet and routing configuration information in each router. A compute element conditionally selects for task initiation a previously received wavelet specifying a particular one of the virtual channels. The conditional selecting excludes the previously received wavelet for selection until at least block/unblock state maintained for the particular virtual channel is in an unblock state. The compute element executes block/unblock instructions to modify the block/unblock state.

Abstract: A shared database platform implements dynamic masking on data shared between users where specific data is masked, transformed, or otherwise modified based on preconfigured functions that are associated with user roles. The shared database platform can implement the masking at runtime dynamically in response to users requesting access to a database object that is associated with one or more masking policies.

Abstract: A method for analog-to-digital conversion with reconfigurable function mapping for acceleration of calculating an activation function of a neural network system includes determining, by a shared circuit, a set of voltage intervals using digital bits in a look-up table to define a shape of the activation function being mapped. The shared circuit determines a set of most significant bits (MSBs) for each voltage interval by storing additional bits in the look-up table corresponding to each voltage interval entry. Further, each of several per-neuron circuits determines whether its accumulated input voltage is in a received voltage interval, and if so, causing the set of MSBs to be stored. Each of the per-neuron circuits determines a set of least significant bits (LSBs) by performing a linear interpolation over the voltage interval. The set of MSBs and the set of LSBs are output as a result of the activation function with analog-to-digital conversion.

Abstract: Systems and methods for caching data in artificial neural network computations are disclosed. An example method may comprise receiving, by a communication unit, data and a logical address of the data, the data being associated with the ANN, determining, by a processing unit coupled to the communication unit and to a plurality of physical memories and based on the logical address and physical parameters of the physical memories, a physical address of a physical memory of the plurality of physical memories, and performing, by the processing unit, an operation associated with the data and the physical address. The determination of the physical address can be based on a usage count of the data in the ANN computation or a time lapse between a time the data is written to the physical memory and a time the data is used in the ANN computation.

Abstract: The present invention relates to the field of analog integrated circuits, and provides a multiply-accumulate calculation method and circuit suitable for a neural network, which realizes large-scale multiply-accumulate calculation of the neural network with low power consumption and high speed. The multiply-accumulate calculation circuit comprises a multiplication calculation circuit array and an accumulation calculation circuit. The multiplication calculation circuit array is composed of M groups of multiplication calculation circuits. Each group of multiplication calculation circuits is composed of one multiplication array unit and eight selection-shift units. The order of the multiplication array unit is quantized in real time by using on-chip training to provide a shared input for the selection-shift units, achieving increased operating rate and reduced power consumption.

Abstract: There is provided an information processing apparatus and an information processing method to present information for improving development efficiency of a neural network to a user. The information processing method includes: providing, by a processor, a form for creating a program for establishing a neural network on a basis of a disposed component and property set for the component; and presenting statistical information relating to the neural network. The information processing apparatus includes a form control unit configured to provide a form for creating a program for establishing a neural network on a basis of a disposed component and property set for the component. The form control unit presents statistical information relating to the neural network.

Abstract: A shared database platform implements dynamic masking on data shared between users where specific data is masked, transformed, or otherwise modified based on preconfigured functions that are associated with user roles. The shared database platform can implement the masking at runtime dynamically in response to users requesting access to a database object that is associated with one or more masking policies.

Abstract: Provided are systems, methods, and integrated circuits neural network processor that can execute a fast context switch between one neural network and another. In various implementations, a neural network processor can include a plurality of memory banks storing a first set of weight values for a first neural network. When the neural network processor receives first input data, the neural network processor can compute a first result using the first set of weight values and the first input data. While computing the first result, the neural network processor can store, in the memory banks, a second set of weight values for a second neural network. When the neural network processor receives second input data, the neural network processor can compute a second result using the second set of weight values and the second input data, where the computation occurs upon completion of computation of the first result.

Abstract: A neural network processing system includes one source node having a source memory and a source core, and one destination node having a destination memory and a destination core, the source core and the destination core being von-Neumann cores, the destination memory including weight data storage areas for storing weight data corresponding to each node, an accumulation memory for accumulating the weight data, and an event address memory, the destination core identifying the weight data storage area and accumulating the weight data to store the accumulated weight data in the accumulation memory, the source memory including a data set having first information for identifying the destination node and second information for identifying the weight data storage area, and the source core reading the data set and sending the second information in the data set to the destination node to conduct remote memory write.

Abstract: Each energy value calculation circuit calculates an energy value, based on a sum total of values obtained by multiplying state values of a plurality of second neurons coupled with a first neuron by corresponding weighting values indicating coupling strengths, and updates the energy value, based on identification information of an updated neuron whose state is updated among the plurality of second neurons and a state value of the updated neuron. Each state transition determination circuit outputs, based on a second energy value and a noise value, a determination signal indicating a determination result of whether a change in a state value of the first neuron is possible. An updated neuron selection circuit selects, based on received determination signals, a first neuron a change in whose state value is possible and outputs identification information of the selected first neuron as identification information of the updated neuron.

Abstract: Aspects for backpropagation of a convolutional neural network are described herein. The aspects may include a direct memory access unit configured to receive input data from a storage device and a master computation module configured to select one or more portions of the input data based on a predetermined convolution window. Further, the aspects may include one or more slave computation modules respectively configured to convolute one of the one or more portions of the input data with one of one or more previously calculated first data gradients to generate a kernel gradient, wherein the master computation module is further configured to update a prestored convolution kernel based on the kernel gradient.

Abstract: Disclosed aspects relate to processing element host management in a stream computing environment having a pool of compute nodes to host a set of processing elements. A set of processing element placement criteria may be identified for the pool of compute nodes with respect to processing element placement on the pool of compute nodes. A set of processing element profile data may be detected for the set of processing elements with respect to processing element placement on the pool of compute nodes. By comparing the set of processing element profile data and the set of processing element placement criteria, a placement arrangement for the set of processing elements on the pool of compute nodes may be determined. Based on the placement arrangement, the set of processing elements may be established on the pool of compute nodes.

Abstract: Techniques for transitioning between code-based and data-based execution forms (or models) are disclosed. The techniques can be used to improve the performance of computing systems by allowing the execution to transition from one of the execution models to another one of the execution models that may be more suitable for carrying out the execution or effective processing of information in a computing system or environment. The techniques also allow switching back to the previous execution model when that previous model is more suitable than the execution model currently being used. In other words, the techniques allow transitioning (or switching) back and forth between a data-based and code-based execution (or information processing) models.

Abstract: A device that includes a node engine configured to emulate a first node, a second node, and a third node. The first node is configured to receive a first correlithm object, fetch a second correlithm object based on the first correlithm object, and output the second correlithm object to the second node and the third node. Each correlithm object is a point in an n-dimensional space represented by a binary string. The second node is configured to receive the second correlithm object, fetch a third correlithm object based on the second correlithm object, and output the third correlithm object to the third node. The third node is configured to receive the second correlithm object, receive the third correlithm object, fetch a fourth correlithm object based on the second correlithm object and the third correlithm object, and output the fourth correlithm object.

Abstract: Disclosed is a method and apparatus for an environmental control system in which a genetic learning algorithm creates scenes and scene triggers and in which a fitness function scores the scenes through end-user interaction.

Abstract: Systems and methods may automatically generate code for deep learning networks. The systems methods may provide a code generation framework for generating target specific code. The code generation framework may include one or more predefined class hierarchies for constructing objects of the generated code. The objects of the class hierarchies may provide an interface to predefined libraries of deep learning functions optimized for use on a target platform. The systems and methods may perform one or more optimizations on the code being generated.

Abstract: A system, method and computer program product for achieving a collective task. The system comprises a plurality of elements representative of a first hierarchy level, each element comprises a plurality of sub-elements. The system comprises also an arbitration module for selecting one of the sub-elements of each element at a point in time based on a global clock, wherein each sub-element relates to one list element of an ordered circular list, and a combination module adapted for a combination of sub-actions performed by a portion of the sub-elements of one of the elements over a predefined period of time, wherein each sub-element performs one of the sub-actions.

Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.

Abstract: Efficient updates of connections in artificial neuron networks may be implemented. A framework may be used to describe the connections using a linear synaptic dynamic process, characterized by stable equilibrium. The state of neurons and synapses within the network may be updated, based on inputs and outputs to/from neurons. In some implementations, the updates may be implemented at regular time intervals. In one or more implementations, the updates may be implemented on-demand, based on the network activity (e.g., neuron output and/or input) so as to further reduce computational load associated with the synaptic updates. The connection updates may be decomposed into multiple event-dependent connection change components that may be used to describe connection plasticity change due to neuron input. Using event-dependent connection change components, connection updates may be executed on per neuron basis, as opposed to per-connection basis.

Abstract: Systems and methods to process packets of information using an on-chip processing system include a memory bank, an interconnect module, a controller, and one or more processing engines. The packets of information include a packet header and a packet payload. The packet header includes one or more operator codes. The transfer of individual packets is guided to a processing engine through the interconnect module and through the controller by operator codes included in the packets.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.

Abstract: A method of generating neuron spiking pulses in a neuromorphic system is provided which includes floating one or more selected bit lines connected to target cells, having a first state, from among a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; and stepwisely increasing voltages applied to unselected word lines connected to unselected cells, having a second state, from among memory cells connected to the one or more selected bit lines other than the target cells having the first state.

Abstract: According to one embodiment, a behavior estimation apparatus includes a storage unit, a first calculation unit, a second calculation unit, and an estimation unit. The storage unit stores first data collecting power values consumed by a consumer in a period. The first calculation unit calculates second data representing a frequency of each power value by using the first data. The second calculation unit calculates a first threshold to divide a first power value from a second power value which is larger than and next to the first power value, among power values corresponding to maximal values of frequencies included in the second data. The estimation unit obtains a power value consumed by the consumer in an estimating period, and estimates the consumer's behavior status in the estimating period by using the power value and the first threshold.

Abstract: Apparatus and methods for developing parallel networks. Parallel network design may comprise a general purpose language (GPC) code portion and a network description (ND) portion. GPL tools may be utilized in designing the network. The GPL tools may be configured to produce network specification language (NSL) engine adapted to generate hardware optimized machine executable code corresponding to the network description. The developer may be enabled to describe a parameter of the network. The GPC portion may be automatically updated consistent with the network parameter value. The GPC byte code may be introspected by the NSL engine to provide the underlying source code that may be automatically reinterpreted to produce the hardware optimized machine code. The optimized machine code may be executed in parallel.

Abstract: A system for timely standby power generation supplementing a solar array during periods of cloud coverage, including a power plant comprising solar arrays for normal power production during periods of maximum or reduced solar influx, and distributed generating sets (DGS) for standby power generation to supplement the solar arrays during periods of cloud coverage. A weather station has sensors for acquiring real-time meteorological data in the vicinity of the power plant and a processor for processing the acquired meteorological data so as to generate data related to a solar influx reduction event at the power plant including an event starting time. A controller receives the event data from the processor and operating the DGS in response to the received event data.