Digital Neural Network Patents (Class 706/41)
  • Patent number: 10963779
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for performing operations using data from a data source. In one aspect, a method includes a neural network system including a controller neural network configured to: receive a controller input for a time step and process the controller input and a representation of a system input to generate: an operation score distribution that assigns a respective operation score to an operation and a data score distribution that assigns a respective data score in the data source. The neural network system can also include an operation subsystem configured to: perform operations to generate operation outputs, wherein at least one of the operations is performed on data in the data source, and combine the operation outputs in accordance with the operation score distribution and the data score distribution to generate a time step output for the time step.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: March 30, 2021
    Assignee: Google LLC
    Inventors: Quoc V. Le, Ilya Sutskever, Arvind Neelakantan
  • Patent number: 10963403
    Abstract: The performance of a neural network (NN) can be limited by the number of operations being performed. Using a line buffer that is directed to shift a memory block by a selected shift stride for cooperating neurons, data that is operatively residing memory and which would require multiple write cycles into a cooperating line buffer can be processed as in a single line buffer write cycle thereby enhancing the performance of a NN/DNN. A controller and/or iterator can generate one or more instructions having the memory block shifting values for communication to the line buffer. The shifting values can be calculated using various characteristics of the input data as well as the NN/DNN inclusive of the data dimensions. The line buffer can read data for processing, shift the data of the memory block and write the data in the line buffer for subsequent processing.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: March 30, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: George Petre, Chad Balling McBride, Amol Ashok Ambardekar, Kent D. Cedola, Boris Bobrov, Larry Marvin Wall
  • Patent number: 10891542
    Abstract: An individual neuron circuit calculates a first value based on a sum of products each obtained by multiplying one of weight values, each representing connection or disconnection between a corresponding neuron circuit and one of the other neuron circuits, by a corresponding one of output signals of the other neuron circuits and outputs 0 or 1, based on a result of comparison between a second value obtained by adding a noise value to the first value and a threshold. An arbitration circuit allows, when first output signals of first neuron circuits interconnected among the neuron circuits simultaneously change based on the weight values, updating of only one of the first output signals of the first neuron circuits and allows, when second output signals of second neuron circuits not interconnected simultaneously change, updating of the second output signals.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: January 12, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Satoshi Matsubara, Hirotaka Tamura
  • Patent number: 10803127
    Abstract: A record management system retrieves relevance information through an information retrieval model that models relevance between users, queries, and records based on user interaction data with records. Relevance information between different elements of the record management system are determined through a set of learned transformations in the information retrieval model. The record management system can quickly retrieve relevance information between different elements of the record management system given the set of learned transformations in the information retrieval model, without the need to construct separate systems for different types of relevance information. Moreover, even without access to contents of records, the record management system can determine relevant records for a given query based on user interaction data and the determined relationships between users, queries, and records learned through the information retrieval model.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 13, 2020
    Assignee: salesforce.com, inc.
    Inventors: Zachary Alexander, Siddharth Rajaram, Tracy Morgan Backes, Scott Thurston Rickard, Jr.
  • Patent number: 10748058
    Abstract: A method and system are provided for updating a neuron membrane potential in a spike time dependent plasticity model in a Neuromorphic system. The method includes approximating a shape of an analog spike signal from an axon input using a hardware-based digital axon timer. The method further includes generating a first intermediately updated neuron membrane potential value from a current axon timer value, a current synapse weight value and a current neuron membrane potential value using a first look-up table and an accumulator. The method also includes generating a second intermediately updated neuron membrane potential value with a leak decay effect using a second look-up table and the first intermediately updated neuron membrane potential value. The method additionally includes generating a final updated neuron membrane potential value based on a comparison of the second intermediately updated neuron membrane potential value with a neuron fire threshold level using a comparator.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Yutaka Nakamura, Junka Okazawa, Takeo Yasuda
  • Patent number: 10690767
    Abstract: A system and method for forming synthetic aperture radar images. Radar return pulses are grouped into sub-dwells, and their frequency content is separated into frequency sub-bands. A coarse image is formed for each sub-band/sub-dwell combination. The coarse images are iteratively interpolated to higher resolution and combined, to form a single high-resolution synthetic aperture radar image.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: June 23, 2020
    Assignee: RAYTHEON COMPANY
    Inventor: Charles T. Hansen
  • Patent number: 10650302
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for augmenting neural networks with an external memory. One of the methods includes providing an output derived from a first portion of a neural network output as a system output; determining one or more sets of writing weights for each of a plurality of locations in an external memory; writing data defined by a third portion of the neural network output to the external memory in accordance with the sets of writing weights; determining one or more sets of reading weights for each of the plurality of locations in the external memory from a fourth portion of the neural network output; reading data from the external memory in accordance with the sets of reading weights; and combining the data read from the external memory with a next system input to generate the next neural network input.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: May 12, 2020
    Assignee: DeepMind Technologies Limited
    Inventors: Alexander Benjamin Graves, Ivo Danihelka, Gregory Duncan Wayne
  • Patent number: 10623775
    Abstract: A system (e.g., an auto-encoder system) includes an encoder, a decoder and a learning module. The encoder generates compressed video data using a lossy compression algorithm, the lossy compression algorithm being implemented using a trained neural network with at least one convolution, generate at least one first parameter based on the compressed video data, and communicate the compressed video data and the model to at least one device configured to decode the compressed video data using an inverse algorithm based on the lossy compression algorithm. The decoder generates decoded video data based on the compressed video data using the inverse algorithm and the model, and generate at least one second parameter based on the decoded video data. The learning module trains the model using the at least one first parameter and the at least one second parameter.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: April 14, 2020
    Assignee: Twitter, Inc.
    Inventors: Lucas Theis, Ferenc Huszar, Zehan Wang, Wenzhe Shi
  • Patent number: 10621490
    Abstract: According to an embodiment, a semiconductor device includes M write word lines, M read word lines, N write bit lines, N read bit lines, N source lines, and M×N cells. The M×N cells are arranged in a matrix including M rows×N columns. A cell in an m-th row×an n-th column includes a first FET, a second FET, and a capacitor. The first FET is connected to an m-th write word line at a gate, to an n-th write bit line at a drain, and to a source of the second FET at a source. The second FET is connected to an m-th read word line at a gate and to an n-th read bit line at a drain. The capacitor is connected to an n-th source line at one end and to the source of the first RET at the other end.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: April 14, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chika Tanaka, Keiji Ikeda
  • Patent number: 10586148
    Abstract: A memory holds D rows of N words and receives an address having log2 D bits and an extra bit. Each of N processing units (PU) of index J has first and second registers, an accumulator, an arithmetic unit that performs an operation thereon to accumulate a result, and multiplexing logic receiving memory word J, and for PUs 0 to (N/2)?1 also memory word J+(N/2). In a first mode, the multiplexing logic of PUs 0 to N?1 selects word J to output to the first register. In a second mode: when the extra bit is a zero, the multiplexing logic of PUs 0 to (N/2)?1 selects word J to output to the first register, and when the extra bit is a one, the multiplexing logic of PUs 0 through (N/2)?1 selects word J+(N/2) to output to the first register.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: March 10, 2020
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Kim C. Houck, Parviz Palangpour
  • Patent number: 10581435
    Abstract: An asynchronous circuit and methods for requesting that an action is triggered. The circuit performs the following steps: 1) receive a plurality of input signals, the input signals each having a first transition between states at a different time, 2) select one of the input signals based on the time of its first transition compared to the time of the first transition of the other input signals, 3) provide a request to an action block to: i) trigger the action in response to receiving the request, and ii) to provide an acknowledgement upon completion of the action, wherein the request and the action are dependent on the input signal that was selected, 4) receive the acknowledgement from the action block, and 5) initiate steps 1) to 4) for a second transition of the input signals after the plurality of input signals have undergone their first transitions.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 3, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Danil Sokolov, Viktor Khomenko, Alex Yakovlev
  • Patent number: 10453277
    Abstract: Systems and methods are provided for retrieving values from a data bus of a vehicle. One illustrative method includes applying values from sensors at a vehicle to addresses of a data bus at the vehicle, retrieving values from the addresses of the data bus based on an operational state of the vehicle, and determining that the vehicle has entered another operational state. The method further includes loading a second sampling scheme corresponding with the other operational state, and retrieving values from an address of the data bus at a new rate corresponding with the other operational state.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 22, 2019
    Assignee: The Boeing Company
    Inventors: David A. Followell, Kevin Swearingen
  • Patent number: 10410117
    Abstract: A method for creating a dynamic neural function library that relates to Artificial Intelligence systems and devices is provided. Within a dynamic neural network (artificial intelligent device), a plurality of control values are autonomously generated during a learning process and thus stored in synaptic registers of the artificial intelligent device that represent a training model of a task or a function learned by the artificial intelligent device. Control Values include, but are not limited to, values that indicate the neurotransmitter level that is present in the synapse, the neurotransmitter type, the connectome, the neuromodulator sensitivity, and other synaptic, dendric delay and axonal delay parameters. These values form collectively a training model. Training models are stored in the dynamic neural function library of the artificial intelligent device.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: September 10, 2019
    Assignee: BRAINCHIP, INC.
    Inventor: Peter A J van der Made
  • Patent number: 10387771
    Abstract: A system for bit-serial computation in a neural network is described. The system may be embodied on an integrated circuit and include one or more bit-serial tiles for performing bit-serial computations in which each bit-serial tile receives input neurons and synapses, and communicates output neurons. Also included is an activation memory for storing the neurons and a dispatcher and a reducer. The dispatcher reads neurons and synapses from memory and communicates either the neurons or the synapses bit-serially to the one or more bit-serial tiles. The other of the neurons or the synapses are communicated bit-parallelly to the one or more bit-serial tiles, or according to a further embodiment, may also be communicated bit-serially to the one or more bit-serial tiles. The reducer receives the output neurons from the one or more tiles, and communicates the output neurons to the activation memory.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: August 20, 2019
    Inventors: Patrick Judd, Jorge Albericio, Alberto Delmas Lascorz, Andreas Moshovos, Sayeh Sharify
  • Patent number: 10254349
    Abstract: The present invention relates to a method for predicting the state of health of a battery based on numerical simulation data. A method for predicting the state of health of a battery, which is performed by a battery management system, according to an embodiment of the present invention includes: a step of obtaining a verified numerical simulation database, into which solution data of the battery is extracted and stored, when a numerical analysis result is verified by an experimental result using electrical and chemical analysis of the battery; a step of counting the number of charges or discharges when a deviation between reference data read from the verified numerical simulation database and measurement data read from the battery is within a preset range and battery capacity satisfies a preset condition; and a step of predicting a state of health of the battery using the number of charges or discharges and a classifier based on a learned machine learning algorithm.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 9, 2019
    Assignee: KOREA UNIVERSITY OF TECHNOLOGY AND EDUCATION INDUSTRY-UNIVERSITY COOPERATION
    Inventors: Kwang Sun Kim, Kyung Min Jang, Kang Wo Joo
  • Patent number: 10032498
    Abstract: A memory cell unit and a recurrent neural network including memory cell units are provided. The memory cell unit includes a first time gate configured to control a cell state value of the memory cell unit, based on a phase signal of an oscillatory frequency, and a second time gate configured to control an output value of the memory cell unit, based on the phase signal.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: July 24, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., UNIVERSITAET ZUERICH
    Inventors: Daniel Neil, Shih-Chii Liu, Michael Pfeiffer
  • Patent number: 10032463
    Abstract: An automatic speech recognition (“ASR”) system produces, for particular users, customized speech recognition results by using data regarding prior interactions of the users with the system. A portion of the ASR system (e.g., a neural-network-based language model) can be trained to produce an encoded representation of a user's interactions with the system based on, e.g., transcriptions of prior utterances made by the user. This user-specific encoded representation of interaction history is then used by the language model to customize ASR processing for the user.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: July 24, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Ariya Rastrow, Nikko Ström, Spyridon Matsoukas, Markus Dreyer, Ankur Gandhe, Denis Sergeyevich Filimonov, Julian Chan, Rohit Prasad
  • Patent number: 9959498
    Abstract: A computer-implemented method that includes receiving, by a processing unit, an instruction that specifies data values for performing a tensor computation. In response to receiving the instruction, the method may include, performing, by the processing unit, the tensor computation by executing a loop nest comprising a plurality of loops, wherein a structure of the loop nest is defined based on one or more of the data values of the instruction. The tensor computation can be at least a portion of a computation of a neural network layer. The data values specified by the instruction may comprise a value that specifies a type of the neural network layer, and the structure of the loop nest can be defined at least in part by the type of the neural network layer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: May 1, 2018
    Inventors: Ravi Narayanaswami, Dong Hyuk Woo, Olivier Temam, Harshit Khaitan
  • Patent number: 9846837
    Abstract: A computer-implemented method that includes receiving, by a processing unit, an instruction that specifies data values for performing a tensor computation. In response to receiving the instruction, the method may include, performing, by the processing unit, the tensor computation by executing a loop nest comprising a plurality of loops, wherein a structure of the loop nest is defined based on one or more of the data values of the instruction. The tensor computation can be at least a portion of a computation of a neural network layer. The data values specified by the instruction may comprise a value that specifies a type of the neural network layer, and the structure of the loop nest can be defined at least in part by the type of the neural network layer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: December 19, 2017
    Assignee: Google Inc.
    Inventors: Ravi Narayanaswami, Dong Hyuk Woo, Olivier Temam, Harshit Khaitan
  • Patent number: 9836691
    Abstract: A computer-implemented method that includes receiving, by a processing unit, an instruction that specifies data values for performing a tensor computation. In response to receiving the instruction, the method may include, performing, by the processing unit, the tensor computation by executing a loop nest comprising a plurality of loops, wherein a structure of the loop nest is defined based on one or more of the data values of the instruction. The tensor computation can be at least a portion of a computation of a neural network layer. The data values specified by the instruction may comprise a value that specifies a type of the neural network layer, and the structure of the loop nest can be defined at least in part by the type of the neural network layer.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: December 5, 2017
    Assignee: Google Inc.
    Inventors: Ravi Narayanaswami, Dong Hyuk Woo, Olivier Temam, Harshit Khaitan
  • Patent number: 9659122
    Abstract: A computer-implemented method of analyzing data representing the optimization of real-world designs of physical entities according to at least one criterion. Different modifications of the design are generated by a cyclic optimization algorithm. The design data is represented by unstructured triangular surface meshes. A displacement measure representing local differences between two design modifications of the different modifications is calculated. Performance difference between the two design modifications is calculated. The performance difference is represented by at least one criterion. Sensitivity information representing correlation between the displacement measure and the performance differences is outputted.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: May 23, 2017
    Assignee: Honda Research Institute Europe GmbH
    Inventors: Lars Graning, Markus Olhofer, Bernhard Sendhoff
  • Patent number: 9424174
    Abstract: A control apparatus which controls a memory having a plurality of banks, allocates the plurality of banks to a first region and a second region, wherein data transfer is performed by interleaving access in a plurality of banks in the first region, and data transfer is performed by non-interleaving access in at least one bank in the second region. The control apparatus sets a bank in the first region and a bank in the second region independently to a low-power state.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: August 23, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koji Nishimori, Hideyuki Rengakuji
  • Patent number: 9390368
    Abstract: The present invention provides a system comprising a neurosynaptic processing device including multiple neurosynaptic core circuits for parallel processing, and a serial processing device including at least one processor core for serial processing. Each neurosynaptic core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of synapse devices. The system further comprises an interconnect circuit for coupling the neurosynaptic processing device with the serial processing device. The interconnect circuit enables the exchange of data packets between the neurosynaptic processing device and the serial processing device.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: July 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bryan L. Jackson, Dharmendra S. Modha, Norman J. Pass
  • Patent number: 9213936
    Abstract: A method of emulating the human brain with its thought and rationalization processes is presented here, as well as a method of storing human-like thought. The invention provides for inclusion of psychological profiles, experience and societal position in an electronic emulation of the human brain. This permits a realistic human-like response by that emulation to the people and the interactive environment around it.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: December 15, 2015
    Assignee: Neuric, LLC
    Inventor: Thomas A. Visel
  • Patent number: 9177388
    Abstract: A method of determining a hash code representing a portion of an image, is disclosed. A Delaunay region (e.g., 450) enclosing an image feature point (e.g., 210) representing at least the portion of the image is determined. The Delaunay region is determined from A* lattice points. A mapping transforming the Delaunay region to a predetermined canonical form is determined A point of the Delaunay region is received. The received point defines a plane containing the A* lattice points of the Delaunay region excluding the received point. A normal of the plane is determined by setting at least two co-ordinates of the normal to predetermined non-zero values, the two co-ordinates being selected according to the determined mapping. The hash code representing a portion of the image is determined according to a distance determined using the normal.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: November 3, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Alan Valev Tonisson, Barry James Drake, Scott Alexander Rudkin
  • Patent number: 9053681
    Abstract: A dynamically reconfigurable heterogeneous systolic array is configured to process a first image frame, and to generate image processing primatives from the image frame, and to store the primatives and the corresponding image frame in a memory store. A characteristic of the image frame is determined. Based on the characteristic, the array is reconfigured to process a following image frame.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: June 9, 2015
    Assignee: FotoNation Limited
    Inventors: Petronel Bigioi, Corneliu Zaharia, Peter Corcoran
  • Patent number: 8924323
    Abstract: A system and method for managing, tracking and recording one or more biological process inputs, outputs and their derived forms is provided. The inputs pertaining to the biological process inputs, outputs and their derived forms are received and processed. The inputs include information related to the biological processes and the biological process inputs, outputs and their derived forms. The inputs further include information related to modifications in the biological process inputs, outputs and their derived forms. The inputs also include outputs of the biological processes. The inputs are processed by modifying the received inputs into a predefined format. Thereafter, the received inputs and processed inputs are stored. The stored inputs are accessed for managing, tracking and recording the biological processes, biological process inputs, outputs and their derived forms.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 30, 2014
    Assignee: Infosys Limited
    Inventors: Ajay Shah, Srinivas Bolisetty, Xian-Wei Meng, Ali G. Ozkabak, Anirban Ghosh, Kirti Jindal, Krutin Boloor, Ramesh Balakrishnan, Manas Ajith Khare, Parag Sangoi
  • Publication number: 20140337263
    Abstract: Disclosed is an improved approach to implement artificial neural networks. According to some approaches, an advanced neural network is implemented using an internet-of-things methodology, in which a large number of ordinary items having RFID technology are utilized as the vast infrastructure of a neural network.
    Type: Application
    Filed: May 6, 2014
    Publication date: November 13, 2014
    Applicant: IOTELLIGENT TECHNOLOGY LTD INC
    Inventor: Theodore ZHU
  • Patent number: 8195648
    Abstract: Methods, systems, and computer-readable media are disclosed for partitioned query execution in event processing systems. A particular method includes receiving a plurality of events via an input stream. The plurality of events is partitioned into one or more groups, and a query application module is instantiated for each of the one or more groups based on a compiled query application plan. Each particular query application module for a particular group is configured to apply a query to events of the particular group to generate partial results. The method includes merging the partial results of each of the query application modules to generate merged output results and providing the output results to an output stream.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: June 5, 2012
    Assignee: Microsoft Corporation
    Inventors: Peter Zabback, Tihomir Tarnavski, Beysim Sezgin, Tomer Verona
  • Patent number: 8126828
    Abstract: A special purpose processor (SPP) for implementing a synthetic neural model of the biological anatomy of the human brain to control a brain-based device (BBD) that is movable in a real-world environment, including neural processing units (NPUs), each having a programmed processor and a local memory that stores data records of neural elements, a system memory for storing data about all the NPUs, and a finite state machine and a system bus for transferring data between the NPUs and system memory.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: February 28, 2012
    Assignee: Neuroscience Research Foundation, Inc.
    Inventors: James A. Snook, Donald B. Hutson, Jeffrey L. Krichmar
  • Patent number: 7941392
    Abstract: According to one aspect of one or more embodiments of the present invention, a system comprises: an HTM network executable at least in part on multiple node processing units (NPUs). In one embodiment the NPUs include one or more nodes, each of which can be executed by its NPU. In one embodiment, the present invention includes a technique for coordinating and scheduling HTM computation across one or more CPUs which (1) enables concurrent computation (2) does not require a central point of control (e.g. a controller entity that “orchestrates” the computation), (3) does not require global synchronization, (4) in some embodiments ensures that the same results are achieved whether the nodes are executed in parallel or serially.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: May 10, 2011
    Assignee: Numenta, Inc.
    Inventor: William Cooper Saphir
  • Patent number: 7925492
    Abstract: A method for emulating human cognition in electronic form is disclosed. Information is received in the form of a textual or voice input in a natural language. This is parsed into pre-determined phrases based on a stored set of language rules for the natural language. Then, the parsed phrases are determined as to whether they define aspects of an environment and, if so, then creating weighting factors to the natural language that are adaptive, the created weighting factors operable to create a weighted decision based upon the natural language. Then it is determined if the parsed phrases constitute a query and, if so, then using the weighted factors to make a decision to the query.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: April 12, 2011
    Assignee: Neuric Technologies, L.L.C.
    Inventor: Thomas A. Visel
  • Patent number: 7637735
    Abstract: In a procedure for regulating a combustion process in an installation while air is being supplied, material is converted by the combustion process, with at least one flame being formed, and the state variables (s(t)) describing the state of the system in the installation are determined using at least one observation device that images the flame, as well as other sensors, and are evaluated in a computer, whereupon any appropriate actions (ai) that may be needed are selected in order to control adjusting devices for the supply of material and/or air, wherein during setpoint regulation to achieve setpoints (s0) of the state variables and/or stability of the combustion process a changeover is occasionally made from setpoint control to disturbance control.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: December 29, 2009
    Assignee: Powitec Intelligent Technologies GmbH
    Inventor: Franz Wintrich
  • Patent number: 7620819
    Abstract: We develop a system consisting of a neural architecture resulting in classifying regions corresponding to users' keystroke patterns. We extend the adaptation properties to classification phase resulting in learning of changes over time. Classification results on login attempts of 43 users (216 valid, 657 impersonation samples) show considerable improvements over existing methods.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: November 17, 2009
    Assignees: The Penn State Research Foundation, Louisiana Tech University Foundation, Inc.
    Inventors: Vir V. Phoha, Sunil Babu, Asok Ray, Shashi P. Phoba
  • Patent number: 7558740
    Abstract: A scheduling system and method for moving plural objects through a multipath system described as a freight railway scheduling system. The scheduling system utilizes a cost reactive resource scheduler to minimize resource exception while at the same time minimizing the global costs associated with the solution. The achievable movement plan can be used to assist in the control of, or to automatically control, the movement of trains through the system.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: July 7, 2009
    Assignee: Harris Corporation
    Inventors: William L. Matheson, Paul M. Julich, Michael S. Crone, Douglas A. Thomae, Thu V. Vu, M. Scott Wills
  • Patent number: 7539624
    Abstract: A scheduling system and method for moving plural objects through a multipath system described as a freight railway scheduling system. The scheduling system utilizes a cost reactive resource scheduler to minimize resource exception while at the same time minimizing the global costs associated with the solution. The achievable movement plan can be used to assist in the control of, or to automatically control, the movement of trains through the system.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: May 26, 2009
    Assignee: Harris Corporation
    Inventors: William L. Matheson, Paul M. Julich, Michael S. Crone, Douglas A. Thomae, Thu V. Vu, M. Scott Wills
  • Publication number: 20080258773
    Abstract: A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive connects utilized to create A plasticity mechanism is also provided, which is based on a plasticity rule for creating stable connections from the plurality of self-assembling chains of nanoparticles for use with the universal, reconfigurable logic gate. The plasticity mechanism can be based, for example, on a 2-dimensional binary input data stream, depending upon design considerations. A circuit is also associated with the plurality of self-assembling chains of nanoparticles, wherein the circuit provides a logic bypass that implements a flip-cycle for second-level logic. Additionally, an extractor logic gate is associated with the plurality of self-assembling chains of nanoparticles, wherein the extractor logic gate provides logic functionalities.
    Type: Application
    Filed: June 22, 2008
    Publication date: October 23, 2008
    Inventor: Alex Nugent
  • Publication number: 20080243741
    Abstract: A method for defining a network of nodes is provided, each representing a unique concept, and making connections between individual concepts through unique relationships to other concepts. Each of the nodes is operable to store a unique identifier in the network and information regarding the concept in addition to the unique relationships.
    Type: Application
    Filed: June 10, 2008
    Publication date: October 2, 2008
    Applicant: NEURIC TECHNOLOGIES, LLC
    Inventors: THOMAS A. VISEL, LUKAS K. WOMACK, GENE P. HAMILTON
  • Patent number: 7430546
    Abstract: An information processing system having neuron-like signal processors that are interconnected by synapse-like processing junctions that simulates and extends capabilities of biological neural networks. The information processing systems uses integrate-and-fire neurons and Temporally Asymmetric Hebbian learning (spike timing-dependent learning) to adapt the synaptic strengths. The synaptic strengths of each neuron are guaranteed to become optimal during the course of learning either for estimating the parameters of a dynamic system (system identification) or for computing the first principal component. This neural network is well-suited for hardware implementations, since the learning rule for the synaptic strengths only requires computing either spike-time differences or correlations. Such hardware implementation may be used for predicting and recognizing audiovisual information or for improving cortical processing by a prosthetic device.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: September 30, 2008
    Inventor: Roland Erwin Suri
  • Patent number: 7389208
    Abstract: A system and method responsive to input stimuli is provided by incorporating a computer software program, hardware processing engine, or a specialized ASIC chip processor apparatus to capture concurrent inputs that are responsive to training stimulation, store a model representing a synthesis of the captured inputs, and use the stored model to generate outputs in response to real-world stimulation. Human user forced-choice approval/disapproval generated descriptions and decisions may be dynamically mapped with conventionally presented information and sensor and control data. The model mapping is stored into and out of a conventional mass storage device, such as is used in a relational database for use in generating a response to the stimuli.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: June 17, 2008
    Assignee: Accord Solutions, Inc.
    Inventor: James C. Solinsky
  • Patent number: 7343314
    Abstract: A scheduling system and method for moving plural objects through a multipath system described as a freight railway scheduling system. The scheduling system utilizes a cost reactive resource scheduler to minimize resource exception while at the same time minimizing the global costs associated with the solution. The achievable movement plan can be used to assist in the control of, or to automatically control, the movement of trains through the system.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: March 11, 2008
    Assignee: Harris Corporation
    Inventors: William L. Matheson, Paul M. Julich, Michael S. Crone, Douglas A. Thomae, Thu V. Vu, M. Scott Wills
  • Patent number: 7340328
    Abstract: A scheduling system and method for moving plural objects through a multipath system described as a freight railway scheduling system. The scheduling system utilizes a cost reactive resource scheduler to minimize resource exception while at the same time minimizing the global costs associated with the solution. The achievable movement plan can be used to assist in the control of, or to automatically control, the movement of trains through the system.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: March 4, 2008
    Assignee: Harris Corporation
    Inventors: William L. Matheson, Paul M. Julich, Michael S. Crone, Douglas A. Thomae, Thu V. Vu, M. Scott Wills
  • Patent number: 7272585
    Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: September 18, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Osamu Nomura, Takashi Morie, Teppei Nakano
  • Patent number: 7222002
    Abstract: The present invention provides an aircraft engine vibration system that provides information about engine health. Embodiments of the present invention monitor for excessive vibration, monitor for bird strike, monitor for ice build up on the fan section, and monitor general engine health. An embodiment of the present invention utilizes neural network architecture for the detection of excessive vibration and ice detection build-up on the fan section of a turbo-fan engine and to monitor engine health through the high-pressure turbine section of the engine.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: May 22, 2007
    Assignee: The Boeing Company
    Inventor: Scott T. Maine
  • Patent number: 7143072
    Abstract: A neural network having layers of neurons divided into sublayers of neurons. The values of target neurons in one layer are calculated from sublayers of source neurons in a second underlying layer. It is therefore always possible to use for this calculation the same group of weights to be multiplied by respective source neurons related thereto and situated in the underlying layer of the neural network.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: November 28, 2006
    Assignee: CSEM Centre Suisse d′Electronique et de Microtechnique SA
    Inventors: Jean-Marc Masgonty, Philippe Vuilleumier, Peter Masa, Christian Piguet
  • Patent number: 7053895
    Abstract: An image processing apparatus which processes input image data of Y lines, each consisting of X pixels, using an SIMD processor, comprises a calculation unit including N (X>N>1, Y>N>1) elemental processors capable of parallel-operating; an input unit for dividing and inputting the image data of one line with respect to every N pixels; a storage for storing the input N-pixel image data of the N lines; and an image processor for supplying, from among the stored N-pixel image data of the N lines, the N image data respectively to the N elemental processors, and causing the respective elemental processors to perform the same-kind calculations in parallel. Thus, the image processing apparatus for performing an image process such as error diffusion by using the SIMD processor without using any auxiliary processor for a sequential process can be provided.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: May 30, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shigeo Yamagata, Hiroshi Tanioka, Manabu Takebayashi
  • Patent number: 6947916
    Abstract: A computing machine capable of performing multiple operations using a universal computing unit is provided. The universal computing unit maps an input signal to an output signal. The mapping is initiated using an instruction that includes the input signal, a weight matrix, and an activation function. Using the instruction, the universal computing unit may perform multiple operations using the same hardware configuration. The computation that is performed by the universal computing unit is determined by the weight matrix and activation function used. Accordingly, the universal computing unit does not require any programming to perform a type of computing operation because the type of operation is determined by the parameters of the instruction, specifically, the weight matrix and the activation function.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: September 20, 2005
    Assignee: Quicksilver Technology, Inc.
    Inventors: Fa-Long Luo, Bohumir Uvacek
  • Patent number: 6842745
    Abstract: A chaotic signal generator includes a set of elements connected together for generating chaotic signals. The connection scheme may correspond to the circuit generally referred to as Chua's circuit, particularly when implemented as a cellular neural network. Interposed in the connection scheme is at least one switch, such as a MOS transistor. Opening and closing of the switch causes variation in the chaotic dynamics of the generated signals. A command signal applied to the switch may correspond to a modulating signal for transmission on a channel, such as a high noise channel. The modulating signal may be a binary signal, and the command signal may be a switching signal having a frequency that increases or decreases depending on the logic level of the binary signal.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: January 11, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luigi Occhipinti, Luigi Fortuna, Alessandro Rizzo, Mattia Frasca
  • Patent number: 6836767
    Abstract: In a first aspect, a pipelined hardware implementation of a neural network circuit includes an input stage, two or more processing stages and an output stage. Each processing stage includes one or more processing units. Each processing unit includes storage for weighted values, a plurality of multipliers for multiplying input values by weighted values, an adder for adding products outputted from product multipliers, a function circuit for applying a non-linear function to the sum outputted by the adder, and a register for storing the output of the function circuit.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: December 28, 2004
    Assignee: International Business Machines Corporation
    Inventor: Chad B. McBride
  • Patent number: 6714924
    Abstract: A method and apparatus for color matching are provided, in which paint recipe neural networks are utilized. The color of a standard is expressed as color values. The neural network includes an input layer having nodes for receiving input data related to paint bases. Weighted connections connect to the nodes of the input layer and have coefficients for weighting the input data. An output layer having nodes are either directly or indirectly connected to the weighted connections and generates output data related to color values. The data to the input layer and the data from the output layer are interrelated through the neural network's nonlinear relationship. The paint color matching neural network can be used for, but not limited to, color formula correction, matching from scratch, effect pigment identification, selection of targets for color tools, searching existing formulas for the closest match, identification of formula mistakes, development of color tolerances and enhancing conversion routines.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: March 30, 2004
    Assignee: BASF Corporation
    Inventor: Craig J. McClanahan