Digital Differential Analyzer Patents (Class 708/102)
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Patent number: 10608660Abstract: Various examples of devices, methods and systems related to pulse based arithmetic units. In one example, a pulse domain device includes an augend area calculator to provide an augend area output for an augend pulse train; an addend area calculator to provide an addend area output for an addend pulse train; a resultant sum area (RSA) decoder to provide a RSA output using the augend and addend area outputs; and a pulse timing calculator to provide RSA output pulse timing. In another example, a pulse domain device includes a multiplicand area calculator to provide an multiplicand area output for a multiplicand pulse train; a multiplier area calculator to provide a multiplier area output for a multiplier pulse train; a resultant product area (RPA) decoder to provide a RPA output using the multiplicand and multiplier area outputs; and a pulse timing calculator to provide RPA output pulse timing.Type: GrantFiled: August 24, 2016Date of Patent: March 31, 2020Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.Inventors: Gabriel Nallathambi, Jose C. Principe
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Patent number: 9471303Abstract: A framework for developing web and hybrid applications (Apps) of a project is described herein. In accordance with one aspect, a façade framework is provided. The façade framework includes a web library having a set of application program interfaces (APIs) of hybrid features of a mobile device, a hybrid library having a set of APIs of hybrid features of a mobile device, and a unified interface for interfacing with the web and hybrid libraries. Base code of a base project may be provided using an application development system. The base code may include common code to web assets common to the web and hybrid Apps of the project. The base code may be extended using the application development system to produce an extended code of the project, where the extended code includes hybrid features used by the project. The unified interface provides APIs from the web and hybrid libraries used by the project.Type: GrantFiled: February 4, 2015Date of Patent: October 18, 2016Assignee: SAP SEInventors: Yiquan Zhou, Ludo Franciscus Maria Noens, Qiushi Wang
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Publication number: 20140201251Abstract: A computer and computer program product for managing analysis of sentiment is disclosed. A computer retrieves data used to perform the analysis of sentiment. The computer analyzes the data and the analysis of sentiment to determine if a gap exists requiring further processing to improve the analysis of sentiment. Responsive to a determination that the gap exists requiring further processing to improve the analysis of sentiment, the computer generates a task to address the gap. The computer then uses crowdsourcing to submit the generated task for processing.Type: ApplicationFiled: August 17, 2013Publication date: July 17, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sheng Hua Bao, Yu Deng, Hong L. Guo, Qi Hu, Jim A. Laredo, Roman Vaculin, Maja Vukovic
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Publication number: 20130173675Abstract: Performing a global barrier operation in a parallel computer that includes compute nodes coupled for data communications, where each compute node executes tasks, with one task on each compute node designated as a master task, including: for each task on each compute node until all master tasks have joined a global barrier: determining whether the task is a master task; if the task is not a master task, joining a single local barrier; if the task is a master task, joining the global barrier and the single local barrier only after all other tasks on the compute node have joined the single local barrier.Type: ApplicationFiled: November 21, 2012Publication date: July 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
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Patent number: 8200731Abstract: A device for and method of determining a coherence measurement for a signal that includes a digitizer for digitizing the signal, a transformer connected to the digitizer, a first squarer connected to the transformer, a second squarer connected to the digitizer, an adder connected to the first squarer and the second squarer, a subtractor connected to the first squarer and the second squarer, a standard-deviation function block connected to the subtractor, a mean generator connected to the adder, a first multiplier connected to the standard-deviation function block, and a divider connected to the output of the mean generator and the first multiplier.Type: GrantFiled: November 20, 2008Date of Patent: June 12, 2012Assignee: The United States of America as represented by the Director, National Security AgencyInventor: Adolf Cusmariu
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Patent number: 8166518Abstract: A computer implemented method provides remote access to a plurality of sessions at a computer. The method includes initiating a master process in a context independent from the sessions, establishing a first slave process in a context of a first session, and maintaining communication between the master process and the first slave process. The master process provides access to the computer's display while the display is under control of the first session, detects a second session, having a respective second slave process, communicates with the second slave process, and provides access to the computer's display while the display is under control of the second user session.Type: GrantFiled: November 15, 2006Date of Patent: April 24, 2012Assignee: Netopia, Inc.Inventors: Michael Byron Price, Marc A. Epard, Donald W. Griffin
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Publication number: 20090234898Abstract: The present invention relates to a method of generating a pulse for a digital differential analyzer. The digital differential analyzer includes a counter, a shift register and an adder with a comparator. The beginning number P of the shift register, the beginning number L of the comparator, and the beginning number Q of the counter, are all set, according to the formula Q=int(0.5L+0.5). A pulse command is inputted into the shift register. The number of the shift register and the number of the counter are added. The sum of the addition step is compared to the number of the comparator. If the sum is greater than or equal to the number of the comparator, the digital differential analyzer generates a pulse.Type: ApplicationFiled: September 5, 2008Publication date: September 17, 2009Applicant: FOXNUM TECHNOLOGY CO., LTD.Inventors: RONG-HWANG HORNG, WEI-DER TANG, YAW-SHEN LAI, CHAU-LIN CHANG, TSANN-HUEI CHANG
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Patent number: 7532751Abstract: An apparatus and a computer program product render a multi-dimensional digital image using raytracing in a multi-dimensional space. A multi-dimensional digital differential analyzer (DDA) is included. Variables of said multi-dimensional digital differential analyzer (DDA) are set up using multiplications only. The digital image is rendered based upon the variables of the multi-dimensional digital differential analyzer (DDA). Each axis of the multi-dimensional space includes a numerator which holds the progress within a cell along that axis and a denominator which describes a size condition causing said DDA to step to a next cell.Type: GrantFiled: March 6, 2008Date of Patent: May 12, 2009Assignee: International Business Machines CorporationInventor: Martijn Boekhorst
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Publication number: 20090063597Abstract: A second derivative of a second-order differential equation is calculated at a reference variable value. The second derivative is multiplied by an analytical small variable value, the first derivative at the reference variable value is added, and a result is output as a first derivative after an increment of the analytical small variable value. The first derivative after an increment of the analytical small variable value is multiplied by the analytical small variable value, a physical value at the reference variable value is added, and a result is output as a physical value after an increment of the analytical small variable value.Type: ApplicationFiled: March 22, 2006Publication date: March 5, 2009Inventors: Hiroaki Sono, Nobuhiro Yamada, Haruya Kitagawa, Tsuyoshi Nomura
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Patent number: 7403989Abstract: Systems and techniques to improve workflow using worksets. In general, in one implementation, the technique includes: providing a data object directed to a particular work role. The data object includes task data for performing the work role, portal environment data for presenting information to a user via a portal, and meta-data descriptive of the work role.Type: GrantFiled: November 27, 2002Date of Patent: July 22, 2008Assignee: SAP AGInventors: Joerg Beringer, Peer Hilgers, Leif Jensen-Pistorius, Klaus Wriessnegger
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Patent number: 7366345Abstract: A method, an apparatus, and a computer program product render a multi-dimensional digital image using raytracing in a multi-dimensional space. Variables of a multi-dimensional digital differential analyzer (DDA) are set up using multiplications only. For each axis of the multi-dimensional space, a numerator holds the progress within a cell along that axis and a denominator describes a size condition causing the DDA to step to a next cell. For a vector, a denominator of the vector for an axis is equal to a delta for a vector component, excluding the component of said axis, for two dimensions; and a product of deltas for all vector components, excluding the component of said axis, for greater than two dimensions.Type: GrantFiled: February 13, 2004Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventor: Martijn Boekhorst
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Patent number: 7260658Abstract: Techniques for verifying input/output (I/O) command data are provided. Information about the contents of the data are specified in the I/O command. After an application issues the I/O command, a subsequent component, such as a controller, uses the information to verify the contents of the data before the I/O command is performed.Type: GrantFiled: April 29, 2003Date of Patent: August 21, 2007Assignee: Oracle International CorporationInventors: William H. Bridge, Jr., James Williams
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Patent number: 6947056Abstract: An apparatus generally having a register, an adder circuit and a mask circuit is disclosed. The register may be configured to replace a current value with a new value in response to a clock value. The adder circuit may be configured to generate the new value by adding the current value to a delta value. The mask circuit may be configured to mask at least one value among the delta value, the new value and the clock value in response to a mask value having a plurality of bits.Type: GrantFiled: March 25, 2003Date of Patent: September 20, 2005Assignee: LSI Logic CorporationInventor: Mark J. Kwong
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Patent number: 6510442Abstract: A digital differential analyzer (DDA) is described that avoids using comparisons, and instead uses shifts, multiplies, and adds. Shifts are less costly to use in terms of processor time, and already exist in the hardware of a computer graphics system. The DDA provides improved linear interpolation procedures for use in computer graphics applications such as line drawing, computing polygon edges, texture mapping, and image scaling. The shifts are used to generate an “imposter” DDA having a larger denominator that substantially exactly simulates a DDA for a finite number of terms. The imposter DDA is a fixed point simulator of the original DDA that provides error-free approximations.Type: GrantFiled: January 12, 2000Date of Patent: January 21, 2003Assignee: Microsoft CorporationInventor: Kirk Olynyk
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Publication number: 20020124030Abstract: The invention relates to methods and apparatus that allow a comparison of phase between a clock signal and a serial bitstream. A phase detector integrates a portion of a transition between adjacent or consecutive bits of the serial bitstream in a relatively fixed window. Advantageously, the relatively fixed window permits operation at relatively high frequencies such as at OC-192 rates of SONET. The integration result contains an amount of time within the window spent in one logic state versus the other. The integration results are held until the logic levels of the integrated bits are ascertained. An indication of a logic level transition is used to relate the integration result to the timing of the transition within the integration window. Multiple bit transitions can be integrated, correlated to timing information, summed, and provided as an input to, for example, a voltage controlled oscillator in a phase-locked loop.Type: ApplicationFiled: June 4, 2001Publication date: September 5, 2002Inventors: Syed K. Enam, Masoud Djafari, R. Kent Smythe