Electrical Digital Calculating Computer Patents (Class 708/100)
  • Patent number: 10977000
    Abstract: Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 13, 2021
    Assignee: Imagination Technologies Limited
    Inventor: Theo Alan Drane
  • Patent number: 10887436
    Abstract: A camera assembly may include a fixed holder, a support means including a first magnetic structure and configured to move relative to the fixed holder, a guiding rail arranged on the fixed holder, a sliding block arranged on the support means and configured to slide along the guiding rail to guide movement of the support means, a camera module arranged on the support means and configured to move between a first position at which the camera module extends out of the fixed holder and a second position at which the camera module retracts into the fixed holder with the movement of the support means, and a second magnetic structure arranged on the fixed holder and configured to generate repulsive force and attractive force to the first magnetic structure to drive the support means to move, such that the camera module moves between the first position and the second position.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 5, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Zanjian Zeng
  • Patent number: 10831543
    Abstract: Applications on different processing elements have different characteristics such as latency versus bandwidth sensitivity, memory level parallelism, different memory access patterns and the like. Interference between applications due to contention at different sources leads to different effects on performance and is quantified. A method for contention-aware resource provisioning in heterogeneous processors includes receiving stand-alone performance statistics for each processing element for a given application. Multi-core performance slowdown can be computed from the received stand-alone performance statistics. When a request to provision an application on the heterogeneous processors is received, application performance requirements of the application can be determined and a bandwidth for the application can be provisioned based on the application performance requirements and the computed multi-core performance slowdown parameter.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nandhini Chandramoorthy, Karthik V. Swaminathan, Ramon Bertran Monfort, Alper Buyuktosunoglu, Pradip Bose
  • Patent number: 10831495
    Abstract: A method for parallelization of a numeric optimizer includes detecting an initialization of a numeric optimization process of a given function. The method computes a vector-distance between an input vector and a first neighbor vector of a set of neighbor vectors. The method predicts, using the computed vector-distance, a subset of the set of neighbor vectors. The method pre-computes, in a parallel processing system, a set of evaluation values in parallel, each evaluation value corresponding to one of the subset of the set of neighbor vectors. The method detects a computation request from the numeric optimization process, the computation request involving at least one of the set of evaluation values. The method supplies, in response to receiving the computation request, and without performing a computation of the computation request, a parallelly pre-computed evaluation value from the set of evaluation values to the numeric optimization process.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Liu, Richard Chen, Shaohan Hu, Marco Pistoia, John A. Gunnels, Antonio Mezzacapo
  • Patent number: 10819483
    Abstract: Demodulation reference signals (e.g., DM-RSs) are transmitted for a 5G, or other next generation network using an adaptive DM-RS structure. Demodulation reference signal data representative of demodulation reference signals employable to perform channel estimation of data channels is generated the demodulation reference signal data is transmitted, via a channel other than the data channels, to be used for the channel estimation. The adaptive DM-RS structure can be based on a modulation scheme used for data transmission. An orthogonal variable spreading factor code tree can be used when choosing an orthogonal cover code, and resource mapping for DM-RSs can be made unequal based on analysis of antenna ports. Further, a DM-RS with high resource density can be used to compensate for phase noise.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: October 27, 2020
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: SaiRamesh Nammi, Arunabha Ghosh, Salam Akoum, Xiaoyi Wang
  • Patent number: 10713055
    Abstract: A method for parallelization of a numeric optimizer includes detecting an initialization of a numeric optimization process of a given function. The method computes a vector-distance between an input vector and a first neighbor vector of a set of neighbor vectors. The method predicts, using the computed vector-distance, a subset of the set of neighbor vectors. The method pre-computes, in a parallel processing system, a set of evaluation values in parallel, each evaluation value corresponding to one of the subset of the set of neighbor vectors. The method detects a computation request from the numeric optimization process, the computation request involving at least one of the set of evaluation values. The method supplies, in response to receiving the computation request, and without performing a computation of the computation request, a parallelly pre-computed evaluation value from the set of evaluation values to the numeric optimization process.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Liu, Richard Chen, Shaohan Hu, Marco Pistoia, John A. Gunnels, Antonio Mezzacapo
  • Patent number: 10545757
    Abstract: Systems, apparatuses, and methods for performing an instruction in a computer processor are described. For example, an instruction having a source and destination operand is executed to determine whether all data elements of the source operand are equal and an indication of the determination is stored in the destination operand.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Matt Walsh, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Bret Toll
  • Patent number: 10448275
    Abstract: A network node and a method performed thereby for supporting VoIP service of a wireless device are provided. The network node is operable in a wireless communication network, and the method comprises, when a channel quality of a channel between the wireless device and the network node falls below a predetermined threshold: determining (110) QoS requirements with regard to GBR for services which the wireless device is currently using; determining (120) an achievable bitrate using TTI bundling; and determining (150) to enable TTI bundling of the wireless device based on the determined aggregated GBR requirement and the determined achievable bitrate.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 15, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Carola Faronius, Anders Christensson, David Sandberg
  • Patent number: 10430162
    Abstract: In this application, example methods for performing quantum Montgomery arithmetic are disclosed. Additionally, circuit implementations are disclosed for reversible modular arithmetic, including modular addition, multiplication and inversion, as well as reversible elliptic curve point addition. This application also shows that elliptic curve discrete logarithms on an elliptic curve defined over an n-bit prime field can be computed on a quantum computer with at most 9n+2?log2(n)?+10 qubits using a quantum circuit of at most 512n3 log2(n)+3572n3 Toffoli gates.
    Type: Grant
    Filed: August 5, 2017
    Date of Patent: October 1, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Martin Roetteler, Kristin Lauter, Krysta Svore
  • Patent number: 10090980
    Abstract: Demodulation reference signals (e.g., DM-RSs) are transmitted for a 5G, or other next generation network using an adaptive DM-RS structure. Demodulation reference signal data representative of demodulation reference signals employable to perform channel estimation of data channels is generated the demodulation reference signal data is transmitted, via a channel other than the data channels, to be used for the channel estimation. The adaptive DM-RS structure can be based on a modulation scheme used for data transmission. An orthogonal variable spreading factor code tree can be used when choosing an orthogonal cover code, and resource mapping for DM-RSs can be made unequal based on analysis of antenna ports. Further, a DM-RS with high resource density can be used to compensate for phase noise.
    Type: Grant
    Filed: January 8, 2017
    Date of Patent: October 2, 2018
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: SaiRamesh Nammi, Arunabha Ghosh, Salam Akoum, Xiaoyi Wang
  • Patent number: 9875049
    Abstract: A memory system and method for reducing peak current consumption. In one embodiment, a method is provided that is performed in a memory system comprising a memory with a plurality of blocks, wherein each block has a peak current consumption. In this method, a plurality of metablocks is created, wherein each metablock is created by grouping together blocks with complementary peak current consumption. Next, the metablocks are programmed. Because each of the metablocks has blocks with complementary peak current consumption, each of the metablocks has similar peak current consumption when programmed. Other embodiments are provided.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: January 23, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Eran Erez, Jonathan H. Hsu, Ken Q. Nguyen
  • Patent number: 9753851
    Abstract: A computer system to schedule a garbage collection process within a computing environment comprises a memory unit and a hardware computer processor. The memory unit includes a load-monitored region configured to undergo a garbage collection process. The hardware computer processor is configured to perform operations comprising invoking a handler to obtain processing control in response to a request from an application to load a pointer that points to an object located within the load-monitored region, and determining by the handler a priority of the application, and performing a garbage selection process according to one mode among a plurality of different modes based on the priority.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles R. Frazier, Michael Karl Gschwind
  • Patent number: 9658790
    Abstract: A memory system and method for power-based operation scheduling are provided. In one embodiment, a memory system begins to perform a plurality of operations in an order in which they are stored in a queue. Before performing a next operation in the queue, the memory system determines whether the power consumed by performing the next operation would exceed a maximum power threshold. In response to determining that the power consumed would exceed the maximum power threshold, the memory system selects an operation out of order from the queue to perform instead, so the maximum power threshold would not be exceeded. Other embodiments are provided.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: May 23, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Eran Erez, Alex Mostovoy
  • Patent number: 9443240
    Abstract: A display enabled RFID tag (DERT) receives transaction details from the reader. DERT verifies that the details match their counterparts in the reader public key certificate. The process is aborted in case of a mismatch. DERT extracts and displays user-verifiable data. It then enters a countdown stage that lasts for a predetermined duration. A user observes the transaction information and, if the transaction amount and other details are deemed correct, presses an accept button provided on the DERT before the timer runs out. DERT signs the time-stamped transaction statement and sends it to the reader. This signed statement is then sent to the payment gateway and eventually to the financial institution that issued the payment DERT.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: September 13, 2016
    Assignee: The Regents of the University of California
    Inventors: Gene Tsudik, Ersin Uzun
  • Patent number: 9437156
    Abstract: An electronic apparatus and a method for switching a display mode are provided. The method includes: turning on the electronic apparatus to enter a full-screen display mode; switching the full-screen display mode to a block display mode when a mode-switching signal is triggered; and enabling a corresponding operation interface in the block display mode according to an execution state of an operation system of the electronic apparatus in the full-screen display mode and displaying the operation interface in the designated block of the display unit.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: September 6, 2016
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Cheng-Yi Ko, Pie-Jen Lin, Yung-Hsiang Chen, Hsin Lu, Chuan-Hao Wen, Chia-An Chen, Hong-Tien Wang
  • Patent number: 9411590
    Abstract: An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a call branch instruction. The branch counter is incremented by one each time a call branch instruction is decoded and an address is pushed onto the link register stack. In response to decoding a return branch instruction and provided the branch counter is not zero, a target address for the decoded return branch instruction is popped off the link register stack, the branch counter is decremented, and there is no need to check the target address for correctness.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 9, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Rodney Wayne Smith, Jeffery M. Schottmiller, Michael Scott McIlvaine, Brian Michael Stempel, Melinda J. Brown, Daren Eugene Streett
  • Patent number: 9356766
    Abstract: The current invention provides simplifications to the user equipment (UE) radio front end module for the cellular handset or dongle through modification of the existing 3GPP specifications for LTE and WCDMA/HSPA+ in order to support half duplex (HD) operation. The option to support HD operation is provided without mandating upgrades to all existing base stations that have already been deployed. The instant invention further prevents HD UEs from attaching to any base stations which do not support HD operations. The instant invention further provides inter-frequency cell search periods for enabling HD UEs to communicate with any base stations/cells supporting the HD operations. The instant invention further enables the HSPA+ system to support the HD-FDD mode.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: May 31, 2016
    Assignees: MSTAR SEMICONDUCTOR, INC. (CAYMAN ISLANDS), MSTAR SOFTWARE R&D (SHENZHEN) LTD., MSTAR SEMICONDUCTOR, INC.
    Inventors: Francesc Boixadera, Cyril Valadon
  • Patent number: 9047050
    Abstract: A modular system of devices, in which a (master) device can be combined with one or more of the other (slave) devices in the system to form a functional electronic device (e.g., handheld cellular phone, tablet computing device), having different functionalities and features in different form factors across various platforms. The master device provides control and/or stored data to operate the slave devices, to reduce redundancy between devices of various form factors and/or platforms, in a manner that provides additional or different functions and features in an optimized and/or enhanced manner as the form factor and/or platform changes from one to another. The master device is not functional independent without attachment to a slave device. The master device requires at least a peripheral component (e.g., a display module) provided by the slave device to become an overall functional unit.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: June 2, 2015
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: John Medica, Leonard Tsai, Shikuan Chen
  • Patent number: 8879663
    Abstract: Adaptive filtering is used to substantially cancel distortion in radio frequency (RF) signals. Such adaptive filtering can be used in an RF transmitting module to pre-compensate an RF signal with compensation (inverse) distortion to cancel inherent transmission path distortion from the RF signal. Adaptive filtering can also be used in a multi-carrier RF receiving module to cancel from a given carrier signal distortion due to cross talk from adjacent carrier signals. Adaptive filtering in an RF transceiver can be used to cancel from a received RF signal distortion arising from leakage of a transmit signal into the receive path.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: November 4, 2014
    Assignee: L-3 Communications Corp.
    Inventors: Osama S. Haddadin, Roy E. Prymek, William K. McIntire
  • Publication number: 20140280409
    Abstract: A device for temporarily storing data output from a register or data obtained by processing the output data, a processing method therefor, a program, and the like is provided. A circuit (hereinafter, referred to as a selective memory cell) in which a plurality of switches and a signal storing circuit are connected is provided in a data processing device. The selective memory cell can selectively store necessary data. A result of a frequently performed process is stored in the selective memory cell. A process whose result is stored can be performed by only outputting the stored data instead of performing the whole process; thus, input data does not need to be transferred, which can result in a reduction in processing time.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 18, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kazuaki Ohshima
  • Patent number: 8775813
    Abstract: In a method of generating a digital signature of a message m, a signature component s of the digital signature is calculated by first masking the long-term private key d using a single additive operation to combine the key d with a first value. The masked value is then multiplied by a second value to obtain component s. The first value is calculated using the message m and another component of the digital signature, and the second value is derived using the inverse of a component of the first value. In this way, the signature component s is generated using a method that counters the effectiveness of side channel attacks, such as differential side channel analysis, by avoiding a direct multiplication using long-term private key d.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: July 8, 2014
    Assignee: Certicom Corp.
    Inventor: Daniel Richard L. Brown
  • Patent number: 8767955
    Abstract: A method for protecting a calculation, by an electronic circuit, of a modular exponentiation of a digital quantity, wherein: a first variable is initialized with a random quantity; at least one second variable is initialized with a value which is a function of the digital quantity; at least for a bit at 1 of an exponent of the modular exponentiation, the first variable is updated by: a) the quotient of its content and a power of the random quantity; and b) the product of its content by that of the second variable; and once all the exponent bits have been processed, the content of the first variable is divided by the random quantity to provide the result of the modular exponentiation.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Patent number: 8700874
    Abstract: A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: April 15, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventors: Edmund G. Chen, Brian Alleyne, Robert Hathaway, Ranjit J. Rozario, Todd D. Basso
  • Publication number: 20140075410
    Abstract: In a method to help a user determine a formula, (e.g., a fact, rule, or principle expressed in scientific, mathematical, technical, etc. symbols), a user may input an indication of the formula in an imprecise syntax. The inputted indication may be in ASCII text, for example, and may include technical shorthand, technical abbreviations, pseudocode, etc. In response, one or more formulas corresponding to the user's input are determined. Optionally, other outputs related to the determined formula (s) may be generated. In one implementation, software programming code corresponding to the formula is generated. Then, the formula (s) and the output(s) are presented to the user.
    Type: Application
    Filed: November 18, 2013
    Publication date: March 13, 2014
    Applicant: WOLFRAM ALPHA LLC
    Inventor: Stephen Wolfram
  • Patent number: 8670557
    Abstract: Systems and/or methods that facilitate secure electronic communication of data are presented. A cryptographic component facilitates securing data associated with messages in accordance with a cryptographic protocol. The cryptographic component includes a randomized exponentiation component that facilitates decryption of data and generation of digital signatures by exponentiating exponents associated with messages. An exponent is divided into more than one subexponent at an exponent bit that corresponds to a random number. Exponentiation of the first subexponent can be performed based on a left-to-right-type of exponentiation algorithm, and exponentiation of the second subexponent can be performed based on a right-to-left square-and-multiply-type of exponentiation algorithm. The final value is based on the exponentiations of the subexponents and can be decrypted data or a digital signature, which can be provided as an output.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: March 11, 2014
    Assignee: Spansion LLC
    Inventors: Elena Trichina, Helena Handschuh, Arnaud Boscher
  • Publication number: 20130339409
    Abstract: The invention concerns a portable computing device comprising a microprocessor capable of running software, hardware means capable of providing at least one physical variable, a memory unit carrying the software adapted to read the physical variable and to perform a mathematical operation utilizing the physical variable. An interface means adapted to allow defining of the mathematical operation in the memory unit by a user of the device. The invention also concerns a firmware product of a microcontroller-operated device, a computer program product and a web service.
    Type: Application
    Filed: December 3, 2012
    Publication date: December 19, 2013
    Inventors: Janne KALLIO, Erik LINDMAN, Mikko MARTIKKA, Kimmo PERNU
  • Patent number: 8553880
    Abstract: The pseudorandom number generating system repeatedly performs simple transformation of a non-secure pseudorandom number sequence that may be generated quickly, and thus may quickly generate a highly secure pseudorandom number sequence having a long period. Furthermore, the encryption system and the decryption system do not generate a large encryption function difficult to be deciphered based on a shared key 122, but prepare multiple functions 126, which perform fast, different types of transformation, and select a combination of functions determined based on information of the shared key 122, and make the selected functions transform a text multiple times, thereby encrypt the text. Each of the functions is fast, and thus transformation by the entire combination is also fast. Furthermore, since the combination of functions and repetitive count can be changed, future improvement in specification is easy. Moreover, security is high since which functions are applied in what order is unknown.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: October 8, 2013
    Assignees: Ochanomizu University, Hiroshima University
    Inventors: Makoto Matsumoto, Takuji Nishimura, Mutsuo Saito, Mariko Hagita
  • Patent number: 8213603
    Abstract: Disclosed herein is an encryption processing apparatus including: a first register device; a second register device; a first flag operation device; a first operation device; a second operation device; a round operation device; a third and a fourth operation device; a second flag operation device; and a fifth operation device.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: July 3, 2012
    Assignee: Sony Corporation
    Inventor: Hiromi Nobukata
  • Patent number: 8214284
    Abstract: A special purpose entity offers a financial product linked to a charitable organization. A monetary donation is made to the charitable organization for paying a premium assigned to the financial product. Capital payments are received from one or more investors for the financial product. The premium is paid by the special purpose entity to the investors. Upon occurrence of a catastrophic event assigned to the financial product, the capital is paid from the special purpose entity to the charitable organization, for funding relief efforts for the catastrophic event. Otherwise, the capital is repaid from the special purpose entity to the investors. Charities and donors can prepare a country for natural and man-made disasters by putting in place funding before a catastrophic event actually occurs.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: July 3, 2012
    Assignee: Swiss Reinsurance Company Ltd.
    Inventors: Albert Otto Selius, Maria Giovanna Guatteri
  • Patent number: 8204713
    Abstract: A results reporting system can generate test results at one or more laboratory sites. Each of the generated test results can be in a conventional unit of measurement. The results reporting system can then convert each of the testing results to a normalized decimal equivalent unit system of measurement. The normalized decimal equivalent unit of measurement can be a unit of measurement that is normalized to an associated reference range of the test result. Once converted to normalized decimal equivalent unit, the test results can be stored in a mass storage device for later reporting. A triggering event (e.g., a request from a reviewing entity) can then trigger the reporting system to generate a results report using the stored test results. The results report can convey the test results to a reviewing entity using the normalized decimal equivalent unit of measurement in graphs, tables or other methods of conveying data.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: June 19, 2012
    Inventor: Kenneth E. Blick
  • Patent number: 8189771
    Abstract: The hash functions with elliptic polynomial hopping are based upon an elliptic polynomial discrete logarithm problem. Security using hash functions is dependent upon the implementation of a computationally hard problem, and the elliptic polynomial discrete logarithm problem provides enough relative difficulty in computation to ensure that the produced hash functions, as applied to message bit strings, are optimally secure. The hash functions are produced as functions of both the elliptic polynomial as well as the twist of the elliptic polynomial, particularly using a method of polynomial hopping.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: May 29, 2012
    Assignee: King Fahd University of Petroleum & Minerals
    Inventors: Lahouari Ghouti, Mohammad K. Ibrahim, Atef J. Al-Najjar
  • Patent number: 8170203
    Abstract: The message authentication code with elliptic polynomial hopping provides methods for the generation of message authentication codes (MACs) utilizing elliptic curves, which are based on the elliptic curve discrete logarithm problem. The elliptic curve discrete logarithm problem is well known to be a computationally “difficult” or “hard” problem, thus providing enhanced security for the MACs. Different elliptic polynomials are used for different blocks of the same plaintext, each elliptic polynomial for each message block being selected at random using an initial secret key and a random number generator.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: May 1, 2012
    Assignee: King Fahd University of Petroleum & Minerals
    Inventors: Lahouari Ghouti, Mohammad K. Ibrahim, Atef J. Al-Najjar
  • Patent number: 8166518
    Abstract: A computer implemented method provides remote access to a plurality of sessions at a computer. The method includes initiating a master process in a context independent from the sessions, establishing a first slave process in a context of a first session, and maintaining communication between the master process and the first slave process. The master process provides access to the computer's display while the display is under control of the first session, detects a second session, having a respective second slave process, communicates with the second slave process, and provides access to the computer's display while the display is under control of the second user session.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: April 24, 2012
    Assignee: Netopia, Inc.
    Inventors: Michael Byron Price, Marc A. Epard, Donald W. Griffin
  • Patent number: 8077847
    Abstract: A method for converting a first time and a first date in a first format to a second time in a second format includes determining a number of seconds that have elapsed between a predetermined date and a beginning of a current year of the first date. The method further includes adding to the determined number of seconds, a calculated number of seconds calculated from the beginning of the current year to a current month and a current day of the first date to obtain a first sum. The first sum varies based on whether the current month is within a leap year and is subsequent to a leap day of the leap year. A number of seconds that have elapsed between a beginning of the current day of the first date and the first time is added to the first sum. Lastly, a predetermined number of seconds is added to the first sum when Daylight Savings Time is in effect to obtain the second time in the second format.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: December 13, 2011
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Kenneth Robert Stroud, Jeffrey Lewis Brandt, Rick Anthony Cherye
  • Patent number: 7953448
    Abstract: A keyboard for a mobile device 400 having a processor 618 for interpreting signals comprises a plurality of keys 410-424 and corresponding indicia including keys associated with alphabetic characters corresponding to an array of letters A-Z. The keys 410-419 that are associated with alphabetic characters number fewer than twenty-six and correspond to one of a QWERTY, QWERTZ, AZERTY, or DVORAK key arrangement. Each of the plurality of keys 410-424 have multiple input surfaces and are arranged in an array of rows and columns that include a first outer column, at least one middle column, and a last outer column. The first and last columns of keys are operable to input at least three different signals to a processor 618 of a mobile device 400 depending upon what input surface of the key 410-424 is pressed. A middle column of keys is operable to input at least five different signals to a processor 618 depending on what input surface of the key 410-424 is pressed.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: May 31, 2011
    Assignee: Research In Motion Limited
    Inventors: Velimir Pletikosa, Jason T. Griffin, Norman M. Ladouceur, Robert Lowles
  • Patent number: 7860687
    Abstract: Methods for applications such as signal processing, analysis, and coding/decoding replace digital signal processing elements with analog components are implemented by combining soft logic gates and filters, permitting the functionality of complex finite state machines to be implemented.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: December 28, 2010
    Assignee: Massachusetts Institute of Technology
    Inventors: Benjamin Vigoda, Neil Gershenfeld
  • Patent number: 7853012
    Abstract: An authentication system and a method for signing data are disclosed. The system uses a hardware software partitioned approach. In its implementation the system of the invention compares favourably with performance and other parameters with a complete hardware or full software implementation. Particularly, advantageously there is a reduced gate count. Also as disclosed in the invention the system makes it difficult for hackers to attack the system using simple power analysis.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: December 14, 2010
    Assignee: Tata Consultancy Services, Ltd.
    Inventors: Aravamuthan Sarangarajan, Thumparthy Viswanatha Rao, Rajiah Murugesh, Narasimhachar Srinidhi, Gundeboina Sreenaiah
  • Publication number: 20100100575
    Abstract: Techniques are disclosed for schedule management. By way of example, a method for managing performance of tasks of a thread associated with a processor comprises the following steps. A request to execute a task of a first task type within the thread is received. A determination is made whether the processor is currently executing a critical section of a task of a second task type within the thread. When it is determined that the processor is not executing a critical section of the second task type within the thread, the task of the first task type is executed within the thread. When it is determined that the processor is executing a critical section of the first task type within the thread, a determination is made whether the request for execution of the task of the first task type within the thread is deferrable based on a prior execution of one or more units of the first task type.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 22, 2010
    Inventors: Joshua Seth Auerbach, David Francis Bacon, Perry Cheng, David Paul Grove
  • Publication number: 20090319980
    Abstract: A method for calculating a composite risk is disclosed. The method may include receiving information associated with a plurality of risk factors. The information may include a timeline for each risk factor, and the timeline may include a plurality of discrete time points. The method may further include determining risk values indicative of risk levels of each risk factor associated with the plurality of discrete time points. The method may also include calculating the composite risk using the determined risk values and a relationship between the composite risk and the plurality of risk factors. The composite risk may include a plurality of composite risk values associated with the plurality of discrete time points.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 24, 2009
    Inventors: Nathan Lee Wilson, Scott William Streitmatter, Frank Chapman Bellrose, Bruce Gehlbach Howell, Stanley Russell Kaniecki
  • Patent number: 7620672
    Abstract: The invention involves a classical computer that runs a special computer program. The program takes as input an initial data-set that contains probabilistic information and returns as output a sequence of elementary operations (SEO). The initial data-set helps determine a classical Bayesian (CB) net. A program called “Q-Embedder” embeds the CB net within a quantum Bayesian (QB) net. A program called “Qubiter” (a quantum compiler) then translates the QB net into an equivalent SEO. The SEO outputted by the classical computer can be used to manipulate an array of qubits in a quantum computer. Application of the SEO to the array, followed by a measurement of the array, yields the value of certain conditional probabilities that we wish to know. The main goal of the invention is to provide a method for performing classical Bayesian net calculations on a quantum computer. Such calculations can be done on a classical computer; the hope is that they can be done much faster on a quantum computer.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: November 17, 2009
    Inventor: Robert R. Tucci
  • Patent number: 7587582
    Abstract: A method and apparatus for efficiently performing graphic operations are provided. This is accomplished by providing a processor that supports any combination of the following instructions: parallel multiply-add, conditional pick, parallel averaging, parallel power, parallel reciprocal square root and parallel shifts.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: September 8, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Subramania Sudharsanan, Jeffrey Meng Wah Chan, Michael F. Deering, Marc Tremblay, Scott R. Nelson
  • Patent number: 7512530
    Abstract: A computer implemented method and system for the generation of software thermal profiles for applications executed on a set of processors in a simulated environment. Execution of a software program being run on a software simulator is detected and hardware operations for the software program being executed by the set of processors are analyzed to create analyzed information. Then, a thermal index is generated based on the analyzed information.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: March 31, 2009
    Assignee: International Business Machines Corporation
    Inventors: Maximino Aguilar, Jr., Charles Ray Johns, Mark Richard Nutter, James Michael Stafford
  • Publication number: 20090024680
    Abstract: In the method of rate-matching, software is used to calculate at least one rate-matching parameter for data, and dedicated hardware is used to perform at least one of a puncturing and repetition process on data based on the calculated rate-matching parameter. In rate de-matching, software is again used to calculate at least one rate de-matching parameter for received data, and dedicated hardware is used to compensate for puncturing and repetition based on the calculated rate de-matching parameter.
    Type: Application
    Filed: May 20, 2008
    Publication date: January 22, 2009
    Inventors: Mark P. Barry, Yi-Chen J. Li, Oliver J. Ridler
  • Publication number: 20080320064
    Abstract: A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level.
    Type: Application
    Filed: December 28, 2007
    Publication date: December 25, 2008
    Inventors: Sung Chung Park, Jun Jin Kong, Seung-Hwan Song, Dong Ku Kang
  • Publication number: 20080183780
    Abstract: A method, computer program product and apparatus are provided for capturing inexact date information. In particular, a sophisticated date entry mechanism is provided that is capable of receiving, as input, date information associated with not only exact dates, but also “fuzzy” (i.e., partial or approximate) dates including, for example, “August of 2006,” or “about the first of June in the year 1996.” This date information may be input via any combination of a mouse, a keyboard, a microphone, or other input element, and in a plurality of different formats, including, for example, a plain language description of the exact or fuzzy date, and/or a relative description of the date. Once the date information has been received, the date entry mechanism is capable of determining in which format the date information was provided, and determining a date corresponding with the date information based on this format.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Inventors: Mimi Amabile, Jeannine Aloe Strope, Larry Constantine
  • Publication number: 20080160177
    Abstract: Methods for forming traces/lines and interconnects on substrates and devices and systems thereof of herein disclosed. In some embodiments, an activator layer is deposited on a surface of a substrate. Pick-up lithography using a pre-patterned lithographic stamp, ultraviolet lithography or like methods are used to selectively remove portions of the activator layer to form a pattern on the surface of the substrate. Electroless metal deposition is then applied to the surface of the substrate to form a metal pattern selectively on the remaining activator layer. Electroless plating can then be used to form traces/lines and interconnects in dimensions of less than 10 micrometers.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: J. C. Mataybas, Lakshmi Supriya, Omar Bchir
  • Patent number: 7389416
    Abstract: In accordance with the present invention, there is provided a method for sharing a secret value x among n participating network devices via an asynchronous network. The n participating network devices comprises t faulty devices and k sub-devices capable of reconstructing the secret value x, wherein t<n/3 and k<n. The secret value x being provided by a distributor.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: June 17, 2008
    Assignee: International Business Machines Corporation
    Inventors: Christian Cachin, Klaus Kursawe, Anna Lysyanskaya, Reto Strobl
  • Publication number: 20080133635
    Abstract: A circuit element includes a plurality of computation blocks connected at least partially in series for processing multi-bit numbers. Each of the computation blocks includes a plurality of transistors having characteristic threshold voltages. The circuit element is configured so that the transistors will each operate at a voltage below its threshold voltage. The circuit element includes a plurality of circuit sub-elements each having an output. The circuit sub-element outputs are connected together.
    Type: Application
    Filed: April 30, 2007
    Publication date: June 5, 2008
    Inventor: Snorre Aunet
  • Publication number: 20080120251
    Abstract: A method of operating a computer system includes storing, in the computer system, a database containing performance measure data regarding performance measures of a plurality of items. The method further includes inputting into the computer system a plurality of performance measure constraints. The method also includes modeling the performance measure constraints with a set of equations. The equations include a plurality of variables. Each of the variables corresponds to a respective one of the items. Each variable is, for example, to be assigned either the value “1” or the value “0”. The value “1” may represent a recommendation to take an action relative to the corresponding item in the portfolio and the value “0” may represent a recommendation to take another action. The computer system is used to solve the set of equations to generate one or more solutions that satisfy the performance measure constraints.
    Type: Application
    Filed: March 27, 2007
    Publication date: May 22, 2008
    Inventors: Rajesh Tyagi, Kete Chalermkraivuth, Marc Anthony Garbiras, John Andrew Ellis, Matthew Allen, James G. Russo
  • Patent number: RE42168
    Abstract: This invention provides a core computer unit that contains all of the components of a conventional computer however will not function unless it is positioned in an enclosure. The enclosure dictates the computer function, the core unit supplies the computer components. The core unit remains dormant and non-functional until it is positioned in a compatible enclosure.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: February 22, 2011
    Assignee: Xybernaut Corp.
    Inventors: Michael D. Jenkins, John F. Moynahan