Zero Suppression Patents (Class 708/166)
  • Patent number: 6230175
    Abstract: A bus for data transmission, bus switches for slicing the bus, and four arithmetic blocks are provided to perform a series of fixed-point arithmetic operations. Each of the four arithmetic blocks has a plurality of digit-serial arithmetic units, namely a multiplier, an adder/subtracter, and a shifter. Each of the digit-serial arithmetic units has the functions of receiving a plurality of input digits representative of an input operand and a digit position indicator of each of the input digits and providing a plurality of result digits representative of an arithmetic result of the input operand and a digit position indicator of each of the result digits to any other one of the plurality of digit-serial arithmetic units. Particularly, the digit-serial adder/subtracter contains therein a selector for input switching so that the digit-serial adder/subtracter can perform butterfly arithmetic.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: May 8, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadashi Okamoto, Hiroshi Kadota, Yoshiteru Mino