Selective Output Patents (Class 708/168)
  • Patent number: 9552348
    Abstract: The present invention provides a method for operating a computer application with spreadsheet functionality. The method comprising receiving one or more inputs in one or more cells by the spreadsheet application, parsing the received inputs for the one or more cells of the spreadsheet, constructing a dependency graph for the one or more parsed input cells, evaluating at least one of the one or more parsed input cells based on one or more criteria in the dependency graph, reconstructing the dependency graph until all of the one or more input cells are evaluated, and returning an output to the spreadsheet application.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: January 24, 2017
    Inventors: Koustubh Moharir, Surya Kumar Saripella, Sushant Reddy, Krishnamurthy Vaidyanathan
  • Patent number: 9323719
    Abstract: A mathematical expression input apparatus includes a mathematical expression display unit configured to display a mathematical expression, a mathematical expression portion designation unit configured to designate a mathematical expression portion displayed by the mathematical expression display unit in accordance with user operation, and an output unit configured to determine a designation method for a mathematical expression portion designated by the mathematical expression designation unit, modify the mathematical expression in accordance with the designation method, and display the modified mathematical expression.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: April 26, 2016
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Saburo Kamitani
  • Patent number: 8725783
    Abstract: A mathematical expression calculation apparatus includes: a display; and a processor to perform the operations of: displaying a mathematical expression on the display; displaying terms included in the mathematical expression displayed on the display in display modes which differ among types of the terms respectively; specifying among the display modes a display mode of any of the terms of the mathematical expression displayed on the display, in accordance with operation of a user; and carrying out calculation among terms which are included in the terms of the mathematical expression displayed on the display and are displayed in the specified mode, and renewing and displaying the mathematical expression.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: May 13, 2014
    Assignee: Casio Computer Co., Ltd.
    Inventor: Satomi Midorogi
  • Publication number: 20130290391
    Abstract: A mathematical expression input apparatus includes a mathematical expression display unit configured to display a mathematical expression, a mathematical expression portion designation unit configured to designate a mathematical expression portion displayed by the mathematical expression display unit in accordance with user operation, and an output unit configured to determine a designation method for a mathematical expression portion designated by the mathematical expression designation unit, modify the mathematical expression in accordance with the designation method, and display the modified mathematical expression.
    Type: Application
    Filed: April 22, 2013
    Publication date: October 31, 2013
    Applicant: CASIO COMPUTER CO., LTD.
    Inventor: Saburo KAMITANI
  • Publication number: 20120096060
    Abstract: A mathematical formula input unit inputs a mathematical formula according to a user manipulation. A calculation unit calculates a calculation result of the mathematical formula. A display unit displays the mathematical formula and the calculation result. A position specifying unit specifics a position in a display area on the display unit according to a user manipulation. A right slide ENG display control unit performs ENG normal conversion to the calculation result and updates display contents thereof when a position of the calculation result is specified by the position. specifying unit and a slide manipulation is performed toward the right. A left slide ENG display control unit performs ENG inverse conversion to the calculation result. and updates display contents thereof when a position of the calculation result is specified by the position specifying unit and a slide manipulation is performed toward the left.
    Type: Application
    Filed: October 11, 2011
    Publication date: April 19, 2012
    Applicant: CASIO COMPUTER CO., LTD.
    Inventor: Makoto OZAWA
  • Publication number: 20110225219
    Abstract: A mathematical expression calculation apparatus includes: a display; and a processor to perform the operations of: displaying a mathematical expression on the display; displaying terms included in the mathematical expression displayed on the display in display modes which differ among types of the terms respectively; specifying among the display modes a display mode of any of the terms of the mathematical expression displayed on the display, in accordance with operation of a user; and carrying out calculation among terms which are included in the terms of the mathematical expression displayed on the display and are displayed in the specified mode, and renewing and displaying the mathematical expression.
    Type: Application
    Filed: February 17, 2011
    Publication date: September 15, 2011
    Applicant: CASIO COMPUTER CO., LTD.
    Inventor: Satomi MIDOROGI
  • Patent number: 6857002
    Abstract: In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: February 15, 2005
    Assignee: Cirrus Logic, Inc.
    Inventors: Axel Thomsen, Jerome E. Johnston, Edwin De Angel, Aryesh Amar
  • Patent number: 6142367
    Abstract: The present invention is intended to enable an electronic calculator device for calculating functions to display a mathematical expression by automatically substituting a variable-value into a variable therein in advance. An electronic device comprises an input device for inputting a mathematical expression containing a variable, a store device for storing a value of the variable and a display device for displaying a mathematical expression on a display screen. The electronic device is further provided with a converting device for reading a value for a variable contained in a mathematical expression from the store device and substituting the read-out value into the variable in the mathematical expression to be displayed on the display screen.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: November 7, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akiyoshi Satoh, Toshiro Oba, Fumiaki Kawawaki
  • Patent number: 6070216
    Abstract: A serial I/O incorporated semiconductor device comprises a transmitting unit 4 including a transmission channel selection register 14 for selecting a transmitting pin to output transmit data and a receiving unit 5 including a receiving channel detection circuit 26 for detecting receiving pins that have received data; a receiving channel flag 27 set to have a predetermined value by the receiving channel detection circuit; a plural channels reception detection circuit 28 for detecting that received data is entered to a plurality of receiving pins; and a plural channels receiving flag 29 set to have a predetermined value by the plural channels reception detection circuit 28 detecting received data has been entered to the plurality of receiving pins; wherein when any one of the flags 23, 25, and 29 is set to a predetermined value, the receiving unit supplies the value to a CPU as a reception interrupt signal.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: May 30, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoichi Kitakami, Hiroki Takahashi
  • Patent number: 6026449
    Abstract: The inventive computer includes a RAM which sequentially stores a series of calculation expression data thereto, a proof unit which proves the series of calculation expression data by inputting those data again, and a display which displays calculation data found to be non-coincident in the proof operation. First, when a series of calculation expression data is input to the computer, the computer performs a required calculation on the series of calculation expression data and sequentially stores the data in the RAM. After the series of calculations on the data is completed, the user inputs data on designation of a proof operation to confirm whether the result of the calculation is correct. Thus, the proof mode is selected and a second series of calculation expression data is input.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: February 15, 2000
    Assignee: Casio Computer Co., Ltd.
    Inventors: Makoro Takenaka, Yasuo Ikeya, Katsuyoshi Suzuki