Sequential Output Patents (Class 708/169)
  • Patent number: 10613756
    Abstract: Aspects disclosed in the detailed description include hardware accelerated storage compression. In one aspect, prior to writing an uncompressed data block to the storage device, a hardware compression accelerator provided in a storage controller compresses the uncompressed data blocks individually into a compressed data block and allocates the compressed data block to a storage data block in the storage device. The hardware compression accelerator then generates a modified logical block address (LBA) to link the uncompressed data block to the compressed data blocks. In another aspect, the hardware compression accelerator locates a compressed data block based on a corresponding modified LBA and decompresses the compressed data block into an uncompressed data block.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: April 7, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Hyunsuk Shin, Jung Pill Kim, Assaf Shacham
  • Patent number: 8713080
    Abstract: The present application addresses a fundamental problem in the design of computing systems, that of minimizing the cost of memory access. This is a fundamental limitation on the design of computer systems as regardless of the memory technology or manner of connection to the processor, there is a maximum limitation on how much data can be transferred between processor and memory in a given time, this is the available memory bandwidth and the limitation of compute power by available memory bandwidth is often referred to as the memory-wall. The solution provided creates a map of a data structure to be compressed, the map representing the locations of non-trivial data values in the structure (e.g. non-zero values) and deleting the trivial data values from the structure to provide a compressed structure.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: April 29, 2014
    Assignee: Linear Algebra Technologies Limited
    Inventor: David Moloney
  • Publication number: 20110113080
    Abstract: According to one embodiment, there is provided an electronic calculator, including a display device, a storage having an operator priority table in which an operator operation priority is stored, and a processor that performs causing the display device to display a formula, performing sequentially an operation of each formula element constituting the formula displayed on the display device according to the operator priority table, displaying distinctly the formula element, to which the operation is performed in the formula displayed on the display device, on the display device each time each formula element operation is sequentially performed, and displaying a solution corresponding to the formula element to which the operation is performed on the display device each time each formula element operation is sequentially performed.
    Type: Application
    Filed: October 27, 2010
    Publication date: May 12, 2011
    Applicant: CASIO COMPUTER CO., LTD.
    Inventor: Akiko Muraki
  • Patent number: 7148818
    Abstract: A method of command entry for an electronic device. First, a single button is pressed to enter the electronic device into a multi-function entry state, indicated by a first light status. The button is pressed again within a first predetermined period after entering the multi-function entry state, corresponding to one command. The light indicator displays a second light status corresponding to the command. Finally, the button is pressed again to confirm the command within a second predetermined period.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: December 12, 2006
    Assignee: Lite-On IT Corporation
    Inventors: Kun-Chang Chang, Chien-Chun Ma, Tung-Wei Kao