Abstract: A distributed data storage system can be configured with a host connected to a first device and an initialization module that performs a default initialization procedure on the first device in response to detecting the first device has an unknown manufacturing origin. Conducting the default initialization procedure may allow the first device to service data access requests from the host. In response to the connection of a second device to the host and initialization module, a manufacturing origin of the second device is identified with the initialization module before the initialization module customizes the default initialization procedure to a custom procedure that is executed to allow the second device to satisfy a background operation prescribed by the initialization module.

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

Abstract: Described herein is a technology for a wakeup pattern-data stream correlation by a detector to provide a trigger condition for a microcontroller in a wakeup receiver (WuRX). For example, the detector includes a data packet layer with a plurality of index registers that are updated through sampling of data streams. A sample clock is coupled to each of the plurality of index registers to independently activate each of the plurality of index registers. A shared comparator will then compare the updated plurality of index registers to corresponding shift registers that are initialized with rotating wakeup pattern bits. Based upon a number of matching results, the detector generates a triggering signal that facilitates a low-power operating mode to a high-power operating mode change.

Abstract: A method to be implemented by the server includes steps of: during a power-on self-test, determining whether a storage device is communicatively connected to the server; when it is determined that a storage device is communicatively connected to the server, determining whether the storage device stores a script file having a preset filename; and when it is determined that the storage device stores a script file having the preset filename, performing a process of modifying the BIOS based on the script file.

Abstract: A wearable electronic device accommodatable in an external electronic device may include a communication circuit, and at least one processor.

Abstract: This disclosure describes techniques and mechanisms for disclosure describes techniques and mechanisms for a central management plane to automatically create and assign system identifiers to network devices, thereby creating a global network hierarchy within a network. The techniques enable the use of a system identifier to be automatically generated and assigned, as well as configuration and network policies to be automatically generated based on the system identifier. Accordingly, the techniques enable automation of regional connectivity and policy application, a simplified manner of troubleshooting/debugging of any connectivity issues, and a simplified, aggregated view of statistic and analytics related to problems at site, sub-region, and region levels.

Abstract: Methods, systems, and devices for transitioning an information handling system (IHS) to a predetermined operating state is disclosed. During the transition, the IHS may obtain data from a variety of sources which may subject it to compromise. To reduce the likelihood that the IHS is compromised, the IHS may evaluate its environment and its own operation to determine its security state. Depending on its security state, the IHS may perform various actions to reduce the likelihood of it being compromised through its transition process.

Abstract: A processor configured for real-time transaction processing is disclosed. A processor circuit includes configuration registers that designate a first range of physical memory addresses as reserved for real-time memory requests and a second, non-overlapping range of physical memory addresses that are shared between real-time and non-real-time memory requests. In response to determining that a memory request is associated with an address in the first range, the processor tags the request as a real-time request. The configuration registers may also store information designating portions of one or more cache memories and one or more buffers as being reserved for real-time memory requests. During arbitration, real-time memory requests are given priority over older, non-real-time memory requests.

Abstract: Techniques for emulating a configuration space may include emulating a set of configuration registers for a set of functions corresponding to a type of peripheral device. The set of functions can include a physical function and a virtual function associated with the physical function. A configuration access request can be processed by retrieving an emulated configuration register from the emulated configuration space, and logging incoming configuration access requests in a configuration transaction log to track configuration accesses.

Abstract: A network (e.g. cloud or enterprise network) includes servers (110) and switches (120) each of which has multiple ports. A bare-metal server's ports are configured for different roles, e.g. management role or data role. The configuration is at least partially automated using a blueprint (340) which does not necessarily specify the roles for the server ports, but may associate a role with a network parameter, e.g. Maximum Transfer Unit (MTU) or QoS. A management computer (320) obtains, from switches, (i) network parameters configured on switch ports, and (ii) MAC addresses for the adjacent server ports. The management computer matches the blueprint's parameters with the switch ports' parameters, and associates matched parameters with the roles specified by the blueprint. These roles are configured on the corresponding server ports. Other features are also provided.

Abstract: An integrated computing system configuration system includes a computing system that executes an engine to receive component specifications for each of one or more components supplied by a plurality of suppliers, and receive user input for selecting a subset of the components to be implemented in a customized integrated computing system by generating a base integrated computing system configuration that comprises the component specifications of the subset of the components. The engine may then apply one or more rules to at least one of the component specifications to verify the subset of components, the rule specifying an architectural standard level to be provided by the at least one component, and display the results of the verification on a display.

Abstract: A system for establishing and maintaining a chain of trust can include a root of trust (RoT) executing a root trusted server that pushes authenticated code and data into memory of a given node in a plurality of nodes. The RoT can also record a memory address range of a static portion of the authenticated code and a corresponding static data in the given node and cause the given node to execute the authenticated code in response to the pushing to establish a trusted relationship between the trusted server of the RoT and the given node. The root trusted server also monitors the given node to ensure that the given node executes trusted operations. The authenticated code in the memory of the given node can include a trusted server that pushes authenticated code into memory of another node in the plurality of nodes.

Abstract: A method of operating a Peripheral Component Interconnect Express (PCIe) device including a first port and a second port comprises: performing a first link training operation to link up a first host with a first link of the first port; operating in a single port mode when the first link training operation is completed; performing a lane reduce operation to reduce a lane corresponding to the first link in response to a mode change request received from the first host; and performing a second link training operation to link up a second host with a second link of the second port when a status of the first link is an L0 state.

Abstract: Hardware-based wake detection and system-on-chip (SoC) firmware support for servicing fixed display port (DP) and High Definition Multimedia Interface (HDMI) port hot plug events which allow a Universal Serial Bus (USB) Type-C subsystem to go into a powered off state while the fixed display is not streaming. Upon receiving a display software-initiated wake for fixed display streaming in response to a hot plug detect, the SoC USB Type-C firmware triggers exit low-power state flow to power up the USB USB Type-C subsystem to handle the display traffic. The SoC USB Type-C firmware has the capability to autonomously re-enter the low power state when the fixed display(s) are not streaming.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed including a capacitor, located in a universal serial bus schematic. The methods, apparatus, systems and articles of manufacture include a controller, include a controller including a state machine and a control signal generator, wherein the controller is configured to be coupled to a connector and to a power supply, the state machine is configured to determine a state of the connector, and the control signal generator is configured to, in response to an indication of a device not connected to the connector, generate a signal to indicate to the power supply to charge a capacitor to a threshold voltage, and wherein the control signal generator is further configured to generate the signal until a second state.

Abstract: A switching fabric role assignment system includes a plurality of switch devices coupled together in a switching fabric. A first switch device included in the plurality of switch devices receives an endhost device identification communication from an endhost device when the endhost device is connected to the first switch device. The first switch device uses the endhost device identification communication to identify an endhost device type of the endhost device and determines, based on the endhost device type, a first switch device role for the first switch device. The first switch device then transmits a first switch device role communication that identifies the first switch device role to a second switch device included in the plurality of switch devices and connected to the first switch device. The second switch device may then determine, based on the first switch device role, a second switch device role for the second switch device.

Abstract: There is disclosed an example of a computing apparatus for providing a hardware-assisted virtual switch on a host, including: a hardware virtual switch (vSwitch) circuit; and a hardware virtual host (vHost) circuit, the vHost circuit having an interface driver specific to the hardware vSwitch and configured to provide a vHost data plane to: provide a plurality of hardware queues to communicatively couple the hardware vSwitch to a guest virtual function (VF); and present to a virtual network driver of the guest VF an interface that is backward compatible with a software network interface.

Abstract: Embodiments herein describe using software or firmware to manage the device capability list of a PCIe device. That is, rather than relying on pure hardware to advertise the capabilities of a PCIe device, the embodiments herein permit software or firmware executing on a processor in the PCIe device to manage read and write requests associated with discovering the capabilities of the device and configuring the device.

Abstract: Methods for providing simultaneous access to a hardware data stream to multiple applications are disclosed. The first application to access a hardware device is responsible for providing and publishing an application programming interface (API) that provides access to the hardware device's data stream, which other applications can then call to gain access to the data stream. In some examples, the first application may be a server process or daemon dedicated to managing the hardware device data stream and publishing the API. In some further examples, the first application may instead may carry out user functionality unrelated to managing the hardware device.

Abstract: A control device having an integrated switch and being configured to logically enable and disable an Ethernet port of the integrated switch. Further disclosed is a device network consisting of at least two field devices, a primary control device and a primary switch, a secondary control device and a secondary switch, which are connected in a daisy chain loop topology. And wherein the secondary control device is configured to logically enable and disable an Ethernet port of the secondary switch. Further disclosed is a flat network consisting of such a device network. Further disclosed is a method for controlling a redundant connection in a flat network, consisting of detecting failure of the primary control device, initiating failover, enabling the Ethernet port of the secondary switch, and disabling the Ethernet port of the primary switch.

Abstract: A method for configuring identical network components wherein network components are each connected to a physical port of a network switch via a network cable. An additional network station is also connected to the network switch. Configuration messages are transmitted from the additional network station to the network components wherein the configuration message of each network component communicates the physical port of the network switch to which the network component is connected. The network component performs a reconfiguration of its function in the network corresponding to the connection to the physical port.

Abstract: A computing device (e.g., a mobile device) can execute a root process of an application to an initial point according to patterns of prior executions of the application. The root process can be one of many respective customized root processes of individual applications in the computing device. The device can receive a request to start the application from a user of the device. And, the device can start the application upon receiving the request to start the application and by using the root process of the application. At least one of the executing, receiving, or starting can be performed by an operating system in the device. The device can also fork the root process of the application into multiple processes, and can start upon receiving the request to start the application and by using at least one of the multiple processes according to the request to start the application.

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

Abstract: Managing devices in an IoT environment. A method includes, as a result of a device being provisioned by a special-purpose solution, storing at a central unified registry a correlation of the device and the given special purpose solution. The method further includes correlating the device to a different special-purpose solution at the unified registry. As a result, the method further includes causing subsequent configuration of the device to be performed by the different special-purpose solution.

Abstract: In some examples, a device for applying an operating mode to a point of sale (POS) peripheral device can include a non-transitory machine readable medium storing instructions executable by a processing resource to detect a peripheral device, access a configuration file based on the detected peripheral device, wherein the configuration file includes a plurality of operating modes associated with the detected peripheral device, and apply one of the plurality of operating modes to the detected peripheral device.

Abstract: An asset includes physical computing resources and a physical computing resources manager. The physical computing resources manager obtains a resource update for the asset; makes a determination that the resource update requires a reset of a portion of the physical computing resources; and, based on the determination, resets the portion of the physical computing resources during a low resource consumption reboot of the asset without resetting a second portion of the physical computing resources, the second portion of the physical computing resources are not reset as part of the low resource consumption reboot.

Abstract: The present disclosure generally relates to prefetching data from one or more CPUs prior to the data being requested by a host device. The prefetched data is prefetched from memory and stored in cache. If a host device requests data that is not already in cache, then a determination is made regarding whether the data is scheduled to be written into cache. If the data is not in cache and is not scheduled to be written into cache, then the data is retrieved from memory and delivered to the host device. If the data is scheduled to be written into cache, or is currently being written into cache, then the request to retrieve the data is delayed or scheduled to retrieve the data once the data is in cache. If the data is already in cache, the data is delivered to the host device.

Abstract: A single-wire bus apparatus that includes a bus slave circuit(s) is provided. The bus slave circuit(s) can receive a unicast, a multicast, and/or a broadcast command sequence over a single-wire bus. In embodiments disclosed herein, the bus slave circuit(s) can be configured to determine whether to respond to a received multicast or broadcast command sequence based on a predefined response policy. As such, the single-wire bus apparatus can be configured to mix and match a legacy slave circuit(s), which always responds to the received multicast or broadcast command sequence, with an enhanced slave circuit(s) that can decide whether to respond to the received multicast or broadcast command sequence based on the predefined response policy. As a result, it is possible to improve design and implementation flexibility, such as supporting more bus slave circuits per port.

Abstract: An apparatus comprises a processing device configured to control delivery of input-output operations from a host device to a storage system over selected ones of a plurality of paths through a network. The processing device is further configured to send one or more requests to the storage system for data corresponding to states of a plurality of storage devices in the storage system. The one or more requests comprise a directive that the data corresponding to the states returned by the storage system relate to changes in the states of the storage devices. The processing device is also configured to receive the data corresponding to the states from the storage system, to identify one or more state changes of one or more of the storage devices based on the received data, and to manage one or more of the input-output operations responsive to the identified one or more state changes.

Abstract: Hardware-based wake detection and system-on-chip (SoC) firmware support for servicing fixed display port (DP) and High Definition Multimedia Interface (HDMI) port hot plug events which allow a Universal Serial Bus (USB) Type-C subsystem to go into a powered off state while the fixed display is not streaming. Upon receiving a display software-initiated wake for fixed display streaming in response to a hot plug detect, the SoC USB Type-C firmware triggers exit low-power state flow to power up the USB USB Type-C subsystem to handle the display traffic. The SoC USB Type-C firmware has the capability to autonomously re-enter the low power state when the fixed display(s) are not streaming.

Abstract: A power control method for controlling power paths between a baseboard and a server board includes: conducting a first power path between the baseboard and a detecting module of the server board via an isolated module; the baseboard obtaining a type of server card of the server board before the server board is powered on; and cutting off the first power path and conducting a second power path between a power source module of the server board and the detecting module of the server board via the isolated module after the server board is powered on; wherein the baseboard provides a side-band signal to the server board.

Abstract: In one embodiment, a method for enumerating logical identifiers for a plurality of backplanes of an information handling system includes: generating, by each of the plurality of backplanes, inventory information indicating a plurality of backplane attributes; sending, by each of the plurality of backplanes, the inventory information to a baseboard management controller; receiving, by the baseboard management controller, the inventory information from each of the plurality of backplanes; determining, by the baseboard management controller, a backplane topology of the information handling system based on the inventory information, the backplane topology indicating a backplane location for each of the plurality of backplanes; generating, by the baseboard management controller, a logical backplane identifier for each of the plurality of backplanes based on the backplane topology; and assigning, by the baseboard management controller, the logical backplane identifier to each of the plurality of backplanes.

Abstract: The present invention discloses a storage device including a memory module and a memory controller. The memory controller includes a memory interface control unit, a command queue, a selecting unit, a buffer and a processing unit. The processing unit is configured to perform: generating a plurality of macro commands by combining a plurality of sequences of memory operation commands; writing the macro commands into the buffer; writing one or more than one operation parameter of the macro command corresponding to a host command into the buffer according to the host command outputted from a host; commanding the selecting unit to select the buffer as an input terminal; and commanding the buffer to output the macro command corresponding to the host command.

Abstract: An imaging apparatus to which an accessory apparatus is attachable includes a camera controller configured to communicate with the accessory apparatus. The camera controller receives first information on a data size receivable by the accessory apparatus, performs a setting for a data size to be transmitted to the accessory apparatus based on the first information, and communicate with the accessory apparatus based on the setting.

Abstract: A system and method for message analysis, including: receiving, by a control service, a first modification request to modify a file system of a computing device, wherein the computing device is operating in a read-only state; identifying, by the control service, a request parameter associated with the first modification request; determining, by the control service, that the request parameter satisfies a permission criteria to perform the first modification request; provisioning, by the control service, the computing device to operate in a read/write state in response to determining that the permission criteria has been satisfied, wherein the first modification request is executed to modify the file system while the computing device is operating in the read/write state; and, upon a determination that the first modification request has successfully completed, provisioning, by the control service, the computing device to operate in the read-only state.

Abstract: A method for changing over a general-purpose OS display for an information processing apparatus to a dedicated display screen includes accessing a setup procedure describing setup processing and at least an account generating process for generating user account information for a general-purpose operating system (“OS”). The method includes accessing changeover information for changing over a general-purpose OS display screen for the information processing apparatus to a dedicated display screen, and in response to starting up the general-purpose OS for the first time, executing the setup processing including the user account generating process based on the setup procedure stored by the procedure storage unit, changing over the general-purpose OS display screen to the dedicated display screen based on the changeover information stored by the changeover information storage unit, and displaying the dedicated display screen. An apparatus and a program product perform the method.

Abstract: Priority reversing data traffic for latency sensitive peripherals, including receiving a connection notification and parameters of a peripheral; identifying, from the parameters, that an interface type associated with the peripheral is a bulk interface, the bulk interface associated with a first communication channel between the IHS and the peripheral and having a first latency; determining, based on the bulk interface type and a data traffic priority associated with the peripheral, that the data traffic associated with the peripheral is priority-inversed; in response to a communication request by an application executing on the IHS for communication with the peripheral, determining that the data traffic associated with the peripheral is priority-inversed, and in response, placing the data traffic in a queue associated with a second communication channel defined between the IHS and the peripheral, the second communication channel having a second latency, wherein the first latency is greater than the second la

Abstract: The technology disclosed in this patent document can be implemented in embodiments to provide a memory controller configured to control a memory device and a method of operating the memory controller and the memory device. The memory controller may control a memory device including a plurality of pages, and may include a command analysis unit configured to generate command information indicating a type of read command for a page selected from among the plurality of pages, and an initialization time decision unit configured to decide on a channel initialization time for initializing channels of a plurality of memory cells included in the selected page based on the command information.

Abstract: A peripheral device may implement storage virtualization for non-volatile storage devices connected to the peripheral device. A host system connected to the peripheral device may host one or multiple virtual machines. The peripheral device may implement different virtual interfaces for the virtual machines or the host system that present a storage partition at a non-volatile storage device to the virtual machine or host system for storage. Access requests from the virtual machines or host system are directed to the respective virtual interface at the peripheral device. The peripheral device may perform data encryption or decryption, or may perform throttling of access requests. The peripheral device may generate and send physical access requests to perform the access requests received via the virtual interfaces to the non-volatile storage devices. Completion of the access requests may be indicated to the virtual machines via the virtual interfaces.

Abstract: A baseboard management controller (BMC) may be configured to enable a communication interface from the BMC to a host processor on a host computing device and provide input to the host processor via the communication interface. The input causes at least one diagnostic operation to be performed on the host computing device. The BMC may collect host information in response to the diagnostic operation(s) being performed. The BMC may report the host information to another entity and/or store the host information in persistent memory within the BMC. In some embodiments, the input may be provided to the host processor in response to receiving a signal from a fabric controller. In some embodiments, the input may be provided to the host processor in response to detecting an anomaly associated with the host computing device. The BMC may take at least one action to mitigate the anomaly.

Abstract: Individual interfaces of USB composite devices can be blocked. When a USB device is connected to a host system, a filter driver can be loaded on top of the USB hub driver and can be configured to monitor I/O control (IOCTL) requests that are sent as part of the enumeration process. When the filter driver detects that the USB device is a USB composite device, it can selectively modify the descriptors that the USB composite device reports based on the number of interfaces that will not be blocked. This selective modification of the descriptors enables individual interfaces to be blocked without filtering the USB composite class driver which in turn minimizes or eliminates any conflicts that may otherwise exist.

Abstract: A method and system method for communication port management in a device. The method including enabling a set of communication ports in response to power up of the device, detecting connection at a port in the set of communication ports prior to operating system boot of the device, and connecting an external device to an operational component of the device in response to the connection at the port.

Abstract: An identification number setting system includes a first element component including a first storing section, coupled to a first branch communication line branching from a main line of a bus-type communication wire, and coupled to a power supply, a second element component including a second storing section, coupled to a second branch communication line branching from the main line, and coupled to the power supply to be capable of switching energization and disenergization, and a control device coupled to the main line and configured to communicate with the first element component and the second element component. The control device writes a first identification number in the first storing section in a first state and writes a second identification number different from the first identification number in the second storing section after the writing of the first identification number and in a second state.

Abstract: The system and methods described herein provided for automatically configuring a network port at a first network device with isolation parameter. A network device receives a network access message that includes network access parameters to be used when a second network device communicates with the first network device. The network device determines network isolation parameter based on the network access parameters to be used for a plurality of network packets received from the second network device. The network device determines whether the port of the network device is configured with the network isolation parameter, and, if not so configured, the network device automatically configures the port with the network isolation parameter.

Abstract: PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.

Abstract: A field device I/O connector includes a base and an I/O module removably mounted on the base for transmitting I/O signals along an I/O channel. A set of electrical connectors mounted on the base connect the base to a field device. The electrical connectors, the base, and the I/O module mounted on the base cooperate to define the I/O channel. The I/O channel includes a conversion circuit to convert between I/O signals and a digital data format output from the field device I/O connector. The base and I/O module also cooperate to define a diagnostic circuit connected to the portion of the I/O channel extending through the I/O module. The diagnostic circuit extends to a diagnostic logic circuit that may be included on the base, in the I/O module, or away from the field device I/O connector.

Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.

Abstract: Provided are techniques for automatically detecting and configuring a variety of spray system components. The techniques include a controller configured to detect one or more spray system components. The controller is also configured to initialize software drivers corresponding to the spray system components upon connection of the spray system components to the controller. The techniques may provide one or more hardware on top (HAT) boards configured to couple to the controller and the spray system components.

Abstract: An information processing system includes a control unit, a peripheral device including a first register, a second register, and an initialization flag circuit, in which the initialization flag circuit is configured to output a high level signal when the information processing system is started and is configured to output a low level signal in a case where data indicating a low level is written into the second register, the low level signal being the same level as the low level, and in which the control unit is configured to write initial setting data for initializing the peripheral device into the first register in a case where the control unit determines that an output signal from the initialization flag circuit is a high level and is configured to write data indicating a low level into the second register, the low level indicating that writing of the initial setting data is completed.