Abstract: A point-of-sale system is disclosed which is freely configurable with a plurality of peripheral input devices. The system includes a general purpose computer having a communications port for receiving and/or transmitting data. An electronic interface is coupled to the communications port and readily connectable to the plurality of peripheral input devices for communicating data between the plurality of input devices and the computer. The plurality of peripheral input devices can be selectively connected and disconnected from the electronic interface, the electronic interface maintaining a continuous dialogue with the computer during the connection and disconnection of the input devices.

Abstract: A device for effecting communication between a peripheral and a host computer of the present invention. The invention is particularly well-adapted for use with printers, copies and other devices not equipped with consumable resource sensing technology at the time of manufacture. In general, the inventive device is disposed within a separate housing and includes an interface for effecting signal translation and routing as necessary between the peripheral and a host computer. The device further includes first mechanisms for effecting communication between a sensor operationally coupled to the peripheral and the interface. Further included are second mechanisms for effecting communication between the interface and the host computer. Plural sensors may be operationally coupled to the peripheral. In the best mode, the sensors are E-labeltm sensors. The interface may be implemented with a microprocessor, digital logic or simple discrete components depending on the application.

Abstract: A system and signal processing method, in which at least two processors have prioritized, shared access to one or more devices connected along a bus. In preferred embodiments, a fast processor is connected along a first bus, a slow processor and shared device are connected along a second bus, and a communication device is connected between the buses. The communication device is configured to provide the fast processor continuous access to the shared device (in response to grant of an access request by the fast processor) for a limited time that is longer than the time required for a single word transfer, but the slow processor must contend with the fast processor for access to the shared device each time after the slow processor completes a word transfer. Preferably, the communication device provides the fast processor continuous access to the shared device for up to a maximum number of word transfers in response to grant of one access request by the fast processor.

Abstract: A universal access controller is described. The universal resource access controller is coupled to a requesting system and a resource, such that when the requesting system desires access to the resource, the requesting system generates a resource access request which is passed to the universal resource controller. The universal resource controller, in turn, uses a specific characteristic operating parameter of the requested resource as well as a current state of the requested resource to generate a corresponding sequenced universal access request command suitable for accessing the resource as required by the requesting system.

Abstract: A recording apparatus and a signal control method for the recording apparatus capable of high speed data reception suitable for each host apparatus and an improved throughput. The recording apparatus is provided with an interface control block and a CPU, the former transmitting an ACKX signal representative of a completion of data reception from a host apparatus to the host apparatus, and the latter controlling not to output the ACKX signal if it is judged that the ACKX signal is unnecessary, and to output the ACKX signal with an optimum width if it is judged that the ACKX signal is necessary.

Abstract: A method and system for communicating an event message from a server connected to at least one peripheral device and at least one client via a network between a peripheral device and at least one client operably connected via a network. The method includes the server sending a message to any available peripheral device, responding to an event message from at least one peripheral device, responding to an acknowledgment message from at least one client, and responding to an expired timeout.

Abstract: A system and method for indicating the availability of a controller channel are disclosed. A system incorporating teachings of the present disclosure may include a controller operable to manage an array of data storage devices. The devices may include, for example, disk drives with both read and write functionality. Preferably, the controller will have at least one channel, which may have both an internal and an external connector. The system may also include an indicator operable to indicate when a data storage device is attached to an internal connector of a given channel. As such, employing teachings of the present disclosure may allow a user to accurately and expeditiously determine whether a given controller channel is available.

Abstract: A serial bus controller having improved bus performance when a physical read request or a physical write request is present. A link and physical layer logic unit is provided, coupled to a serial bus having at least one peripheral device coupled thereto. A host interface is provided, coupled to a host data bus. A request FIFO is provided, coupled to receive a host memory read or write request packet from the link and physical layer logic unit, and coupled to said host interface. A physical read request FIFO is provided, coupled to receive a physical read request from the request FIFO for further processing of the physical read request. A physical write request FIFO is provided, coupled to receive a physical write response for transfer to the peripheral device.

Abstract: The invention relates to the detection of the presence of a connector in a socket (10), the connector keeping a pin (13) of the socket to a a given level. The invention suggests to take advantage of this for detecting the presence of the connector, by trying to pull the pin to another-level (20, 21), and determining whether the level on the pin is the given level or the other level. For a socket for a WOL connector in the motherboard of a computer, the pin used is the wake signal pin, which is normally at a low level. Pull-up means are used to try and pull-up the voltage at the pin. This voltage is measured by scanning the status bit of the event register of the controller, to which the pin is connected. The voltage is pulled up only if no connector is plugged into the socket.

Abstract: An information processing apparatus to which a plurality of devices are connected comprises: an obtaining means for obtaining system setting information provided by the operating system; and a displaying means for recognizing the connection status of the plurality of devices based on the system setting information obtained by the obtaining means, and displaying the connection status of the plurality of devices. Also, an information processing apparatus to which a plurality of devices are connected comprises: an obtaining means for obtaining connection information of the plurality of devices; a comparing means for comparing the length of character strings of connection information for the plurality of devices, based on connection information obtained by the obtaining means; and a displaying means for displaying the connection status of the plurality of devices according to the comparison results from the comparing means.

Abstract: The present invention is a method and system to automatic loading program on a medium into memory for execution. In one embodiment, a mode word is configured. The insertion of the medium into a drive is detected based on the mode word. A program on the medium is started when insertion is detected. In another embodiment, a polling circuit in a chipset detects the insertion of the medium into the drive. A status bit is checked in response to an interrupt generated by the polling circuit. A flag in a memory is updated based on the status bit. A poll request by an operating system is responded.

Abstract: A method of using bank tag registers in a multi-bank memory device to avoid background operation collision is described. A memory controller includes a plurality of bank registers, each of which is associated with one of a plurality of memory banks, wherein a bank register is arranged to store information, a bank number, a bank status, and a bank counter for a particular bank. The memory controller further includes an adjustable bank comparator coupled to each bank register. The memory controller receives an incoming system address request, which includes a requested bank number. The requested bank number is used to configure the adjustable bank comparator with the particular bank operating characteristics, to locate the bank register, and to determine the bank status and the bank entry status of the requested memory bank. The requested memory bank is accessed when the bank entry status identifies the requested memory bank as open.

Abstract: A system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is “soft” and freely defined. A system management interrupt (SMI) pin is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.

Abstract: In a data storage system that employs multiple storage drives to access removable data storage media, idle data storage media are analyzed and than selectively demounted by automated equipment to increase storage drive availability and also minimize unnecessary mount/demount operations. Initially, the system establishes a maximum permitted number of concurrently mounted idle storage media, and also establishes a maximum permitted length of time for leaving idle storage media mounted. Next, storage media mounted to the media drives are analyzed for possible demounting. The system determines how many storage media are presently mounted, and each media's mount time. Then, the system identifies suitable demounting candidates (if any) to comply with the established maximums.

Abstract: A method and apparatus for configuring multiple devices in a computer system is presented. Upon receipt of a device enumeration request corresponding to a first device, an indication that the first device is inoperable is returned. In response to a second device enumeration request corresponding to a second device, an indication of the capabilities of the second device is returned. When a configuration command corresponding to the second device is received, configuration information derived based on the configuration command is provided to both the first and second devices such that uniform parameter configuration is achieved with respect to the first and second devices. Because the operating system that issues the device enumeration request is informed that the first device is inoperable, the first device will be rendered unconfigurable and therefore configuration commands addressed to the first device will not be generated by the operating system.

Abstract: A method of monitoring issuance of interrupt and transaction commands without involving central processor units of computer systems. The method employs a fabric controller to manage transaction commands among peer and host devices. The method employs an interrupt controller to manage interrupt commands issued by peer devices. With this method, congestion due to control and data traffic is minimized and a more efficient operation of central processor units is achieved.

Abstract: Embodiments of the present invention comprise systems and methods for detecting the status of printing devices and recovering from printing errors.

Abstract: Embodiments of the present invention comprise methods and systems which enable a user to detect the status of printing devices without the use of additional hardware or application program modification for this purpose. These embodiments comprise a print processor which can check printing device status prior to sending a print task to a printing device. These embodiments may further check the status of a printing device after a print task has been sent to the device and may determine whether a printing device has successfully completed a print task. Some embodiments may further redirect, restart and reconfigure print tasks with the help of printing device status information.

Abstract: The present invention provides a network peripheral sharing system comprising a computer network, at least one client computer connected to the computer network, at least one server computer connected to the computer network, and a network address table containing network addresses of server computers connected to the computer network. Each client computer has a peripheral searching program that searches peripherals connected to the computer network and each server computer has at least one connected peripheral. The peripheral serving program in the server computer provides information on the status of peripherals to the client computer and transmits the status message of the peripheral to the client computer after receiving a request from the user thus establishing a link between the client computer and the peripheral.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A standard platform independent messaging environment for use with devices is provided. The environment provides programming and operational building blocks that can be used to interface with existing data providing capabilities to identify, respond to, and report errors and failover conditions. Customizable decision logic is used to provide more sophisticated response and reporting capabilities, even though the basic device hardware and operation is not redesigned.

Abstract: In an electronic device, its main unit has a data processing function and has a first and a second input means. The first input means is coupled to the main unit so as to be movable relative thereto between a first position in which the first input means overlaps with the main unit and a second position in which the first input means protrudes from the main unit. The first input means permits input operation in both of the first and second positions. The second input means is arranged in the main unit so as not to be movable relative thereto. The second input means is hidden by the first input means when the first input means is in the first position, and is exposed when the first input means is in the second position. The second input means permits input operation when it is exposed. The first input means is interchangeable with a third input means.

Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

Abstract: A method and system for automatically running a program stored on a medium upon detection of insertion of the medium into a drive are provided. The operating system periodically polls the drive regarding the status of the drive. After receiving a response from the drive regarding the drive's status, the operating system determines whether the drive's status has changed. If the drive's status has changed, the operating system broadcasts a message indicating the change in the drive's status. When the shell receives a message from the operating system indicating a change in the drive's status, the shell determines whether the change in the drive's status indicates that a medium has been inserted into the drive. If the change in the drive's status indicates that a medium has been inserted into the drive, the shell searches for a predefined file on the medium. The shell then runs a program stored on the medium that is specified in the predefined file.

Abstract: With respect to each of low speed and high speed input/output ports of an input/output control unit, an activation time from a time point when an end status in association with the end of transfer is responded to a time point when an activation request is received is measured and stored in a memory. When the high speed port receives an activation request from a high speed channel, the activation time in the memory measured with respect to the low speed port is read out and an input/output request for the low speed port is preferentially accepted for such an activation time. As an activation time of the low speed port, the minimum time, average time, and maximum time are obtained from the result of the measurement. Either one of the above three times is selected as an activation time so as to almost equalize busy ratios of the high speed port and low speed port.

Abstract: In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus.

Abstract: The present invention relates to a setting method for installation of plug and play device by utilizing the set-up file (INF) of a hardware driver to directly read the device ID of a new device and copy the driver file to the corresponding directory. And, deleting the device ID and all related device class of the original device. Then, while the computer being restarted the Windows system will display that the new device is found and will automatically establish the relationship between the new device and the previously installed driver through the new device ID and class in order to let the new device be operated normally.

Abstract: A media element library defines a viral configuration different from the physical configuration of media and drives actually present in the library. A plurality of host computer systems communicate with the library as if they were communicating with a conventional library having a physical configuration identical to the virtual configuration defined by the library.

Abstract: Improved techniques for controlling buses of a computer system are disclosed such that peripheral devices (and/or their associated buses) can be connected or disconnected to the computer system while the computer system is active. The peripheral devices are connected to the computer system by being inserted into a slot or other receptacle of the computer system. The peripheral devices are disconnected from the computer system by being removed from a slot or other receptacle of the computer system. The slots or receptacles typically includes connectors designed to receive peripheral devices, such as PC CARD slots, expansion bays, and the like. Given that the peripheral devices can be inserted or removed while the computer system is active is active, the computer system according to the invention permits “hot-plugging” of peripheral devices. The invention is particularly well suited for controlling PCI buses for peripheral devices connecting to a computer system by way of peripheral ports.

Abstract: With respect to each of low speed and high speed input/output ports of an input/output control unit, an activation time from a time point when an end status in association with the end of transfer is responded to a time point when an activation request is received is measured and stored in a memory. When the high speed port receives an activation request from a high speed channel, the activation time in the memory measured with respect to the low speed port is read out and an input/output request for the low speed port is preferentially accepted for such an activation time. As an activation time of the low speed port, the minimum time, average time, and maximum time are obtained from the result of the measurement. Either one of the above three times is selected as an activation time so as to almost equalize busy ratios of the high speed port and low speed port.

Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

Abstract: In a small and thin memory module for sharing data among electronic devices such as information processing apparatuses, a write prohibit state can be visually recognized. A conductive seal is attached to a predetermined position on a support member, thereby setting the memory module in the write prohibit state. The conductive seal visually indicates the write prohibit state. When the memory module is mounted in a connector section of a card-shaped holder, connector pins are electrically connected to each other via the conductive seal. Thus, a write prohibit mechanism is realized at low cost.

Abstract: A system where pieces of information equipment are connected via a network, including a memory unit and a compensating means. The memory unit stores position information that represents a physical position of each piece of information equipment. The compensating means compensates a physical distance from one piece of information equipment to another piece of information equipment based on the position information, according to a frequency of information exchange between the former and the latter.

Abstract: An image communication apparatus converts image data received through a communication line into bit image data to be reproduced as a visible image by means of using a data converting unit and a reproducing unit. The apparatus converts data from a data processing apparatus into bit image data to be reproduced as a visible image by means of using the data converting unit and the reproducing unit, so as to accomplish an efficient system as a whole.

Abstract: A method and apparatus provide a mechanism for a personal computer to allow the insertion and removal of devices to and from device ports without re-starting the operating system of the computer. Device drivers are pre-loaded during the start-up process of the computer system for devices that may be inserted in the system later. Upon detection of device insertion, a high priority thread process determines the type of device inserted and determines which pre-loaded device driver can operate the newly inserted device. The selected device driver is linked to the file system and is activated by signaling to the device driver or to the operating system of the existence of the newly inserted device. The operating system can then operate the inserted device. Upon device removal, device drivers for the removed device can be deactivated. The system also allows a docking station to have devices added or removed from device ports after the docking process has been completed.

Abstract: A real time “plug and play” installation mechanism which, instead of signaling the operating system to activate a pre-existing installation file previously shipped with the operating system file structure, energizes the operating system to retrieve the installation from a remote source. Examples of locations from which the installation resources may be retrieved include (1) an internet universal resource location (URL), (2) a dial-up bulletin board service (BBS), (3) a local area network (LAN) or wide area network (WAN) in which any required access protocols are supplied with the new device being installed, or (4) non-volatile storage (e.g. firmware) physically located on the new device being installed. The device manufacturer gives the operating system manufacturer a special installation file at the time that the operating system manufacturer distributes a new release. The special file appears to the operating system to be a conventional installation file.

Abstract: A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation—one which might affect the storage hierarchy as perceived by other devices within the system—is posted in the snoop queue of a remote snooping device. The flag remains set and is reset only when a synchronization instruction (such as the “sync” instruction supported by the PowerPC™ family of devices) is received from a local processor. The state of the flag thus provides historical information regarding architected operations which may be pending in other devices within the system after being snooped from the system bus. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered and additional system bus cycles made available for other purposes.

Abstract: A software architecture for the hot add and swap of adapters. The software architecture allows users to replace failed components, upgrade outdated components, and add new functionality, such as new network interfaces, disk interface adapters and storage, without impacting existing users. The software architecture supports the hot add and swap of off-the-shelf adapters, including those adapters that are programmable.

Abstract: A method and system for managing resources required by peripheral devices present within a computer system, the resources selected from a group of resources required for audio, video, pointing device, input, output, memory, and modem devices. A nominal selection of resources is initially associated with a peripheral device present within the computer system. Next, a minimal amount of resources required by the peripheral device to function normally within the computer system is determined, in response to associating the nominal selection of resources with the peripheral device.

Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

Abstract: A digital data transfer system transfers digital data along a path in a ring topology. The digital data transfer system comprising a host controller and a digital data transfer subsystem. The host controller generates and receiving digital data and the digital data transfer subsystem receives the digital data from the host controller and transferring the digital data to one or more devices connectable thereto, and further receives digital data from the last of the devices connectable thereto for provision to the host controller, thereby to define the ring data transfer topology. The digital data transfer subsystem comprises an upstream port, a plurality of input/output ports and a port control. The upstream port transfers digital data from an external source to the input of the first input/output port in the series and transfers digital data received from the last input/output port in the series to the host controller.

Abstract: The present invention provides a method, device and article of manufacture for efficient transfer of data items between a host processor and an external device. The host processor is coupled to external queue pointers and is used for queuing a plurality of data items and transferring the plurality of data items to the external device using an interrupt service routine unit. The external device is coupled to the host processor and is used for storing and incrementing or decrementing the external queue pointers, and processing the data items.

Abstract: In an electronic computer system in which a plurality of OSs are operated, a plurality of input-output arrangement information defined in response to each of a plurality of OSs and a correspondence table indicative of a correspondence relationship between each OS and each input-output arrangement information are created previously and stored in a control information storage means. When an input-output request is issued from an arbitrary OS, the central processing unit identifies the corresponding OS, and recognizes input-output arrangement information corresponding to the identified OS based on the correspondence table. Then, the central processing unit executes an input-output processing based on the recognized input-output arrangement information.

Abstract: A network scanner system and original reading method, which can efficiently use time and hardware resources, and can efficiently input originals consisting of a plurality of pages. When a personal computer (100) reads originals using N scanners (200) to which are connected via a LAN and each of which has an automatic document feeding facility, for example, 100 pages of originals are divided into three groups in correspondence with three scanners (200) used for reading, a re-arranging order of three bundles of divided originals set on the three scanners is input to the personal computer (100), and thereafter, a reading instruction for reading the divided originals is supplied to the three scanners (200). In accordance with this instruction, the scanners are controlled to read the set originals.

Abstract: It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started.

Abstract: A method for implementing a link level service in a computer network having a first port device and a second port device coupled by a communication link. Prior to a link incident being reported, the first port device executes a link incident record registration (LIRR) ELS message addressed to the second port device. The second port device responds to the LIRR by adding an address of the first port device to a registration list of ports registered to receive link incident reports. The second port device also responds to the LIRR by sending an accept reply message addressed to the first port device. After a link incident is detected by the second port device, the second port device generates a link incident record comprising data describing the link incident. The second port device selects an address from the registration list sends a registered link incident record ELS message addressed to the selected address.

Abstract: A system for serializing and synchronizing data stored in a tape drive emulation system utilizes a physical lock system and control data MUTEXes to assure serialization.

Abstract: Disclosed is a storage controller for interfacing between a plurality of host systems and direct access storage devices (DASDs). The storage controller includes a bridge, a first host adaptor, and a first device adaptor that are configured to communicate with a first processor. A first DASD is linked to the first device adaptor. The bridge interfaces the first processor, the first host adaptor, and the first device adaptor. The storage controller further includes a second host adaptor and a second device adaptor that are configured to communicate with a second processor. A second DASD is linked to the second device adaptor. The bridge further interfaces the second processor, the second host adaptor, and the second device adaptor. After configuration, an input/output (I/O) request from at least one of the host systems is directed to the first DASD via the first host adaptor, the first processor, and the first device adaptor.

Abstract: An SCSI quick arbitration and select protocol reduces the timing overhead associated with multiple, sequential data transfer operations, thereby significantly increasing bus efficiencies and average throughput. The conventional arbitration and selection phases are collapsed into a quick arbitrated and select phase, whereby the current SCSI target hosts an arbitration proceeding without the bus transitioning to a bus free phase. The quick arbitrate and select phase is invoked by a current target device by broadcasting a QAS message code during the message-in phase of the current process. QAS capable devices snoop the bus, recognize the QAS message code and enter a quick arbitrate and select phase. A fairness algorithm grants control of the bus to a participating QAS target with the next lowest SCSI ID from that of the current QAS target.

Abstract: A peripheral system includes (a) a peripheral device having peripheral memory located thereon, (b) at least one input/output (I/O) card communicating with the peripheral device, and (c) a means for managing the peripheral memory between the peripheral device and the at least one I/O card. In a preferred embodiment, the means for managing the peripheral memory includes (a) a means for determining, during normal operation, an optimum amount of peripheral memory for allocating to each I/O card, and (b) a means for allocating, during normal operation, the optimum amount of peripheral memory to each I/O card. A preferred method for managing memory, between a peripheral device, having peripheral memory thereon, and at least one input/output (I/O) card, includes (a) determining, during normal operation, an optimum amount of peripheral memory for allocating to each I/O card, and (b) allocating, during normal operation, the optimum amount of peripheral memory to each I/O card.