Access Locking Patents (Class 710/200)
  • Patent number: 8224799
    Abstract: A method of providing lock-based access to nodes in a concurrent linked list includes providing a plurality of striped lock objects. Each striped lock object is configured to lock at least one of the nodes in the concurrent linked list. An index is computed based on a value stored in a first node to be accessed in the concurrent linked list. A first one of the striped lock objects is identified based on the computed index. The first striped lock object is acquired, thereby locking and providing protected access to the first node.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: July 17, 2012
    Assignee: Microsoft Corporation
    Inventors: Chunyan Song, Joshua Phillips, John Duffy, Tim Harris, Stephen H. Toub, Boby George
  • Patent number: 8225012
    Abstract: A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventor: Thomas A. Piazza
  • Patent number: 8219712
    Abstract: A network interface device for providing an interface between a network and a data processing device, the network interface device having: a plurality of resources of different types for supporting the interface, and a bus interface for interfacing with the data processing device by means of a bus over which data can be sent by addressing to a address on the bus, the network interface device being arranged so that each resource may be addressed by a respective address on the bus.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: July 10, 2012
    Assignee: Solarflare Communications, Inc.
    Inventors: David Riddoch, Steven Pope
  • Patent number: 8219732
    Abstract: A method for managing states by a Media Access Control (MAC) layer in a wireless network is disclosed. The method includes determining next occurable physical interrupts for each of the states; configuring a link of the states according to the determination result; transitioning to a state to be linked next if a physical interrupt occurs in each state; and transitioning to an initial state if an timer interrupt occurs in each state. The MAC layer transitions to the initial state if a physical interrupt occurs in a last state among the linked states. The physical interrupt occurs in association with a physical event, and the timer interrupt occurs in association with a timer event.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: July 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-Ho Jang
  • Patent number: 8209448
    Abstract: A data processing apparatus includes an arithmetic circuit and a peripheral device protection circuit that controls access of the arithmetic circuit to the peripheral devices. The peripheral device protection circuit has a first protection preset value and a second protection preset value set as a protection level higher than that of the first protection preset value. The peripheral device protection circuit includes: a setting selection circuit that generates access permission/denial information by referring to the first protection preset value and the second protection preset value when the arithmetic circuit operates at a first operation authority level, or by referring to the second protection preset value when the arithmetic circuit operates at the second operation authority level. An access protection circuit that determines permission/denial of access to the peripheral devices based on access information output from the arithmetic circuit and the access permission/denial information.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: June 26, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Junichi Sato, Hitoshi Suzuki
  • Patent number: 8209689
    Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: June 26, 2012
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Shay Gueron, Gad Sheaffer
  • Publication number: 20120151110
    Abstract: In one embodiment, a non-transitory processor-readable medium stores code representing instructions that when executed cause a processor to obtain a first mutual exclusion object. The first mutual exclusion object can be a write mutual exclusion object associated with a shared resource. The code can further represent instructions that when executed cause the processor to obtain a second mutual exclusion object associated with an object manager module and define a read event object with a name conforming to a predetermined format. The code can further represent instructions that when executed cause the processor to release the second mutual exclusion object, release the first mutual exclusion object, read at least a portion of the shared resource, obtain the second mutual exclusion object, destroy the read event object and release the second mutual exclusion object.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 14, 2012
    Inventors: Richard Pointon, Richard James Somerfield
  • Patent number: 8195859
    Abstract: A multiprocessor server system executes a plurality of multiprocessor or single-processor operating systems each using a plurality of storage adapters and a plurality of network adapters. Each operating system maintains load information about all its processors and shares the information with other operating systems. Upon changes in the processor load of the operating systems, processors are dynamically reassigned among operating systems to improve performance if the maximum load of the storage adapters and network adapters of the reassignment target operating system is not already reached. Processor reassignment includes shutting down and restarting dynamically operating systems to allow the reassignment of the processors used by single-processor operating systems. Furthermore, the process scheduler of multi-processor operating systems keeps some processors idle under light processor load conditions in order to allow the immediate reassignment of processors to heavily loaded operating systems.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: June 5, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Damien Le Moal
  • Patent number: 8195802
    Abstract: A method of processing allocation and deallocation requests in a computing environment. The method forms an Allocation Queue of requests for resource allocations, a Deallocation Queue of requests for resource deallocations, a Pending Queue of requests for resource allocation which cannot be met immediately, and a Cancel Queue of requests to cancel an earlier request already waiting in either the Pending Queue or the Allocation Queue. A cycle of servicing the Allocation Queue, the Deallocation Queue, the Pending Queue, and the Cancel Queue in a chronological sequence is carried out. In the cycle: the Deallocation Queue is serviced first, the Cancel Queue is serviced after the Deallocation Queue is serviced until the Cancel Queue is empty, the Pending Queue is serviced after the Cancel Queue is serviced, and the Allocation Queue Queue is serviced after the Pending Queue is serviced.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventor: Rajendra Kumar Bera
  • Patent number: 8176022
    Abstract: The present invention discloses a Locking Protocol using Dynamic Locks and Dynamic Shared Memory which provides a method whereby a designated critical section monitors object status through employment of counters attached to the object=s definition that will increment and decrement during reading and writing.
    Type: Grant
    Filed: August 26, 2006
    Date of Patent: May 8, 2012
    Inventor: Radames Garcia
  • Patent number: 8176283
    Abstract: A data object is stored in a hosted storage system and includes an access control list specifying access permissions for data object stored in the hosted storage system. The hosted storage system provides hosted storage to a plurality of clients that are coupled to the hosted storage system. A request to store a second data object is received. The request includes an indicator that the first data object stored in the hosted storage system should be used as an access control list for the second data object. The second data object is stored in the hosted storage system. The first data object is assigned as an access control list for the second data object stored in the hosted storage system.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: May 8, 2012
    Assignee: Google Inc.
    Inventors: David R. Hanson, Erkki Ville Juhani Aikas
  • Patent number: 8166256
    Abstract: A method, system, and computer usable program product for using a dual mode reader writer lock. A contention condition is detected in the use of a lock in a data processing system, the lock being used for managing read and write access to a resource in the data processing system. A determination of the data structure used for implementing the lock is made. If the data structure is a data structure of a reader writer lock (RWL), the data structure is transitioned to a second data structure suitable for implementing the DML. A determination is made whether the DML has been expanded. If the DML is not expanded, the DML is expanded such that the data structure includes an original lock and a set of expanded locks. The original lock and each expanded lock in the set of expanded locks forms an element of the DML.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: April 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bruce Mealey, James Bernard Moody
  • Patent number: 8161481
    Abstract: An operating system for a computing device includes a scheduler incorporating an algorithm for ordering the running of threads of execution having different priorities. The operating system is also arranged to provide a list of threads which are scheduled to run on the device, ordered by priority. At least one locking mechanism for docking access to a resource of the device from all threads except for a thread that holds the locking mechanism is also provided, and the operating system arranges for a scheduled thread which is docked from running because the resource it requires is locked to cause the thread which holds the locking mechanism to run.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: April 17, 2012
    Assignee: Nokia Corporation
    Inventor: Dennis May
  • Publication number: 20120089760
    Abstract: In one embodiment, the present invention includes a method for accessing a shared memory associated with a reader-writer lock according to a first concurrency mode, dynamically changing from the first concurrency mode to a second concurrency mode, and accessing the shared memory according to the second concurrency mode. In this way, concurrency modes can be adaptively changed based on system conditions. Other embodiments are described and claimed.
    Type: Application
    Filed: December 14, 2011
    Publication date: April 12, 2012
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai
  • Patent number: 8156275
    Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: April 10, 2012
    Assignee: Apple Inc.
    Inventors: Josh P. de Cesare, Ruchi Wadhawan, Michael J. Smith, Puneet Kumar, Bernard J. Semeria
  • Patent number: 8149450
    Abstract: In a document management system according to an embodiment of the present invention, in order to prevent a leakage of information, in a case where a copy of a document is transferred to a media, a deletion processing with respect to the document is disabled. Then, in a case where it is confirmed that document leakage is not performed from the media, the deletion processing with respect to the document from the media is canceled.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: April 3, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsuo Kimura
  • Patent number: 8145816
    Abstract: A method and system of deadlock free bus protection of memory and I/O resources during secure execution. A bus cycle initiates entry of a bus agent into a secure execution mode. The chipset records an identifier of the secure mode processor. Thereafter, the chipset intercedes if another bus agent attempts a security sensitive bus cycle before the secure mode processor exits the secure mode.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Stephen A. Fischer, Douglas Raymond Moran, James A. Sutton, II
  • Patent number: 8145817
    Abstract: A scalable locking system is described herein that allows processors to access shared data with reduced cache contention to increase parallelism and scalability. The system provides a reader/writer lock implementation that uses randomization and spends extra space to spread possible contention over multiple cache lines. The system avoids updates to a single shared location in acquiring/releasing a read lock by spreading the lock count over multiple sub-counts in multiple cache lines, and hashing thread identifiers to those cache lines. Carefully crafted invariants allow the use of partially lock-free code in the common path of acquisition and release of a read lock. A careful protocol allows the system to reuse space allocated for a read lock for subsequent locking to avoid frequent reallocating of read lock data structures. The system also provides fairness for write-locking threads and uses object pooling techniques to make reduce costs associated with the lock data structures.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: March 27, 2012
    Assignee: Microsoft Corporation
    Inventor: David L. Detlefs
  • Patent number: 8141086
    Abstract: A method and system for validating a scan of a chain in a multithreaded environment. A modification counter and an anchor address are atomically copied from the chain's header into a first variable (browse counter) and second variable, respectively. The second variable is set to a next address stored in a current element of the chain. The next address references a next element of the chain. The browse counter is incremented. If the browse counter is greater than a current value of the modification counter (M.Counter) and if the second variable includes a valid address, then the scan is valid up to the current element, the scan continues with the next element as the current element, and the process repeats starting with setting the second variable to the next address. Otherwise, if the browse counter is less than or equal to M.Counter, then the scan is invalid.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Martin William John Cocks, Felicity Jane Merrison
  • Patent number: 8135999
    Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 13, 2012
    Assignee: Intel Corporation
    Inventors: Warren Morrow, Pete Vogt, Dennis Brzezinski
  • Patent number: 8135893
    Abstract: Systems, apparatuses and methods for timing access to a shared communications bus by a plurality of devices. Each of a plurality of nodes is successively provided an opportunity to gain access to a shared bus according to a time slot allocation referenced from a time reference. The successive time slot allocation occurs until one of the nodes has a message to send via the shared bus. The node that has the message to send transmits a frame onto the bus. A new time reference is established at each of the nodes based on an indication provided by the transmitted frame, whereby each of the nodes can then be afforded a new opportunity to gain access to the shared bus according to the time slot allocation referenced from the new time reference.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: March 13, 2012
    Assignee: Honeywell International, Inc.
    Inventor: Ralph C. Brindle
  • Patent number: 8136112
    Abstract: Thread synchronization methods and apparatus for managed run-time environments are disclosed.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: March 13, 2012
    Assignee: Intel Corporation
    Inventors: Tatiana Shpeisman, Ali-Reza Adl-Tabatabai, Brian Murphy
  • Publication number: 20120060160
    Abstract: Systems and methods of protecting a shared resource in a multi-threaded execution environment in which threads are permitted to transfer control between different software components, for any of which a disclaimable lock having a plurality of orderable locks can be identified. Back out activity can be tracked among a plurality of threads with respect to the disclaimable lock and the shared resource, and reclamation activity among the plurality of threads may be ordered with respect to the disclaimable lock and the shared resource.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kirk J. Krauss
  • Publication number: 20120059963
    Abstract: System, method, computer program product embodiments and combinations and sub-combinations thereof for adaptive locking of retained resources in a distributed database processing environment are provided. An embodiment includes identifying a locking priority for at least a portion of a buffer pool, determining lock requests based upon the identified locking priority, and granting locks for the lock requests.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 8, 2012
    Applicant: Sybase, Inc.
    Inventors: Kantikiran Krishna Pasupuleti, Anusha Sivananainthaperumal, Jihong Jin
  • Publication number: 20120054394
    Abstract: Access by multiple threads to a common resource can be controlled using a bias-lock having a single owner thread selected from among the plurality of threads. The bias-lock includes an n-process lock for which non-owner processes compete and a 2-process lock for which the owner and non-owner holder of the n-process lock compete. The owner of the bias-lock can be switched to one of the non-owner threads without suspending the owner thread. An asymmetric lock can be used to eliminate the need for the 2-process lock. Bias-locks can further be extended to provide read/write bias locking mechanisms.
    Type: Application
    Filed: September 1, 2010
    Publication date: March 1, 2012
    Applicant: ALCATEL-LUCENT USA INC.
    Inventors: Kedar S. Namjoshi, Nalini Vasudevan
  • Patent number: 8127062
    Abstract: In one embodiment, a solution is provided wherein a lock client sends lock requests to a lock manager upon receipt of an input/output (I/O) and receives back a lock grant. At some point later, the lock client may send a lock release. The lock manager, upon receipt of a lock release from a lock client, remove a first lock request corresponding to the lock release from a lock grant queue corresponding to the lock manager. Then, for each dependency queue lock request in a dependency queue corresponding to the first lock request, the lock manager may determine whether the dependency queue lock request conflicts with a second lock request in the lock grant queue, and then may process the dependency queue lock request according to whether the dependency queue lock requires conflicts with a second lock request in the lock grant queue.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: February 28, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Maurilio Cometto, Arindam Paul, Varagur V. Chandrasekaran
  • Patent number: 8127161
    Abstract: An access stop control apparatus is provided in a resource control apparatus so that reception of access from a master apparatus is temporarily stopped during changing of a clock frequency and the clock frequency is changed at safe timing. Thereby, the operation of the master apparatus does not need to be stopped during changing of the clock frequency and a period for which access to a resource is stopped can be suppressed. Therefore, execution of an application requiring real-timeness is not affected.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: February 28, 2012
    Assignee: Panasonic Corporation
    Inventor: Daisuke Murakami
  • Patent number: 8117616
    Abstract: A deadlock prevention mode indicator is provided, wherein the deadlock prevention mode indicator is a lock that can be held in a shared mode or in an exclusive mode by one or more of a plurality of threads, and wherein the plurality of threads can cause deadlocks while acquiring a plurality of data locks. An execution of the plurality of threads is serialized by allowing a data lock to be acquired by a thread in response to the thread holding the deadlock prevention mode indicator, wherein serializing the plurality of threads avoids any deadlock from occurring.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventor: Russell Lee Lewis
  • Patent number: 8108586
    Abstract: To provide a multi-core LSI capable of improving the stability of operation. A multi-core LSI comprises a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bus and the second shared bus, for arbitrating an access to the module (s) by the CPUs, and a system controller that monitors whether or not a response signal to an access request signal of the CPUs is output from module to be accessed, wherein the system controller outputs a pseudo response signal to the first shared bus via the shared bus controller to terminate the access by the CPU while accessing if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: January 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Mamoru Sakugawa
  • Patent number: 8103638
    Abstract: Methods, systems, and computer-readable media are disclosed for partitioning contended synchronization objects. A particular method determines a contention-free value of a performance metric associated with a synchronization object of a data structure. A contended value of the performance metric is measured, and the synchronization object is partitioned when the contended value of the performance metric exceeds a multiple of the contention-free value of the performance metric.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: January 24, 2012
    Assignee: Microsoft Corporation
    Inventors: Fabricio Voznika, Alexandre Verbitski, Pravin Mittal
  • Patent number: 8099538
    Abstract: In one embodiment, the present invention includes a method for accessing a shared memory associated with a reader-writer lock according to a first concurrency mode, dynamically changing from the first concurrency mode to a second concurrency mode, and accessing the shared memory according to the second concurrency mode. In this way, concurrency modes can be adaptively changed based on system conditions. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: January 17, 2012
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai
  • Patent number: 8095628
    Abstract: A computer implemented method and apparatus for rebooting a host having a plurality of network interfaces. A server reboots the host by stopping an NFS server process on the host. The server sends at least one consolidated notification to a plurality of clients identified in a consolidated notification table, wherein the consolidated notification comprises at least two addresses of network interfaces of the host. The server determines that an acknowledgement is received from each of the plurality of clients. The server halts resending of consolidated notifications, responsive to determining that an acknowledgement is received from the each of the plurality of clients.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: January 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Adekunle Bello, Radhika Chirra, Aruna Yedavilli
  • Patent number: 8090892
    Abstract: A device receives a first request from a requesting device for first information that is stored at contiguous address locations beginning at a first address. A plurality of spawned requests are generated that each request a different portion of the first information. A table location is allocated to each one of the plurality of requests, wherein the relative location of each allocated table location is indicative of an order that the information from each spawned request is to be returned to the requesting device relative to the information from each other spawned request.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: January 3, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Thang Q. Nguyen
  • Publication number: 20110320661
    Abstract: A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Lisa C. Heller
  • Patent number: 8086581
    Abstract: A method and a distributed locking system for the management of lock resources in a distributed files system having several lock managers, each managing lock resources in its respective domain. Each lock manager maintains a registry lock file that comprises of a list of all locked files and a list of lock requests. The registry lock files of all lock managers in the distributed locking system are saved in a central database. Furthermore, the system enables concurrent locking operations of different file sharing protocols on the same file system resources.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: December 27, 2011
    Assignee: Dell Global B.V. - Singapore Branch
    Inventors: Ofer Oshri, Nadav Danieli, Menny Hamburger
  • Patent number: 8082379
    Abstract: In one embodiment, a system for managing semantic locks and semantic lock requests for a resource is provided. Access to the resource is controlled such that compatible lock requests can access the resource and incompatible lock requests are queued.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: December 20, 2011
    Assignee: EMC Corporation
    Inventors: Neal T. Fachan, Aaron J. Passey
  • Patent number: 8078764
    Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: December 13, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Jun Okitsu, Yoshiko Yasuda, Takashige Baba, Keitaro Uehara, Yuji Tsushima
  • Patent number: 8078591
    Abstract: Methods, systems and software applications are provided for real time data processing. In one implementation, a method is provided for locking data objects in a computer system. The method may comprise determining whether a number of lock objects to be locked is less than or equal to a maximum number of lock objects; creating, when the number is less than or equal to the maximum, one or more lock objects comprising names and values for key fields; and creating, when the number is greater than the maximum, one or more lock objects by applying a heuristic process such that the lock objects include wild cards for key fields.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: December 13, 2011
    Assignee: SAP AG
    Inventor: Roman Rapp
  • Patent number: 8078781
    Abstract: A device having priority update capabilities and a method for updating priorities, the method includes: receiving a request to update to a requested priority, priorities of transaction requests stored within a first sequence of pipeline stages that precede an arbiter; updating a priority level of a transaction request stored in the first sequence to the requested priority if the transaction request is priority upgradeable and if the requested priority is higher that a current priority of the transaction request; and arbitrating between transaction requests in response to priority attributes associated with the transaction requests.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: December 13, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ori Goren, Yaron Netanel, Aviel Livay, Gil Moran, Yossy Neeman
  • Publication number: 20110296069
    Abstract: A replicated finite state machine lock service facilitates resource sharing in a distributed system. A lock request from a client identifies a resource and a lock-mode, and requests a leaseless lock on the resource. The service uses client instance identifiers to categorize requests as duplicate, stale, abandoned, or actionable. A lock may be abandoned when a client holding the lock goes down. After a per-client abandonment timer expires, the lock service may treat any exclusive lock granted to the client as abandoned, and treat any non-exclusive lock granted to the client as unlocked. The service tries to notify a lock-holding client if another client requests the same lock, and treats the lock as abandoned if the notification attempt fails. An abandoned read lock is granted to a different client on request. An abandoned write lock is granted or refused depending on whether the requesting client accepts abandoned write locks.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: MICROSOFT CORPORATION
    Inventors: Mihail Gavril Tarta, Gopala Krishna R. Kakivaya
  • Patent number: 8065459
    Abstract: A plurality of data processing tasks with processing elements (10) that contend for a resource (18). Execution of each task comprising executing a series of instructions. During execution indications are measured of the speed of progress of executing the instructions for respective ones of the tasks. Requests to access the resource (18) for different ones of the tasks are arbitrated, a priority for judging arbitration being assigned to each task based on the measured indication of the speed of progress of the task. At least over a part of a range of possible speed of progress values increasingly higher priority is assigned in case of increasingly lower indication of the speed of progress.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 22, 2011
    Assignee: NXP B.V.
    Inventor: Marco J. G. Bekooij
  • Patent number: 8060642
    Abstract: Techniques for host to host transfer of media and the use of persistent reservation to protect media during host to host transfer is disclosed. Exemplary embodiments may be realized as methods and systems for transferring a sequential media loaded in a drive from a first host to a second host without physically unloading the media. The first host may have a persistent reservation or non-persistent reservation of the drive. Likewise, the second host may have a persistent reservation or non-persistent reservation of the drive. Logical unload, logical load and preemption commands are utilized as is error recovery from a failed reservation.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: November 15, 2011
    Assignee: Symantec Corporation
    Inventors: Raymond Wesley Gilson, Adonijah Park
  • Patent number: 8060880
    Abstract: Locks which protect data structures used within atomic sections of concurrent programs are inferred from atomic sections and acquired in a manner to avoid deadlock. Locks may be inferred by expression correspondence using a backward inter-procedural analysis of an atomic section. Locks may be sorted according to a total order and acquired early in an atomic section to prevent deadlock. Multiple granularity of locks are determined and employed. Fine grained locks may be inferred and acquired to reduce contention. Coarse grained locks may be determined and substituted for fine grained locks when necessary for unbounded locations or to reduce the number of finer grained locks.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: November 15, 2011
    Assignee: Microsoft Corporation
    Inventors: Sigmund Isy Cherem, Trishul Amit Madhukar Chilimbi, Sumit Gulwani
  • Patent number: 8055827
    Abstract: In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to receiving a first interrupt message communicating a first interrupt that is targeted at a host in the system. The second interrupt controller is configured to signal the processor for an interrupt in response to receiving a second interrupt message communicating a second interrupt that is targeted at a guest that is controlled by the host and that is executable on the processor.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: November 8, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin C. Serebrin, Donald W. McCauley
  • Patent number: 8051424
    Abstract: A computer system receives a data collection and creates an administration table. A main process locks the data collection against unauthorized access using an association, in a lock table, between it and a lock identifier required for data collection access by processes. The main process divides the data collection into subgroups. The lock identifier and each subgroup are forwarded to one of the processes; the subgroups being parallel processed by recipient processes that access and update the data collection using the lock identifier, and set the lock identifier and update the administration table regarding the processing done by the recipient process, the administration table being common to all of the subgroups. After the recipient processes, the data collection is unlocked by the main process by removing the association between the data collection and the lock identifier in the lock table.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: November 1, 2011
    Assignee: SAP AG
    Inventors: Joerg Steinmann, Karthikeyan Ayyadurai, Himanshu Kacker, Mohan Marar, Jayanta M. Boruah, Wolfgang Gentes
  • Patent number: 8044880
    Abstract: A theft preventing system easy to operate and capable of implementing countermeasures to theft of a projection type image display device is provided. The projection type image display device is equipped with a unit for detecting a used condition of the device and a unit for registering a used condition of the device. By further equipping the device with a unit for inhibiting normal operations of the device in its used condition other than the registered condition, a simple and easy-to-operate unauthorized use preventing system can be realized and thus protection of the device against theft can be attained.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: October 25, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuro Nakamura, Masaaki Takatsuji, Atsushi Maruyama
  • Patent number: 8042122
    Abstract: A hybrid resource manager is provided for use in a computing environment. The hybrid resource manager serves as the single resource manager that cooperates with an operating system to manage each of the individual device drivers associated with the various functions of a multifunction hardware device. In one example the hybrid resource manager implements a consistent management and policy framework to prevent conflicts from arising when multiple functions are simultaneously requested by various applications.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: October 18, 2011
    Assignee: Microsoft Corporation
    Inventors: Shivaram H. Mysore, Dan Sledz
  • Publication number: 20110246694
    Abstract: A multi-processor system of the present invention comprises a plurality of processors each configured to lock a shared resource and process a task; each of the processors including a lock wait information storage unit for storing lock wait information indicating whether or not the processor is waiting for acquirement of a lock of the shared resource; and a lock acquirement priority information storage unit for storing lock acquirement priority information indicating a priority according to which the shared resource is acquired; and each of the processors being configured to acquire the lock of the shared resource based on the lock wait information and the lock acquirement priority information.
    Type: Application
    Filed: June 10, 2011
    Publication date: October 6, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Naoya Ichinose
  • Patent number: 8032677
    Abstract: An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Limited
    Inventors: Takeshi Sumou, Katsumi Imamura, Hideyo Fukunaga
  • Patent number: 8027925
    Abstract: The present invention comprises a method and apparatus for enforcing software licenses for resource libraries such as an application program interface (API), a toolkit, a framework, a runtime library, a dynamic link library (DLL), an applet (e.g. a Java or ActiveX applet), or any other reusable resource. The present invention allows the resource library to be selectively used only by authorized end user software programs. The present invention can be used to enforce a “per-program” licensing scheme for a resource library whereby the resource library is licensed only for use with particular software programs. In one embodiment, a license text string and a corresponding license key are embedded in a program that has been licensed to use a resource library. The license text string and the license key are supplied, for example, by a resource library vendor to a program developer who wants to use the resource library with an end user program being developed.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: September 27, 2011
    Assignee: Apple Inc.
    Inventors: Blaine Garst, Bertrand Serlet