Abstract: A spinlock circuit connected to one or more first processors through one or more broadside interfaces. The spinlock circuit is configured to receive a plurality of requests for use of a computing resource from one or more first processors, and reply to each of the plurality of requests within a single clock cycle of the one or more first processors. The spinlock circuit can reply to each of the plurality of requests within a single clock cycle of the one or more first processors by alternately assigning the computing resource to a requesting processor from among the one or more first processors or indicating to the requesting processor from among the one or more first processors that the computing resource is not available.

Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.

Abstract: Embodiments of the disclosure provide a database processing method, a database processing apparatus, and an electronic device. The database processing method can include: providing a plurality of transactions to a transaction queue, wherein each transaction of the plurality of transactions includes an encapsulated write request for writing data into a database; generating auto-increment identifiers (IDs) for data rows of the data corresponding to the plurality of transactions according to an order of the transactions in the transaction queue; and writing the data into the database according to the auto-increment IDs assigned to the data rows of the data in the transaction.

Abstract: A serial communications bus system comprising a plurality of end users arranged to transmit data on a common data bus, each end user provided with a bus arbiter, physically separate from the respective end user, configured to define, for that end user, a cycle of transmission enable intervals whereby the end user may transmit data on the data bus and transmission disable intervals whereby the end user may not transmit data on the data bus.

Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.

Abstract: Determining priority of conflicting resource requests using dynamic logic includes analyzing current computer resource availability using cognitive capabilities and determining priority for the computer resources. The method may further include continuously assessing impact of the priority determinations, dynamically configuring the defined logic based on the assessment and modifying the defined logic using machine learning of effectiveness of the priority determinations. The method may also include predicting an urgency of the received computer resources requests and determining a pattern computer resource requests by users.

Abstract: The present disclosure involves systems, software, and computer implemented methods for resource allocation and management. One example method includes receiving a request, including a first application priority, to run a task for an application. At least one second application priority is identified. A maximum number of parallel tasks per application priority is determined. Application priority weights are assigned to the first application priority and the second application priorities. Application priority divisors are determined, for the first application priority and the second application priorities, based on a respective application priority weight and a number of currently running applications of a respective application priority. A number of parallel tasks for the first application and other applications are determined based on the maximum number of allowable parallel tasks per application, an overall divisor, and a respective application priority weight.

Abstract: A storage control system receives an I/O request from a client for accessing storage resources that are logically divided into device groups, and determines a resource token request value associated with the I/O request and a target device group to which the I/O request is directed. The storage control system determines a number of allowed resource tokens to allocate to the client as a function of (i) the resource token request value, (ii) a sum total of resource tokens requested by other clients for accessing the target device group, and (iii) a total amount of resource tokens currently allocated to the target device group to which the I/O request is directed. The storage control system sends the determined number of allowed resource tokens to the client to thereby enable the client to limit a number of inflight I/O requests that the client issues to the storage control system.

Abstract: A method for configuring hardware within a computing system. The method includes one or more computer processors identifying information respectively associated with a plurality of hardware resources within a portion of a computing system. The method further includes determining whether a set of memory modules of differing performance ratings are operatively coupled to a shared bus fabric. The method further includes responding to determining that the set of memory modules of differing performance ratings is operatively coupled to the shared bus fabric by configuring a subsystem to selectively access respective groups of memory modules within the set of memory modules based on a performance rating corresponding to a respective group of memory modules.

Abstract: An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period.

Abstract: An application processor includes a system bus, as well as a host processor, a voice trigger system, and an audio subsystem that are electrically connected to the system bus. The voice trigger system performs a voice trigger operation and issues a trigger event based on a trigger input signal that is provided through a trigger interface. The audio subsystem processes audio streams that are replayed or recorded through an audio interface, and receives an interrupt signal through the audio interface while an audio replay operation is performed through the audio interface.

Abstract: An I/O processing system includes reception of a request to perform an I/O operation from a user-mode application, providing of the request to a storage device, scheduling of an operating system deferred procedure call to determine whether the storage device has completed the I/O operation, execution of the scheduled deferred procedure call to determine that the storage device has completed the I/O operation, and transmission of a return corresponding to the completed I/O operation to the user-mode application.

Abstract: An application processor includes a system bus, a host processor, a voice trigger system and an audio subsystem that are electrically connected to the system bus. The voice trigger system performs a voice trigger operation and issues a trigger event based on a trigger input signal that is provided through a trigger interface. The audio subsystem processes audio streams through an audio interface of the audio subsystem.

Abstract: An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period.

Abstract: A method that incorporates teachings of the present disclosure may include, for example, receiving at a media resource center a first pairing key from a first mobile device server and enabling the first mobile device to access at least one media device based on the first pairing key, where the at least one media device is operably coupled with the media resource center, where the first mobile devices provides media services by executing a web server application that utilizes the at least one media device, and where the first mobile device communicates with a second mobile device server to provide the media services. Other embodiments are disclosed.

Abstract: A processing circuit is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag. A trace circuit is provided for generating trace data elements indicative of operations performed by the processing circuit. When the processing circuit 4 processes at least one selected instruction, then the trace circuit generates a trace data element including a traced condition value indicating at least the subset of condition flags required to determine the outcome of the conditional instruction. A corresponding diagnostic apparatus uses the traced condition value to determine a processing outcome of the at least one conditional instruction.

Abstract: Techniques for provision of on-demand utility services utilizing a yield management framework are disclosed. For example, in one illustrative aspect of the invention, a system for managing one or more computing resources associated with a computing center comprises: (i) a resource management subsystem for managing the one or more computing resources associated with the computing center, wherein the computing center is able to provide one or more computing services in response to one or more customer demands; and (ii) a yield management subsystem coupled to the resource management subsystem, wherein the yield management subsystem optimizes provision of the one or more computing services in accordance with the resource management subsystem and the one or more computing resources.

Abstract: A portable media player communicates with a host computer for enabling a user of the player to manage media distribution using the control software of the host computer. The host computer can send a GUI that is displayed on the otherwise “dumb” player, and the user can view the GUI and press a single button to command the control software to download a media title to the player. The host computer can periodically poll the player to determine its status.

Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.

Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.

Abstract: Memory-based semaphores are described that are useful for synchronizing processes between different processing engines. In one example, operations include executing a first process at a first processing engine, the executing including updating a memory register, sending a signal from the first processing engine to a second processing engine that the memory register has been updated, the signal including a memory register address to identify the updated memory register inline data and a dataword, fetching data from the memory register by the second processing engine, comparing the fetched data to the received dataword, and conditionally executing a next command of a second process at the second processing engine based on the comparison.

Abstract: A First Come First Server (FCFS) arbiter that receives a request to utilize a shared resource from a plurality of devices and in response generates a grant value indicating if the request is granted. The FCFS arbiter includes a circuit and a storage device. The circuit receives a first request and a grant enable during a first clock cycle and outputs a grant value. The grant enable is received from a shared resource. The grant value communicated to the source of the first request. The storage device includes a plurality of request buckets. The first request is stored in a first request bucket when the first request is not granted during the first clock cycle and is moved from the first request bucket to a second request bucket when the first request is not granted during a second clock cycle. A granted request is cleared from all request buckets.

Abstract: A method that incorporates teachings of the present disclosure may include, for example, receiving at a media resource center a first pairing key from a first mobile device server and enabling the first mobile device to access at least one media device based on the first pairing key, where the at least one media device is operably coupled with the media resource center, where the first mobile devices provides media services by executing a web server application that utilizes the at least one media device, and where the first mobile device communicates with a second mobile device server to provide the media services. Other embodiments are disclosed.

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

Abstract: An Artificial Intelligence (AI) interface and engine is described that enables the monitoring and analysis of vehicle information to determine if the vehicle has had at least one of hardware and software maliciously changed, added, or removed. The AI interface may determine the presence of the maliciously changed, added, or removed hardware and/or software such as by receiving an emergency condition from at least one sensor that is in disagreement with another sensor.

Abstract: A motor vehicle has a master bus device that is designed to use a vehicle communication bus of the motor vehicle to exchange messages with slave bus devices. A transmission device of the master bus device cyclically exchanges the messages with the slave bus devices on the basis of a schedule For making efficient use of the vehicle communication bus by the schedule-controlled master bus device, the transmission device is designed to receive a diagnosis request signal via a data input that is different than the bus port of the master bus device and to take the diagnosis request signal as a basis for interrupting the cyclic processing of the schedule and to exchange at least one special message that is different than the messages stipulated in the schedule with at least one of the slave bus devices and then to continue the processing of the schedule.

Abstract: A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device.

Abstract: A method, system, apparatus, and article of manufacture for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance with one embodiment of the present invention, a first process initially-requests an action to be performed by a second process. A reservation is set at a cacheable memory location via a store operation. The first process reads the cacheable memory location via a load operation to determine whether or not the requested action has been completed by the second process. The load operation of the first process is stalled until the reservation on the cacheable memory location is lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.

Abstract: A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.

Abstract: Apparatus having corresponding methods and computer-readable media comprise: a memory having a plurality of ports; a plurality of processors, wherein each processor is configured to access a respective port of the memory, and wherein each processor is configured to wait responsive to assertion of a respective wait signal; and an arbiter configured to assert the wait signals responsive to memory enable signals asserted by the processors such that the memory is accessed by only one of the processors at a time.

Abstract: A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have predetermined bit widths. To provide the memory controller with adjustable port widths, a mapping interface may be provided that interfaces between master processing modules and the memory controller. The mapping interface may allocate port resources such as read data ports and write data ports of the memory controller to each master processing module. The mapping interface may assign a desirable number of read data ports and write data ports to each master to accommodate the requirements of that master. The mapping interface may assign a command port to each master that receives memory access requests from that master. The mapping interface may convey write acknowledgements in response to fulfilling write access requests.

Abstract: A system and method for allocating and/or utilizing spare computing system (e.g., personal computing system) resources. Various aspects of the present invention may, for example and without limitation, provide a system and/or method that communicates incentive information with computing systems, and/or representatives thereof, regarding the allocation of computing resources for utilization by other computing systems and/or incentives that may be associated with such utilization. Various aspects of the present invention may, for example, allocate one or more resources of a computing system for utilization by another computing system based, at least in part, on such communicated incentive information.

Abstract: An arbiter configured to selectively grant access to a shared bus to a plurality of requestors. The arbiter includes a plurality of request shapers each configured to receive a request signal corresponding to a request, from a respective one of the plurality of requestors, to access the shared bus, a base priority signal indicating a base priority level of the respective one of the plurality of requestors, and a delta period signal indicating a counter value threshold. The counter value threshold corresponds to a threshold amount of time, and the counter value threshold is different for each of the plurality of requestors. Each of the plurality of request shapes is configured to separately output the request signal and a priority signal indicating a priority level of the request based on the base priority level, the counter value threshold, and a counter value.

Abstract: In some embodiments, a processor-implemented method for disabling at least one text application on a mobile device may comprise: processing an image captured in a vehicle by a mobile device to identify a seat belt in the image; determining a slope of the seat belt relative to a horizon, wherein the horizon is determined using information pertaining to a position and an orientation of the mobile device relative to a frame of reference at a time when the image was captured; determining a speed of the mobile device; and disabling at least one text application on a mobile device based, on the slope of the seat belt and the speed of the mobile device.

Abstract: The present invention discloses an arbitration mechanism for controlling access of a plurality of nodes external to a shared resource, to which accesses by the number of nodes must be restricted, is applicable to any shared source in a computer or computer-controlled system. The present design delivers the following advantageous features. It provides localized arbitration to obtain resource access and localized self-management of resource mastery; eliminates resource seizure locally; it allows equal access to the share resource, encapsulate all four above features with the same circuit/protocol.

Abstract: A signal transfer circuit comprising a control signal transfer unit configured to output an access request output signal and a memory address output signal to the arbiter after timings of the access request input signal of the access request and the memory address input signal input from the bus master have been adjusted, and output an access permission output signal, and a data signal transfer unit configured to output each data output signal to the corresponding bus master or the arbiter after a timing of each data input signal of the access request input from the arbiter or the bus master is adjusted, and output a data validity period output signal to the bus master after a timing of a data validity period input signal indicating a period in which each data is valid in the access request input from the arbiter is adjusted.

Abstract: A transaction routing device (e.g. an interconnect) for routing transactions in an integrated circuit includes arbitration circuitry for performing arbitration between a plurality of candidate transactions using attribute values associated with the candidate transactions. Candidate transactions are selected for routing to a destination device in dependence on the arbitration. In a cycle in which a new candidate transaction is received, the arbitration is performed using a default attribute value as the attribute value for the new transaction. Meanwhile, the actual attribute value is stored to an attribute storage unit. In a following processing cycle, if the new candidate transaction has not yet been selected for muting, then the arbitration is performed using the actual attribute value stored in the storage unit.

Abstract: In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.

Abstract: A multiprocessing system executes a plurality of processes concurrently. A process execution circuit (10) issues requests to access a shared resource (16) from the processes. A shared access circuit (14) sequences conflicting ones of the requests. A simulating access circuit (12) generates signals to stall at least one of the processes at simulated stall time points selected as a predetermined function of requests from only the at least one of the processes and/or the timing of the requests from only the at least one of the processes, irrespective of whether said stalling is made necessary by sequencing of conflicting ones of the requests. Thus, part from predetermined maximum response times, predetermined average timing can be guaranteed, independent of the combination of processes that is executed.

Abstract: Embodiments of a unified communication and control bus architecture for Ethernet and/or PoE systems are provided. Embodiments enable a unified communication and control bus architecture that significantly simplifies communication and control in Ethernet and/or PoE systems. Embodiments enable significant savings both in terms of cost and complexity as the number of communication and control buses is reduced down to one. Embodiments can be used in various Ethernet and/or PoE implementations, including, for example, single PCB-single PoE, single PCB-multiple PoE, chassis-based switch, and stackable-based switch configurations. Further, embodiments can be implemented using standard Ethernet as well as proprietary implementations.

Abstract: Multiple applications communicate tasks to a collective arbitrator. The arbitrator submits the tasks to a shared resource (work processor) for execution. For each segment of multiple segments of time, the arbitrator tracks consumption of time associated with execution of pending tasks submitted to the shared resource for execution on behalf of multiple applications. The arbitrator further controls subsequent submission of additional sets of one or more tasks to the shared resource for each of the multiple applications over successive segments of time depending on how much time it took the shared resource to perform the submitted tasks in one or more prior time segments. Tracking an amount of time that it takes the shared resource to execute submitted tasks and using such information to control future submission of tasks ensures that each of the task generating resources, over time, is provided fair use of the shared resource.

Abstract: The present disclosure relates to a configurable simulator comprising at least one configuration component and a plurality of configurable modular cards. The configuration component determines configuration parameters of the cards and exchanges configuration messages with the cards. Each card comprises a configurable input/output unit comprising a plurality of configurable inputs and outputs, and a power supply comprising a plurality of configurable power supply circuits. The input/output unit exchanges configuration messages with the simulation controller. Each card further comprises a processor for configuring the plurality of inputs and outputs of the configurable input/output unit, and the plurality of power circuits of the power supply. The processor also executes a simulation code to implement a functionality of the simulator. The present disclosure also relates to a method for operating a configurable simulator comprising a plurality of configurable modular cards.

Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.

Abstract: Described embodiments provide arbitration for a cache of a network processor. Processing modules of the network processor generate memory access requests including a requested address and an ID value corresponding to the requesting processing module. Each request is either a locked request or a simple request. An arbiter determines whether the received requests are locked requests. For each locked request, the arbiter determines whether two or more of the requests are conflicted based on the requested address of each received memory requests. If one or more of the requests are non-conflicted, the arbiter determines, for each non-conflicted request, whether the requested addresses are locked out by prior memory requests based on a lock table. If one or more of the non-conflicted memory requests are locked-out by prior memory requests, the arbiter queues the locked-out memory requests. The arbiter grants any non-conflicted memory access requests that are not locked-out.

Abstract: The present application relates to a method for resource controlling comprising controlling the processing of requests of a first category having a first priority. The method comprises controlling the processing of requests of a second category having a second priority, wherein the first priority is set such that processing the requests of the first category has priority over processing the requests of the second category. The method comprises blocking requests of the first category by a mechanism that detects when a predefined condition regarding the service provided to the second category is met.

Abstract: The present specification describes techniques for packet exchange arbitration. In some embodiments, a request is maintained to an arbiter at least until a packet exchange has been communicated and/or at least until a time-sensitive packet is communicated. In some other embodiments, a grant of a request is delayed at least until the communication of an isochronous packet.

Abstract: A system comprises one or more slave elements operably coupled to a plurality of master devices. A central protection function is operably coupled to a first communication bus and configured to control data flow between the one or more slave elements and the plurality of master devices via the communication bus.

Abstract: Methods and apparatus are provided for controlling an availability of a user in an enterprise environment. If an enterprise user requests to change an availability status on one or more media, a determination is made as to whether to grant the request based on one or more predefined criteria associated with the enterprise. For example, the predefined criteria may comprise resource needs or one or more policies of the enterprise. The predefined criteria may be expressed as one or more rules in a rule base.

Abstract: A system including a first communication module to transmit or receive data via an antenna in accordance with a first communication standard; a second communication module to transmit or receive data via the antenna in accordance with a second communication standard; and an arbitration module. The arbitration module outputs a first mutual grant where both the first communication module and the second communication module are able to simultaneously transmit data via the antenna; a second mutual grant where both the first communication module and the second communication module are able to simultaneously receive data via the antenna; a third mutual grant where the first communication module and the second communication module are able to simultaneously transmit and receive data, respectively, via the antenna; and a fourth mutual grant where the first communication module and the second communication module are able to simultaneously receive and transmit data, respectively, via the antenna.

Abstract: A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device.