Abstract: System and techniques for memory side cache request handling are described herein. When a memory request is received, a cache set for the memory request is determined. Here, the cache set has multiple ways and each way corresponds to a cache line. It can be detected that a way of the multiple ways is not ready for the memory request. In this case, a representation of the memory request is stored in a queue of multiple queues based on an interface upon which the memory request was received and the present ways of the cache set. Entries from the multiple queues can be dequeued in a defined order to determine a next memory request to process. The defined order gives priority to memory requests for a present way and then for external over internal requests.

Abstract: At least one application of a client executes via system software on a hardware computing system that includes at least one CPU and at least one coprocessor. A virtualization layer establishes unified memory address space between the client and the hardware computing system, which also includes memory associated with the at least one coprocessor. The virtualization layer then synchronizes memory associated with the client and memory associated the at least one coprocessor. The virtualization layer may be installed and run in a non-privileged, user space, without modification of the application or of the system software running on the hardware computing system.

Abstract: Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.

Abstract: A method for managing access to a shared resource in an electronic system including a control unit and the shared resource. The control unit is intended to execute applications that are candidates for access to the shared resource. The method uses a calendar of periods of equal duration, each assigned to just one of the applications, to define a temporal distribution of access to the shared resource, and penalty indices associated with each of the applications. The method includes steps for conditionally processing the access requests transmitted by the applications according to their penalty indices. Thus, each application is prevented from accessing the shared resource when the quota assigned thereto is reached, which makes it possible to limit the encroachment of an application that is executed on the access quotas for accessing the resource that are assigned to the other applications.

Abstract: Methods and systems disclosed herein relate generally to evaluating resource loads to determine when to transform queues and to specific techniques for transforming at least part of queues so as to correspond to alternative resources.

Abstract: Methods of arbitrating between requestors and a shared resource wherein for each processing cycle a plurality of select signals are generated and then used by decision nodes in a binary decision tree to select a requestor. The select signals are generated using valid bits and priority bits. Each valid bit corresponds to one of the requestors and indicates whether, in the processing cycle, the requestor is requesting access to the shared resource. Each priority bit corresponds one of the requestors and indicates whether, in the processing cycle, the requestor has priority. Corresponding valid bit and priority bits are combined in an AND logic element to generate a valid_and_priority bit for each requestor. Pair-wise OR-reduction is then performed on both the valid bits and the valid_and_priority bits to generate additional valid bits and valid_and_priority bits for sets of requestors and these are then used to generate the select signal.

Abstract: Some aspects of this disclosure relate to implementing a thread device that can associate with a thread network. The thread device includes a network processor, a first memory, and a host processor communicatively coupled to the network processor and the first memory. The first memory can be a nonvolatile memory with a first level security protection, and configured to store a first dataset including thread network parameters for the network processor to manage network functions for the thread device associated with the thread network. The network processor can be coupled to a second memory to store a second dataset having a same content as the first dataset. The network processor is configured to manage the network functions based on the second dataset. The second memory can be a volatile memory with a second level security protection that is less than the first level security protection.

Abstract: An apparatus comprises interface circuitry to receive requests and selection circuitry responsive to the interface circuitry receiving a given request to select, from a pool of items, at least one selected item to be associated with the given request. The selection circuitry comprises a plurality of nodes arranged in a tree structure, each node being configured to select m output signals from n input signals provided to that node, wherein n>m. The apparatus comprises control circuitry configured to output, in dependence on a type of the given request, a suppression signal, and the tree structure comprises a gate node configured to suppress, in response to the suppression signal having a first value, selection from input signals received from a given portion of the tree structure to prevent a subset of the pool of items from being selected for at least one type of request.

Abstract: Bandwidth control can be provided for input/output channels according to some aspects described herein. In one example, a system can detect an input/output (I/O) request transmitted by a software application. In response to detecting the I/O request, the system can determine a bandwidth group that corresponds to an I/O channel associated with the I/O request. The system can then determine whether bandwidth consumption of the bandwidth group exceeds a predefined bandwidth limit. If so, the system can execute a predefined policy assigned to the I/O channel for handling the I/O request.

Abstract: An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem.

Abstract: An apparatus comprises memory access circuitry to access a memory system; a plurality of memory mapped registers, including at least an insert register and a producer pointer register; and control circuitry to perform an insert operation in response to receipt of an insert request from a requester device sharing access to the memory system. The insert request specifies an address mapped to the insert register and an indication of a payload. The insert operation includes controlling the memory access circuitry to write the payload to a location in the memory system selected based on a producer pointer value stored in the producer pointer register, and updating the producer pointer register to increment the producer pointer value.

Abstract: Methods and systems disclosed herein relate generally to evaluating resource loads to determine when to transform queues and to specific techniques for transforming at least part of queues so as to correspond to alternative resources.

Abstract: According to examples, an apparatus may include a memory on which is stored machine-readable instructions that may cause a processor to determine, for each of a plurality of members in a group, a respective least privilege level for a resource and determine, based on the determined respective least privilege levels, a privilege level to be assigned to the group for the resource. The instructions may also cause the processor to assign the determined privilege level to the group for the resource and apply the assigned privilege level to the members of the group for the resource.

Abstract: Methods and apparatus for low latency operation in user space networking architectures. In one embodiment, an apparatus configured to enable low latency data transfer is disclosed. The exemplary embodiment provides a multiplexer that allocates a fixed portion of network bandwidth for low latency traffic. Low latency traffic is routed without the benefit of general-purpose packet processing. In one embodiment, network extensions for low latency operations are described. Specifically, an agent is described that enables low latency applications to negotiate for low latency access. In one embodiment, mechanisms for providing channel event notifications are described. Channel event notifications enable corrective action/packet processing by the low latency application. In one embodiment, mechanisms for providing interface advisory information are described. Interface advisory information may be provided asynchronously to assist in low latency operation.

Abstract: An apparatus includes a memory device and a microcontroller device integrated with the memory device. The microcontroller device is adapted to be communicatively coupled to a processor device and is configured to manage access by the processor device to data stored on the memory device. Managing access by the processor device to the data stored on the memory device includes setting an access permission for controlled data stored by the memory device based on authorization data stored in the memory device. Managing access by the processor device further includes receiving, from the processor device, a request to access the controlled data. Managing access by the processor device further includes determining whether to initiate access to the controlled data by the processor device based on the access permission.

Abstract: In some examples, using a model generated from an aggregation of parameter values for a plurality of host systems, a system predicts an operational metric representing usage or performance of a shared resource due to a requester in a first host system of the plurality of host systems, the shared resource being outside of the plurality of host systems.

Abstract: Provided is a task scheduling method. The method may include: assigning a task to one of first processing units functionally connected to an electronic device; and migrating, at least partially on the basis of a performance control condition related to the task, the task to one of second processing units for processing.

Abstract: Systems and methods described herein provide for assigning classifications to signals and corresponding messages for prioritization and transmission across a vehicle CAN bus. The assigned classifications are used to prioritize messages, signals, and nodes of the vehicle CAN bus. The classifications are used to prioritize critical messages and high priority messages that control operations of the vehicle system.

Abstract: A system on chip including a first peripheral circuit, a second peripheral circuit, and a first bridge control circuit is provided. The first bridge control circuit stores a first attribute setting value and a second attribute setting value and determines whether the attribute information of the first output command matches the first attribute setting value or the second attribute setting value. In response to the attribute information of the first output command matching the first attribute setting value, the first bridge control circuit provides the first output command to the first peripheral circuit. In response to the attribute information of the first output command matching the second attribute setting value, the first peripheral circuit provides the first output command to the second peripheral circuit.

Abstract: An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem.

Abstract: A method for monitoring at least one software application able to be executed on a platform including resources that each software application is able to access during its execution, is implemented by an electronic monitoring device. It comprises: monitoring each access request sent by a non-critical software application in order to access a set of resource(s) shared between the non-critical software application and at least one critical software application; and putting the access request sent by the non-critical software application on hold if it is sent during a buffer time period preceding the execution of the next critical software application including a reserved section for the set of shared resource(s), the reserved section being a time period during which one of the at least one critical software application requests exclusive access to the set of shared resource(s).

Abstract: A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells. The processor is configured to test memory cells of a protected memory area of the memory by performing memory accesses at bit level, control a counting register in such a way that a value stored in the counting register is modified according to a number of performed memory accesses, and test memory cells of the protected memory area of the memory only if the value stored in the counting register lies within a permissible value range.

Abstract: In certain embodiments, a Service Deployment Infrastructure (SDI) request engine is disclosed. The SDI request engine can perform tracking, management and provisioning of services subscribed to by users of a computer infrastructure system. The SDI request engine can be deployed to process large volumes of provisioning requests and deliver time critical applications for customers. The SDI request engine can translate each request into a list of tasks of various sizes based on the requirement and configuration of the request, and store each task in a queue. In certain embodiments, the SDI request engine may evaluate a dynamic weight associated with each task to prioritize the processing of tasks, which may improve the overall throughput of request processing.

Abstract: A method and apparatus for cooperative scheduling of virtual machines. An exemplary method includes maintaining a CPU mask by a virtual machine manager, wherein the CPU mask comprises a real-time availability of each of a plurality of physical CPUs (PCPUs). A virtual machine (VM) is allowed to read the CPU mask.

Abstract: The disclosed systems and methods provide hyperscalar packet processing. A method includes receiving a plurality of network packets from a plurality of data paths. The method also includes arbitrating, based at least in part on an arbitration policy, the plurality of network packets to a plurality of packet processing blocks comprising one or more full processing blocks and one or more limited processing blocks. The method also includes processing, in parallel, the plurality of network packets via the plurality of packet processing blocks, wherein each of the one or more full processing blocks processes a first quantity of network packets during a clock cycle, and wherein each of the one or more limited processing blocks processes a second quantity of network packets during the clock cycle that is greater than the first quantity of network packets. The method also includes sending the processed network packets through data buses.

Abstract: In one aspect of multi-mode address mapping management in accordance with the present disclosure, mapping and unmapping operations may be conducted in one of multiple address mapping management modes to both improve overall system performance and maintain data integrity. In one embodiment, a first address mapping management mode such as a rigorous mode, for example, confirms completion of an unmapping of an address mapped data unit buffer before a re-mapping is permitted. Mapping and unmapping operations may be switched to a performance mode in which unmap completion confirmation is bypassed to improve performance. In one embodiment, address mapping management modes may be switched in real time as a function of monitored operating conditions. Other aspects and advantages are provided, depending upon the particular application.

Abstract: A multi-die system includes a non-volatile memory, a first die having a first operational clock, a second die having a second operational clock, and an arbiter. The first die includes a first bus, a first bus filter coupled to the first bus and the arbiter for controlling access signals, a first access controller coupled to the first bus filter, and a first input/output (I/O) filter coupled to the first access controller, the arbiter and the non-volatile memory for controlling access to the non-volatile memory. The second die includes a second bus, a second bus filter coupled to the second bus and the arbiter, a second access controller coupled to the second bus filter, and a second I/O filter coupled to the second access controller, the arbiter and the non-volatile memory. The first and second operational clocks are independent.

Abstract: Aspects described herein may utilize self-federation in a plugin-based authentication system to support combinations of authentication processes. The authentication system may include a plugin that executes an authentication process that is a combination of two or more other authentication processes. This plugin may handle the combined authentication process by self-federating back to the authentication interface, generating its own authentication requests under each of the subsidiary authentication processes. Thus, the self-federating plugin corresponding to the combined authentication process may allow the authentication system to support authentication requests that indicate the combined authentication process. This “chained” authentication process, accomplished through self-federation, may allow the authentication system to reuse existing code paths and avoid downsides associated with duplication of code.

Abstract: Methods and systems for controlling writing to register files in a processing system having at least two execution pipelines are provided. Aspects include obtaining a micro operation for execution by an execution unit of a first pipeline in the processing system, wherein the micro operation includes writing data to a register file. Aspects also include determining whether the data will be accessed by an execution unit of a second pipeline in the processing system. Based on a determination that the data will only be accessed by the execution unit of the first pipeline, aspects include blocking writing of the data to a register file of the second pipeline.

Abstract: A method for dynamically remediating a security system entity includes establishing a security score for a security system entity (SSE) supporting a trusted network based on a security policy configuration of the SSE. The method further includes receiving, by the SSE, ingress network traffic flows directed to the trusted network and determining an updated security score for the SSE based on the security policy configuration of the SSE and the ingress network traffic flows that are permitted into the trusted network via the SSE. The method also includes remedying the security policy configuration of the SSE if the updated security score differs from the baseline security score by a predefined amount.

Abstract: Methods, systems, and devices are described for controlling a sprinkler system, including an apparatus for sprinkler system control that includes a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions are executable by the processor to receive operation instructions for the sprinkler system from a source that is separate from a control panel of the sprinkler system, and operate valves of the sprinkler system independent of instructions from the control panel.

Abstract: An example operation may include one or more of identifying a blockchain transaction submitted from a requestor member of the blockchain, identifying one or more task requests associated with the blockchain transaction, determining one or more blockchain members having resources available for completing the one or more task requests, wherein the resources are identified via known computing parameters associated with each of the one or more blockchain members, and assigning the one or more task requests to the one or more blockchain members based on the resources available.

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for providing a customized representation of a business process involving one or more organizational entities that are accessible through a network. A user interface that can display a customized representation of a business process is provided. User information, including user privileges associated with the business process, is stored in a central repository that is accessible through the network. A request to view the business process is received from a first user through the user interface. The user privileges for the first user are retrieved from the central repository. A customized representation of the business process is displayed with the user interface. The customized representation is in compliance with the retrieved user privileges for the first user.

Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.

Abstract: A memory system includes a memory controller having a bank command scheduler implemented in a hardware logic block and a power budget controller including a power budget register and a credit register. The hardware logic block is able to determine a command in a queue to be transmitted to a memory bank over a channel, estimate a power consumption value for the command, and query the power budget controller to determine if the power consumption value is within a threshold. If the power consumption value is within the threshold, the hardware logic block receives a grant response from the power budget controller, adds the power consumption value to the credit register value, transmits the command over the channel, and transmits a signal to the power budget controller indicating that the command has been executed and that the power consumption value should be subtracted from the credit register value.

Abstract: Methods, systems, and computer programs for receiving, by an embedded controller (EC), an EC firmware update from a central processing unit (CPU); storing the EC firmware update into a buffer region of a flash memory medium via a first bus, the first bus communicatively coupling the EC and the flash memory medium; verifying the EC firmware update stored in the buffer region of the flash memory medium; and in response to verifying the EC firmware update: storing the verified EC firmware update into a primary region of the flash memory medium; and loading the verified EC firmware update from the primary region into an EC memory medium of the EC via the first bus.

Abstract: An apparatus for controlling a solid state drive (SSD) includes an host interface, to receive a set of memory access commands from a host computer, and processing circuitry coupled to the host interface and to memory cells of the SSD, to distinguish the write commands from the read commands in the set, and execute up to a threshold number of the write commands prior to executing any of the read commands.

Abstract: According to a method of transforming a message passing interface (MPI) program, an MPI function is parsed such that a computer may directly access data created by another computer through a memory when an MPI parallel program is executed on a computer system for distributed processing, a network function corresponding to the MPI function is created for network communication, and a bus line function is created for directly accessing the memory through a bus line.

Abstract: Technologies for determining a root of congestion include a network switch. The network switch is to operate arbiter units in at least one upstream stage at a packet transfer rate that is greater than a packet transfer rate of an arbiter unit in an output stage, determine whether an input buffer of a remote network switch in communication with the output stage has sustained congestion over a first predefined time period, determine whether an output buffer of the arbiter unit in the output stage has sustained congestion over a second predefined time period, and determine, as a function of whether the input buffer of the remote network switch has sustained congestion and whether the output buffer of the arbiter unit in the output stage has sustained congestion, whether the network switch is a root of congestion.

Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

Abstract: Usage instrumented workload scheduling is disclosed. For example, a plurality of nodes host first and second pluralities of guests. An orchestrator includes a usage monitor, a workload classifier, and a scheduler, and executes on a processor to track, by the usage monitor, respective usage patterns of a plurality of accounts including a first account. A first workload is received from the first account, which has a first account factor based on the respective usage patterns of the first account. The first workload is assigned by the workload classifier to a first workload type of a plurality of workload types. The first workload is assigned by the scheduler to the first plurality of guests based on the first account factor and the first workload type.

Abstract: In order to make use of computational resources available at runtime through fog networked robotics paradigm, it is critical to estimate average performance capacities of deployment hardware that is generally heterogeneous. It is also not feasible to replicate runtime deployment framework, collected sensor data and realistic offloading conditions for robotic environments. In accordance with an embodiment of the present disclosure, computational algorithms are dynamically profiled on a development testbed, combined with benchmarking techniques to estimate compute times over the deployment hardware. Estimation in accordance with the present disclosure is based both on Gustafson's law as well as embedded processor benchmarks. Systems and methods of the present disclosure realistically capture parallel processing, cache capacities and differing processing times across hardware.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for persistent memory management. Persistent memory management may include providing a persistent data structure stored at least partially in volatile memory configured to ensure persistence of the data structure in a non-volatile memory medium. Persistent memory management may include replicating a persistent data structure in volatile memory buffers of at least two non-volatile storage devices. Persistent memory management may include preserving a snapshot copy of data in association with completion of a barrier operation for the data. Persistent memory management may include determining which interface of a plurality of supported interfaces is to be used to flush data from a processor complex.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a persistent data structure. A method includes associating a logical identifier with a data structure. A method includes writing data of a data structure to a first region of a volatile memory module. A volatile memory module may be configured to ensure that data is preserved in response to a trigger. A method includes copying data of a data structure from a volatile memory module to a non-volatile storage medium such that the data of the data structure remains associated with a logical identifier.

Abstract: For preventing implementation errors due to misconfigured host applications, a storage controller provisions a storage destination with a capability identifier configured to indicate that the storage destination mandates atomic write operations. The storage controller also receives a write request for the storage destination from host application, and rejects, in response to the received request including a non-atomic write operation, the non-atomic write request.

Abstract: In some cases, processor graphics with a slower local memory can compensate by using another memory in place of the lowest level or L3 cache. For example, in some processors, there is a large register space that can be used for the local memory function by allocating the local memory within those registers. Also, since the registers do not operate with barriers, barriers can be simulated by letting one execution unit thread execute more SIMD instructions. For example, one execution thread may simulate a whole work-group in the OpenCL API.

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

Abstract: Method and system are disclosed for controlling hardware queues. In one embodiment, a system for controlling hardware queues includes a slow memory configured to store a set of hardware queues, a set of fast memories configured to facilitate operations to the set of hardware queues in the slow memory, where a fast memory in the set of fast memories includes a head cache configured to track read operations of a hardware queue in the set of hardware queues, and a tail cache configured to track write operations of the hardware queue in the set of hardware queues, a set of queue control engines configured to control the write operations and read operations to the set of hardware queues through the set of fast memories, and a processor configured to control the set of queue control engines with the write operations and read operations to the set of hardware queues through the set of fast memories.

Abstract: Methods and systems disclosed herein relate generally to evaluating resource loads to determine when to transform queues and to specific techniques for transforming at least part of queues so as to correspond to alternative resources.

Abstract: A processor may include a core to execute interrupt latency control unit (ILCU) software and an interrupt controller circuitry. The interrupt controller circuitry includes: a first register to store a first time value at which a first interrupt is received at the interrupt controller circuitry and a second register to store a second time value at which the first interrupt is delivered to the core. The ILCU software is to: read the first time value in the first register and the second time value in the second register; determine an amount of time the first interrupt was pending at the interrupt controller circuitry; determine interrupt configuration information that adjusts the first interrupt priority of a subsequent interrupt; and send the interrupt configuration information to the interrupt controller circuitry. The interrupt controller circuitry is to adjust the first interrupt priority of the subsequent interrupt to the second interrupt priority.