Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit includes a first interface coupled to a host device and a second interface coupled to the HBM device. The logic circuit receives a first command from the host device through the first interface and converts the received first command to a first processing-in-memory (PIM) command that is sent to the HBM device through the second interface. The first PIM command has a deterministic latency for completion. The logic circuit further receives a second command from the host device through the first interface and converting the received second command to a second PIM command that is sent to the HBM device through the second interface. The second PIM command has a non-deterministic latency for completion.

Abstract: The present disclosure generally relates to improving data transfer speed. A data storage device includes both a controller and a memory device. The controller provides instructions regarding read and/or write commands to the memory device through the use of control lines. The data to be written/read is transferred between the controller and the memory device along data lines. The control lines typically are not used during data transfer. During data transfer, the control lines can be used to increase data transfer speed by utilizing the otherwise idle control lines for data transfer in addition to the data lines. Hence, data transfer speed is increased by using not only the data lines, but additionally the control lines. Once the data transfer is complete, the control lines return to their legacy function.

Abstract: Wireless communication techniques that include QoS techniques for scheduling transmission of QUIC streams in a wireless communication system are discussed. A wireless communication device may receive a data packet having a header that includes a first plurality of fields. The wireless communication device may also schedule transmission of the data packet based on QoS parameters associated with the first plurality of fields. The transmission of the data packet may be scheduled based on QoS parameters associated with the first plurality of fields when the first plurality of fields match a second plurality of fields. Other features are also described.

Abstract: According to one embodiment, a memory system retrieves write data from a write buffer of a host, and executes a write operation of writing the write data to a write destination location of a write destination block selected from a plurality of blocks. In a case where a first read command to designate the write data as read target data is received from the host before the write operation is finished such that the write data becomes readable, the memory system executes a read operation including an operation of reading the read target data from the write buffer of the host and an operation of returning the read target data to the host. The memory system prohibits releasing a region in the write buffer where the write data is stored until execution of the first read command is completed.

Abstract: A system architecture is provided and includes an on-chip coherency unit, a processing unit, an accelerator and dedicated wiring. The processing unit is communicative with the on-chip coherency unit via a first interface. The accelerator is communicative with the on-chip coherency unit via a second interface. The accelerator is configured to be receptive of a request to execute lossless data compression or decompression from the processing unit and to responsively execute the lossless data compression or decompression faster than the processing unit. The processing unit and the accelerator are directly communicative by way of the dedicated wiring.

Abstract: Systems and methods for intelligent fetching of data storage device commands from submission queues are provided. One such method involves fetching commands from one or more submission queues, monitoring characteristics of the commands including a command type, predicting a next command based on the monitored command characteristics, monitoring a resource state of a data storage device, selecting a submission queue based on the predicted next command and the resource state, fetching a command from the selected submission queue, and providing the command from the selected submission queue to command processing logic.

Abstract: An integrated circuit includes a display sub-system that has a plurality of image processing resources and control logic. The image processing resources include a plurality of image processing pipelines configured to operate in parallel, overlay logic coupled to receive image data from the plurality of image processing pipelines, and an image output port coupled to an output of the overlay logic with image data outputs configured to couple to one or more display devices. The control logic is dynamically configurable to assign each of the image processing resources to a selected one of a first control port and a second control port. The first control port is configured to be controlled exclusively by a first processor and the second control port is configured to be controlled exclusively by a second processor.

Abstract: Systems and methods for providing input/output (I/O) determinism. An I/O instruction and at least one service level indicator are received, wherein the at least one service level indicator includes a required time for executing the I/O instruction. It is determined whether the I/O instruction can be executed on the storage within the required time. When it is not determined that the I/O instruction can be executed on the storage within the required time, a notification is sent.

Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.

Abstract: Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. On method is implemented in a data storage device including a controller and a memory. The method includes collecting submission queue command statistics; monitoring resource state of the data storage device. The method further includes using the submission queue command statistics and the resource state to select a submission queue from which a next data storage device command should be fetched. The method further includes fetching the command from the selected submission queue. The method further includes providing the command to command processing logic.

Abstract: In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.

Abstract: Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. On method is implemented in a data storage device including a controller and a memory. The method includes collecting submission queue command statistics; monitoring resource state of the data storage device. The method further includes using the submission queue command statistics and the resource state to select a submission queue from which a next data storage device command should be fetched. The method further includes fetching the command from the selected submission queue. The method further includes providing the command to command processing logic.

Abstract: An electronic device includes a control circuit and a bus interface. The control circuit packs a plurality of commands in a compound command frame. The bus interface communicates with another electronic device via a bus between the electronic device and the another electronic device, and packs the compound command frame in a single packet and transmits the single packet over the bus.

Abstract: An apparatus is provided that includes a transceiver to transmit and receive data between an upstream device and the apparatus, and further includes service latency reporting logic coupled to the transceiver to provide a service latency tolerance value of the apparatus to the upstream device, the service latency tolerance value corresponding to an activity state of the apparatus. The service latency tolerance value for an idle activity state can be greater than the service latency tolerance value for an active activity state.

Abstract: A memory device includes a first memory block suitable for transmitting and receiving signals through a first channel, a second memory block suitable for transmitting and receiving signals through a second channel, and a test control unit suitable for applying a first command signal among a plurality of command signals to the first and second channels at different values, while applying the plurality of command signals from an exterior of the memory device to the first and second channels in a test operation, wherein the first command signal distinguishes write and read operations of the first and second memory blocks, wherein, when the first memory block performs a read operation in the test operation, the second memory block performs a write operation, and data outputted from the first memory block is inputted to the second memory block.

Abstract: A circuit information generating apparatus includes a switching section that switches wiring between a base module and an extension module, an address acquisition section acquiring identification information of the extension module, a wiring information acquisition section, a firmware acquisition section acquiring firmware that operates the extension module, a wiring information rewriting section identifying circuit configuration information of each extension module based on the identification information, and rewrites a part of the wiring information based on the circuit configuration information, a circuit information generating section generating circuit information based on the circuit configuration information of the extension module and the rewritten wiring information, and a firmware generating section rewrites definition information of the wiring included in the firmware, based on the rewritten wiring information, and generates information indicating a circuit configuration of an electronic circuit co

Abstract: Systems and methods providing a downloadable custom light emitting diode (LED) blinking pattern for a controller, which performs backplane or enclosure management. The controller has a memory, which stores data of a standard LED blinking pattern. When no custom LED blinking pattern data is available in the memory, the controller controls the LEDs to perform a standard blinking pattern based on the standard LED blinking pattern data to indicate the of the storage drives. A user may generate a custom pattern file, which contains custom LED blinking pattern data, and then use a downloading tool to download the custom pattern file to the controller, such that the memory of the controller may store the custom LED blinking pattern data. Instead of using the standard LED blinking pattern, the controller may then control the LEDs to perform a custom blinking pattern based on the custom LED blinking pattern data.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can continually increase a command rate of an interconnect if one or more requests to lower the command rate are not received within one or more periods of time. In one example, the command rate can be set to a fastest level. In another example, the command rate can be incrementally increased over periods of time. If a request to lower the command rate is received, the command rate can be set to a reference level or can be decremented to one slower rate level. In one or more embodiments, the one or more requests to lower the command rate can be based on at least one of an issue rate of speculative commands and a number of overcommit failures, among others.

Abstract: An integrated circuit device may include a first integrated circuit (IC) portion having a memory array that stores data units as storage locations and burst access circuitry that sequentially accesses N relates storage locations within the memory array, where N>1; and a second IC portion comprising a plurality of burst access registers coupled to the burst access circuitry, each burst access register having register locations to store at least N data units, and being coupled to a corresponding port by a single data unit access path.

Abstract: An exemplary embodiment of this disclosure is a method for operating a data processing system, where the data processing system includes a service bus connected between a client and a server. The service bus includes one or more applications configured to mediate message flow between the client and the server. The method includes receiving a message from the client at the service bus, and mediating the message at a message-mediating application of the service bus. The mediation includes adding a header to the message, the header defining a source and a predetermined condition under which a target can respond directly to the source. The source is either the client or an application of the service bus, and the target is either an application of the service bus or the server.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can continually increase a command rate of an interconnect if one or more requests to lower the command rate are not received within one or more periods of time. In one example, the command rate can be set to a fastest level. In another example, the command rate can be incrementally increased over periods of time. If a request to lower the command rate is received, the command rate can be set to a reference level or can be decremented to one slower rate level. In one or more embodiments, the one or more requests to lower the command rate can be based on at least one of an issue rate of speculative commands and a number of overcommit failures, among others.

Abstract: APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams.

Abstract: A system and method for transferring data between a memory and peripheral units via a plurality of direct memory access (DMA) transactions, wherein a respective timestamp is assigned and/or appended to at least two of the plurality of the DMA transactions.

Abstract: An external memory interface includes an input/output (IO) logic unit operable to convert a rate of data from a first rate corresponding to a memory controller/schedule unit to a second rate corresponding to an external memory device. The external memory interface also includes a latency adjustment unit, operating in a timing domain of the memory controller/schedule unit, operable to add between 1 to [(second rate/first rate)?1] cycles of latency of the second rate.

Abstract: Described herein are techniques for cancelling I/O requests. Initially, virtual memory of an application is assigned to a first portion of memory. The application may issue a read request to an external device. The external device is instructed to record any response to the read request in the first portion of memory. The read request may be cancelled as follows. The virtual memory of the application may be re-assigned to a second portion of the memory. If and when the external device finishes processing the read request, the external device's response to the read request may still be saved in the first portion of memory, even though the read request has been cancelled. Such action of the external device would ordinarily corrupt the virtual memory of the application, but due to the memory re-assignment, no corruption of the virtual memory occurs. Similar techniques may be applied to cancel write requests.

Abstract: A print control apparatus includes a print management unit, a storage unit, a print control unit, and a checking unit. The print management unit accepts print instructions for output data, and records an order in which the print instructions have been accepted. The storage unit temporarily stores the output data related to the print instructions accepted by the print management unit. The print control unit sequentially acquires the output data from the storage unit, transmits the output data to an image forming apparatus, and records an order in which the output data have been transmitted. The checking unit compares and checks the order in which the print instructions have been accepted, which has been recorded by the print management unit, and the order in which the output data have been transmitted, which has been recorded by the print control unit.

Abstract: A data processing device includes a memory, a direct memory access controller including a receiving module configured to receive data coming from outside the device and for writing the data in a main buffer memory of the memory, and a processing unit programmed to read and process data written by the receiving module in a work area of the main buffer memory. The main buffer memory is divided between a used space, where the receiving module is configured not to write, and free space, where the receiving module is configured to write. The processing unit is further programmed to define the work area, and the direct memory access controller includes a buffer memory manager configured to free data written in the main buffer memory, by defining a location of this data as a free space, only when this data is outside the work area.

Abstract: Methods and apparatus for packing received Serial Attached SCSI (SAS) frames in buffers for transmission to a host system memory. SAS frames are received from another SAS device and stored in a frame buffer memory. User data in the received frames has appended SCSI Data Integrity Fields (DIF information) to enhance reliability. Features and aspects hereof use the DIF information to validate the user data and then strip the DIF information to densely pack the validated user data in a DMA staging buffer for transmission to a host's system buffer memory using DMA features of the SAS device. The DMA circuit is programmed and started when the staging buffer is filled to at least a threshold amount of data to thereby improve efficacy of the DMA transfer performance. Other criteria may also be employed to determine when to start the DMA circuit.

Abstract: A data processing system includes an audio processor with a main memory for storing data, first and second buffers for temporarily storing the data to input/output an audio signal, and a data input/output (I/O) unit for outputting the stored data. A direct memory access (DMA) controller is provided for transmitting data between the main memory and the first and second buffers according to a DMA transmission process. If transmission of the data stored in the first buffer ends and an interrupt signal is thus generated, the DMA controller increases sizes of the first and second buffers during transmission of the data stored in the second buffer.

Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

Abstract: APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams.

Abstract: Systems and methods are provided that may be implemented to manage machine-specific System Profile Unique Data (SPUD) information for one or more information handling systems. Such SPUD information may be managed and transported through in-band and/or out-of-band processing and communications, and may be employed to make restoration of machine-specific data possible either through network data communications and/or local system data communications.

Abstract: A system for controlling a storage device. A semiconductor chip of the storage device, includes a first memory. The first memory corresponds to a first type of memory, is configured to perform random access memory functions, and is not configured to perform direct memory access functions. A second memory external to the semiconductor chip is configured to interface with the semiconductor chip. The second memory corresponds to a second type of memory that is different than the first type of memory, is configured to perform direct memory access functions, and is not configured to perform random access memory function. The second memory includes a memory cell and an interface configured to interface between components of the second memory including the memory cell and the semiconductor chip.

Abstract: In an information processing device according to an embodiment, a generating unit generates a descriptor including information indicating an area in a storage unit and state information indicating a state of an entry in which the information indicating the area is stored, and an update unit updates the state information according to at least one of writing and reading of data to the area indicated in the entry selected according to the state information by the input/output unit. The generating unit generates the descriptor in advance before at least one of writing and reading of data to/from the storage unit is started.

Abstract: When a data request signal is inactivated while a DMA controller is executing DMA data transfer in a burst transfer mode, an address at this time is held and a remaining number of transfer times is counted. After the DMA data transfer in the burst transfer mode is finished, the address and the remaining number of transfer times are re-set in the DMA controller and then the DMA data transfer is executed. This makes it possible to re-transfer data remaining at the timing when the data request signal is inactivated, and the DMA data transfer using the burst transfer mode is executed to or from a module requesting the DMA data transfer by using level of the data request signal.

Abstract: An SD/SDIO host controller is disclosed, which includes a control register and interrupt generation module, an internal DMA module, an SD/SDIO command interface module, an SD/SDIO data interface module, and a frequency divider and trigger/sampling enable signal generation module which is connected to an output end of the control register and interrupt generation module; the frequency divider and trigger/sampling enable signal generation module employs a frequency divider to perform frequency division on a local high-speed clock so as to obtain the operating clock of the SD/SDIO card, and simultaneously generates a trigger/sampling enable signal by the frequency divider and enables the position of the enable signal to be adjustable with respect to the operating clock of the SD/SDIO card. The present invention is capable of solving the setup/hold time issues caused by delay in digital signals.

Abstract: A system for improving direct memory access (DMA) offload. The system includes a processor, a data DMA engine and memory components. The processor selects an executable command comprising subcommands. The DDMA engine executes DMA operations related to a subcommand to perform memory transfer operations. The memory components store the plurality of subcommands and status data resulting from DMA operations. Each of the memory components has a corresponding token associated therewith. Possession of a token allocates its associated memory component to the processor or the DDMA engine possessing the token, making it inaccessible to the other. A first memory component and a second memory component of the plurality of memory components are used by the processor and the DDMA engine respectively and simultaneously. Tokens, e.g., the first and/or the second, are exchanged between the DDMA engine and the processor when the DDMA engine and/or the microcontroller complete accessing associated memory components.

Abstract: Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

Abstract: In general, in one aspect, a method includes determining a repeated, periodic DMA (Direct Memory Access) coalescing interval based, at least in part, on a power sleep state of a host platform. The method also includes buffering data received at the device in a FIFO (First-In-First-Out) queue during the interval and DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.

Abstract: A data transfer system includes: a processor; a main memory that is connected to the processor; a peripheral controller that is connected to the processor; and a peripheral device that is connected to the peripheral controller and includes a register set, wherein the peripheral device transfers data stored in the register set to a predetermined memory region of the main memory or the processor by a DMA (Direct Memory Access) transfer, and the processor reads out the data transferred to the memory region by the DMA transfer without accessing to the peripheral device.

Abstract: A system, method, and computer program product are provided for inserting a gap in information sent from a drive to a host device. In operation, one or more commands are received at a drive from a host device. Additionally, information is queued to send to the host device. Furthermore, a gap is inserted in the information to send to the host device such that the host device is capable of sending additional commands to the drive.

Abstract: APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams.

Abstract: Methods and apparatus are provided for managing interrupts within a virtualizable communication device. Through virtualization, one port of the device may be able to support multiple hosts (e.g., computers) and multiple functions operating on each host. Any number of interrupt resources may be allocated to the supported functions, and may include receive/transmit DMAs, receive/transmit mailboxes, errors, and so on. Resources may migrate from one function to another, such as when a function requests additional resources. Each function's set of allocated resources is isolated from other functions' resources so that their interrupts may be managed and reported in a non-blocking manner. If an interrupt cannot be immediately reported to a destination host/function, the interrupt may be delayed, retried, cancelled or otherwise handled in a way that avoids blocking interrupts to other hosts and functions.

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Abstract: A sub-system for controlling a medical device comprises memory including a first table and a second table. The first table stores blocks of event data corresponding to events that are to be performed during a period of time (e.g., a 0.5 sec. or 1 sec. period of time). The second table stores blocks of time data corresponding to the period of time. The implantable stimulation system also includes a direct memory access (DMA) controller including a first DMA channel and a second DMA channel. The first DMA channel selectively transfers one of the blocks event data from the first table to one or more registers that are used to control events. The second DMA channel selectively transfers one of the blocks of time data from the second table to a timer that is used to control timing associated with the events.

Abstract: An I/O controller and method are provided. The I/O controller to which an I/O device can be connected, and instructs the I/O device to execute a process includes a descriptor transfer device that transfers a descriptor indicating contents of a process to be executed, and execution instruction unit that instructs the I/O device to execute the process, based on the descriptor transferred from the descriptor transfer device, wherein the descriptor transfer device includes a memory for storing the descriptor; descriptor reading unit that reads, according to an indication regarding a descriptor read source from a processor, an indicated descriptor from a main memory or said memory which stores the descriptor, and descriptor transfer unit that transfers the read descriptor to the execution instruction unit.

Abstract: A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

Abstract: An image forming apparatus that can reduce the number of signal lines that can respond to interrupt processing by conducting I/O control that can acquire irregularly generated sensor detection signals. Identification control means of the image forming apparatus uses the data line in the period other than when conducting identification control of the detection means or the drive means to acquire the data of the specified detection means as valid data. Delay of the detection response time to irregularly generated signals can be minimized by using the data line other than when conducting identification control of the detection means or the drive means to acquire irregularly generated detection signals.

Abstract: Methods and apparatus for packing received Serial Attached SCSI (SAS) frames in buffers for transmission to a host system memory. SAS frames are received from another SAS device and stored in a frame buffer memory. User data in the received frames has appended SCSI Data Integrity Fields (DIF information) to enhance reliability. Features and aspects hereof use the DIF information to validate the user data and then strip the DIF information to densely pack the validated user data in a DMA staging buffer for transmission to a host's system buffer memory using DMA features of the SAS device. The DMA circuit is programmed and started when the staging buffer is filled to at least a threshold amount of data to thereby improve efficacy of the DMA transfer performance. Other criteria may also be employed to determine when to start the DMA circuit.

Abstract: A method and system for accessing a computer system memory without processor intervention is disclosed. In one embodiment, the method includes initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface. The predetermined communication protocol enables an access operation to be performed on the first or second memory without intervention by the first or second processor. In one embodiment, the predetermined communication protocol utilizes a plurality of predefined packet types which are identified by a packet header decoder.