Direct Memory Accessing (dma) Patents (Class 710/22)
  • Patent number: 10838896
    Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: November 17, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Brian Jason Karguth, Charles Lance Fuoco, Samuel Paul Visalli, Michael Anthony Denio
  • Patent number: 10838654
    Abstract: When contents of UFSHCI standard are directly implemented in a UFS host, a problem may occur such that read/write operations of a UFS device stop or contents of data are destroyed. A semiconductor device has a UFS host controller that performs data transfer with a universal flash storage (UFS) device. The semiconductor device includes a Run-Stop register that sets the UFS host controller into a processing possible state, a Door bell register that instructs the UFS host controller to perform transfer, and a ready bit that indicates whether or not the UFS host controller can perform processing of transfer request. When the Run-Stop register is cleared while the data transfer is in process, the UFS host controller prevents a next data transfer from being registered until the data transfer is completed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 17, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Daisuke Mizoguchi
  • Patent number: 10788991
    Abstract: Providing access to a data storage resource. A storage subsystem comprising one or more storage address units and is associated with one or more access interfaces is identified. An address-interface correlation guideline is identified that defines a combination of rules that govern which access interfaces are used to access storage address units. A target address unit identification is received from a requesting system. A processor determines which storage address units a requesting system requests to access to based on the received target address unit identification. The target address unit identification is associated with at least one of the storage address units. The requesting system is provided with access to the storage address units using access interfaces that are determined based on a target interface conclusion.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sergio Reyes, Brian C. Twichell
  • Patent number: 10783103
    Abstract: A signature is generated to indicate a direct memory access (DMA) operation involving a transfer, by a DMA engine, of data between a host memory circuit and an endpoint memory circuit of an endpoint processor circuit. First descriptors of the DMA engine are defined relative to the endpoint memory circuit or host memory circuit. A signature is received that indicates that second descriptors have been configured by the endpoint processor circuit. In response to receiving the endpoint signature, the DMA engine is enabled to begin the DMA operation.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 22, 2020
    Assignee: Xilinx, Inc.
    Inventors: Sunita Jain, Bharat Kumar Gogada, Ravikiran Gummaluri
  • Patent number: 10769086
    Abstract: A recording medium to be used by being connected to a digital device includes a local bus, a plurality of recording units, an information storage unit, and a communication unit. The local bus has a plurality of switches or bridges. The plurality of recording units are connected to the local bus. The information storage unit stores information indicating a bus configuration of the local bus. The communication unit is used for transferring the information to and from the digital device. After the recording medium is inserted into the digital device, the bus configuration of the local bus is reconstructed based on the information acquired from the communication unit via the information storage unit by the digital device.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: September 8, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hideaki Yamashita, Takeshi Otsuka, Masanori Mitsuzumi
  • Patent number: 10761733
    Abstract: A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: September 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 10761982
    Abstract: An efficient data storage device is disclosed, which uses a microprocessor and at least one volatile memory to operate a non-volatile memory. The microprocessor allocates the volatile memory to provide a cache area. According to an asynchronous event request (AER) issued by a host, the microprocessor uses the cache area to collect sections of write data requested by the host, programs the sections of write data collected in the cache area to the non-volatile memory together, and reports failed programming of the sections of write data to the host by AER completion information.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 1, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Ming-Hung Chang, Fang-I Peng
  • Patent number: 10740150
    Abstract: Method and system are disclosed for a programmable state machine controller in a parallel processing system. The programmable state machine controller includes a set of control registers configured to serve a set of application specific engines; a set of task engines configured to access a plurality of application resources in parallel; one or more processors configured to: receive multiple requests from the set of application specific engines, determine availability of the set of task engines and the plurality of application resources being requested, assign the set of task engines to serve the set of application specific engines based on the availability of the set of task engines and the availability of the plurality of application resources being requested, and serve the multiple requests from the set of application specific engines in parallel.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: August 11, 2020
    Assignee: X-Drive Technology, Inc.
    Inventor: Darder Chang
  • Patent number: 10725946
    Abstract: In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communica
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 28, 2020
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, Wade Andrew Butcher
  • Patent number: 10725861
    Abstract: System and techniques for error correction code (ECC) memory security are described herein. A write request that includes data is received. An integrity check value (ICV) is computed for the data. Then, the write request is performed, including writing a representation of the data to a data area in memory and writing the ICV into an ECC area in memory. Here, the data area is addressable by a host and the ECC area corresponds to the data area via hardware of the memory.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Anatoli Bolotov, Mikhail Grinchuk, Rajat Agarwal
  • Patent number: 10725909
    Abstract: According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kosuke Yanagidaira, Shouichi Ozaki
  • Patent number: 10705974
    Abstract: A data processing method and a storage apparatus are disclosed. The data processing method includes: receiving, by a non-volatile memory express (NVMe) storage device, an NVMe write command sent by a host, where the NVMe write command carries a key and a value pointer, the value pointer points to first storage space, and the first storage space is used to store a value; obtaining, by the NVMe storage device, the key from the NVMe write command and a value length, and allocating second storage space to the value according to the value length, where the second storage space is in the NVMe storage device; and obtaining, by the NVMe storage device, the value from the host, and storing the value in the second storage space.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: July 7, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xin Qiu, Huifeng Xu, Haitao Guo, Hongguang Liu, Huawei Liu, Chunyi Tan, Victor Gissin
  • Patent number: 10705952
    Abstract: Systems, methods, and/or devices are used to store metadata in a storage system. In one aspect, a first user space module sends a logical memory request to a memory management module of a kernel space module. The logical memory request includes data and metadata. A second user space module obtains the metadata of the logical memory request. A storage engine of the second user space module determines, in accordance with the obtained metadata, a location in non-volatile memory for the data. A second user space module generates a physical memory request including an indication of the non-volatile memory for the data. The second user space module transmits the physical memory request to the kernel space memory management module.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Vishal Kanaujia, Ramesh Chander, Manavalan Krishnan, Brian W. O'Krafka, Johann George
  • Patent number: 10698616
    Abstract: Embodiments disclosed herein provide systems, methods, and computer readable media for storing data to a plurality of physical storage volumes. In a particular embodiment, a method provides identifying first data for storage on the plurality of physical storage volumes. Each of the plurality of storage volumes corresponds to respective ones of a plurality of data channels. The method further provides segmenting the first data into a plurality of data segments corresponding to respective ones of the plurality of data channels and transferring the plurality of data segments as respective bit streams over the respective ones of the plurality of data channels to the respective ones of the plurality of physical storage volumes. The plurality of storage volumes stores the respective bit streams in the exact condition in which the bit streams are received.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 30, 2020
    Assignee: Quantum Corporation
    Inventors: Suayb S. Arslan, Turguy Goker, Jaewook Lee
  • Patent number: 10698785
    Abstract: A computer-implemented method, a computer program product, and a computer system for parallel task management. A computer system receives a new task that requests to access a resource may be received. In response to an access workload being above a first threshold, the computer system dispatches the new task to at least one predefined processing unit, wherein the access workload may be associated with the resource that is in parallel accessed by a plurality of existing tasks.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ping Ping Cheng, Jun Hua Gao, Guan Jun Liu, Xue Yong Zhang, Xi Bo Zhu, Bei Chun Zhou
  • Patent number: 10698819
    Abstract: A memory system may include: a nonvolatile memory device including a memory cell array and a page buffer coupled to the memory cell array; and a controller configured to interface with the nonvolatile memory device, wherein the controller moves descriptors on a cache command from a command queue to a cache queue, the cache command being transferred to the nonvolatile memory device, and selectively moves the descriptors moved to the cache queue to a response queue.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventor: Beom Rae Jeong
  • Patent number: 10691404
    Abstract: Technologies for cryptographic protection of I/O audio data include a computing device with a cryptographic engine and an audio controller. A trusted software component may request an untrusted audio driver to establish an audio session with the audio controller that is associated with an audio codec. The trusted software component may verify that a stream identifier associated with the audio session received from the audio driver matches a stream identifier received from the codec. The trusted software may program the cryptographic engine with a DMA channel identifier associated with the codec, and the audio controller may assert the channel identifier in each DMA transaction associated with the audio session. The cryptographic engine cryptographically protects audio data associated with the audio session. The audio controller may lock the controller topology after establishing the audio session, to prevent re-routing of audio during a trusted audio session. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Sudha Krishnakumar, Reshma Lal, Pradeep M. Pappachan, Kar Leong Wong, Steven B. McGowan, Adeel A. Aslam
  • Patent number: 10693478
    Abstract: A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 23, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jui-Chang Tsao, Chen-Kuo Hwang, Po-Wei Liu
  • Patent number: 10684795
    Abstract: A storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a first region and a second region. The controller classifies a plurality of read requests for reading data from the nonvolatile semiconductor memory into first read requests for reading data from the first region and second read requests for reading data from the second region, pairs one of the first read requests with one of the second read requests to generate a third read request, and outputs the third read request to the nonvolatile semiconductor memory.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshihisa Kojima
  • Patent number: 10672440
    Abstract: Aspects of the present disclosure include a memory sub-system configured to reduce latency and power consumption during a read-write cycle. The memory system comprises a first memory component and a processing device operatively coupled to the first memory component. The processing device is configured to receive a request to write a first sequence of data bits from a first data block of a second memory component to memory media of the first memory component. In response to receiving the request, the processing device reads a second sequence of data bits from a second data block stored in the memory media of the first memory component, and compares the first sequence of data bits with the second sequence of data bits.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jeffrey Frederiksen
  • Patent number: 10664418
    Abstract: A peripheral device controlling device according to an embodiment of the inventive concept includes a command queue for storing at least one Device to Device (D2D) command for data communication between a first peripheral device and a second peripheral device, a command parser for obtaining information related to the data communication from the at least one D2D command, and an orchestrator for controlling at least one of the first peripheral device and the second peripheral device to transfer data from the first peripheral device to the second peripheral device based on the acquired information.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 26, 2020
    Assignee: Seoul National University R&DB Foundation
    Inventors: JangWoo Kim, JaeHyung Ahn, DongUp Kwon
  • Patent number: 10656956
    Abstract: Disclosed herein are a virtual desktop server for supporting high-quality graphics processing and a method for processing high-quality graphics using the virtual desktop server. The virtual desktop server includes one or more virtual desktops for creating instructions for accelerated graphics processing by running a high-quality graphics application, one or more hardware-based graphics accelerators for creating screen data by executing the instructions for accelerated graphics processing and for storing the created screen data in a frame buffer, and a hypervisor for transmitting the screen data received from the virtual desktop to a client over a network, and the virtual desktop captures the screen data stored in the frame buffer, converts the captured screen data, and delivers the converted screen data to the hypervisor.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: May 19, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Soo-Cheol Oh, Dae-Won Kim, Sun-Wook Kim, Jae-Geun Cha, Ji-Hyeok Choi, Seong-Woon Kim
  • Patent number: 10642766
    Abstract: A direct memory access (DMA) device provides for transforming source data as it is transferred to a destination memory space. The transformation can encompass a range of arithmetic logic unit (ALU) operations. The transformation can include discerning comparative matches in the source address space, such that matched-indice-reference-offsets are transferred to destination memory. A processor requesting the transfer can also configure the transformation to be completed by writing configuration data to memory and/or programming the DMA device. In transforming data as it is transferred, the DMA device can obviate time-consuming processing otherwise done after conventional DMA transfers.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: May 5, 2020
    Inventor: Daniel Kilsdonk
  • Patent number: 10635469
    Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: April 28, 2020
    Assignee: Dynavisor, Inc.
    Inventor: Sreekumar Nair
  • Patent number: 10635613
    Abstract: The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Frank F. Ross, Robert M. Walker
  • Patent number: 10613887
    Abstract: Dynamically setting the order of optimization of physical hosts allows more efficient and varied optimization. An ordering policy mechanism utilizes ordering policies to set an order for the optimizer to optimize physical the hosts. The ordering policy mechanism may allow a system administrator to create and/or select ordering policies. The ordering policies may include fixed ordering policies or dynamic ordering policies.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joseph W. Cropper, Jennifer D. Mulsow, Taylor D. Peoples
  • Patent number: 10613889
    Abstract: Dynamically setting the order of optimization of physical hosts allows more efficient and varied optimization. An ordering policy mechanism utilizes ordering policies to set an order for the optimizer to optimize physical the hosts. The ordering policy mechanism may allow a system administrator to create and/or select ordering policies. The ordering policies may include fixed ordering policies or dynamic ordering policies.
    Type: Grant
    Filed: January 9, 2016
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joseph W. Cropper, Jennifer D. Mulsow, Taylor D. Peoples
  • Patent number: 10616068
    Abstract: Based on a request to identify a networking component, a first application programming interface (API) signature is selected from a plurality of API signatures within a priority list that associates the first API signature with a corresponding first API type, wherein the first API signature includes a first characteristic. A first API implemented by the networking component is tested to determining whether the first API implemented by the networking component exhibits the first characteristic. A determination is made of whether the networking component implements the first API type based on determining that the first API implemented by the networking component exhibits the first characteristic.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 7, 2020
    Assignee: CA, Inc.
    Inventor: Michael Paul Shevenell
  • Patent number: 10607392
    Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 31, 2020
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
  • Patent number: 10599197
    Abstract: An integrated circuit (IC) package of an electronic device includes a first input coupled to a first voltage rail and a second input coupled to a second voltage rail. The IC package further includes a set of one or more input/output (IO) pad cells and a power sequence detector coupled to the first and second voltage rails. The power sequence detector monitors the first and second voltage rails and configures the set of one or more IO pad cells to operate at one of a non-zero first voltage level or a non-zero second voltage level depending on which of the first voltage rail and the second voltage rail ramps up to a corresponding specified voltage level first.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: March 24, 2020
    Assignee: NXP USA, INC.
    Inventors: Haku Sato, Robert Greenwood, Paul M. Herbst
  • Patent number: 10599568
    Abstract: Techniques for managing multi-level memory and coherency using a unified page granular controller can simplify software programming of both file system handling for persistent memory and parallel programming of host and accelerator and enable better software utilization of host processors and accelerators. As part of the management techniques, a line granular controller cooperates with a page granular controller to support both fine grain and coarse grain coherency and maintain overall system inclusion property. In one example, a controller to manage coherency in a system includes a memory data structure and on-die tag cache to store state information to indicate locations of pages in a memory hierarchy and an ownership state for the pages, the ownership state indicating whether the pages are owned by a host processor, owned by an accelerator device, or shared by the host processor and the accelerator device.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventor: Eran Shifer
  • Patent number: 10592436
    Abstract: Secure memory allocation technologies are described. A processor includes a processor core and a memory controller that is coupled between the processor core and main memory. The main memory comprises a protected region including secured pages. The processor, in response to a content copy instruction, is to initialize a target page in the protected region of an application address space. The processor, in response to the content copy instruction, is also to select content of a source page in the protected region to be copied. The processor, in response to the content copy instruction, is also to copy the selected content to the target page in the protected region of the application address space.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Francis X. McKeen, Carlos V. Rozas, Krystof C. Zmudzinski
  • Patent number: 10579306
    Abstract: A memory management method is provided. The method includes storing an acquired first command into a command queue, and setting a command phase value of the first command according to a current command phase, wherein in response to determining that the first command is a flush command, calculating a command phase count value corresponding to the current command phase, and adjusting the current command phase; selecting a new target command from the command queue, and executing the target command according to a target command phase value of the target command and a corresponding target command phase count value, wherein the target command phase count value which is not a preset value is adjusted; determining, according to the adjusted target command phase count value, whether to respond to a host system that an execution of a target flush command corresponding to the target command phase value is completed.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: March 3, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Shang-Pin Huang, Hung-Chih Hsieh, Yu-Hua Hsiao
  • Patent number: 10579559
    Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes a core, a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory, and a stall circuit coupled to the core configured to stall or resume the core in response to one or more inputs.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 3, 2020
    Assignee: XILINX, INC.
    Inventors: Goran H K Bilski, Juan J. Noguera Serra, Jan Langer, Baris Ozgul
  • Patent number: 10572260
    Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Joseph Nuzman, Jonas Svennebring, Doddaballapur N. Jayasimha, Samantika S. Sury, David A. Koufaty, Niall D. McDonnell, Yen-Cheng Liu, Stephen R. Van Doren, Stephen J. Robinson
  • Patent number: 10572401
    Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: February 25, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chad McBride, Jeffrey Bradford, Steven Wheeler, Christopher Johnson, Boris Bobrov, Andras Tantos
  • Patent number: 10560547
    Abstract: Provided is a communication apparatus and a relay protection apparatus, the communication apparatus supports at least one of communication protocols and provides functions of at least two dedicated communication profile components for each of the communication protocols, and the communication apparatus comprises: a configuration module for setting an operational parameter of the communication apparatus, wherein the operational parameter indicates that which one of the at least two dedicated communication profile components is used for the communication apparatus; a management module for causing the communication apparatus to operate as the one of the at least two dedicated communication profile components according to the configuration of the configuration module; and a communication function module for providing the functions of the at least two dedicated communication profile components, wherein the management module causes the communication apparatus to operate as the one of the at least two dedicated comm
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: February 11, 2020
    Assignee: Schneider Electric Industries SAS
    Inventor: Shaogang Wang
  • Patent number: 10552048
    Abstract: Memory systems may include a redundant array of independent disks (RAID) group including a plurality of disks, and a storage access layer including a RAID engine suitable for requesting data from the RAID group, determining whether a disk in the plurality of disks is busy based on a latency threshold, when the disk is determined to be busy, determining whether the requested data can be obtained from other non-busy disks in the plurality of disks, and obtaining the requested data when the data is determined to be obtainable from the other non-busy disks.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Tae Il Um, In Gu Kang, Mehryar Rahmatian
  • Patent number: 10552206
    Abstract: Contextual awareness associated with resources can be employed to facilitate controlling access to resources of a system, including function blocks. A resource manager component (RMC) can pre-load a defined number of respective versions of configuration parameter data associated with respective applications in each resource. With regard to each application, the RMC can associate a context value, unique for each application, with the respective versions of configuration parameter data associated with that application. When a current application is being changed to a next application, the RMC can write the context value associated with the next application to a context select component (CSC). Each resource can read the context value in the CSC, identify and retrieve the version of configuration parameter data associated with the next application based on the context value, and configure the function block based on the version of configuration parameter data.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 4, 2020
    Assignee: GE Aviation Systems LLC
    Inventors: Melanie Sue-Hanson Graffy, Colin Holmwood, Jon Marc Diekema
  • Patent number: 10545894
    Abstract: A processor includes a plurality of first processing units. A direct memory access unit is coupled to at least one first processing unit of the plurality of first processing units. The processor includes a plurality of data storage units. A second processing unit is adapted to process data from at least one data storage unit of the plurality of data storage units. The direct memory access unit is configured to transfer data stored in a memory to the at least one data storage unit of the plurality of data storage units. The second processing unit is separate from the plurality of first processing units and the direct memory access unit. The at least one first processing unit and the second processing unit are configured to work in parallel. The processor further includes a first register. The second processing unit is configured to receive an operation signal from the first register.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shyh-An Chi
  • Patent number: 10516740
    Abstract: A transport for data communication can be selected based on current data communication activity. A master device and a slave device can establish a control channel on one transport and one or more data channels. A master device can determine which transport should be used for the data channel(s) based on real-time status information about the data exchange and can coordinate with the slave device to switch the data channel(s) to a different transport when appropriate.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 24, 2019
    Assignee: Apple Inc.
    Inventors: Augustin Prats, Jason C. Conn
  • Patent number: 10515036
    Abstract: A memory management circuit includes a direct memory access (DMA) channel. The DMA channel includes logic configured to receive a buffer of data to be written using DMA. The DMA channel further includes logic to perform bit manipulation in real-time during a DMA write cycle of the first buffer of data.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: December 24, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Yong Yuenyongsgool, Stephen Bowling, Cobus van Eeden, Igor Wojewoda, Naveen Raj
  • Patent number: 10511455
    Abstract: A time-sensitive networking system includes gate control circuits configured to control egress of data from multiple queues, respectively. A list execution circuit configures gate states of the plurality of gate control circuits based on a current gate control list that specifies a sequence of operations. Each operation specifies the gate states of the gate control circuits. A cycle timer circuit transmits a timing signal that signals to start a gating cycle by the list execution circuit. A list configuration circuit inputs a new gate control list and establishes the new gate control list as the current gate control list. The list configuration circuit transmits an initial cycle start signal directly to the list execution circuit, bypassing the cycle timer circuit, in response to completion of establishing the new gate control list as the current gate control list.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 17, 2019
    Assignee: XILINX, INC.
    Inventors: Ravinder Sharma, Ramesh R. Subramanian, Ashish Banga
  • Patent number: 10496388
    Abstract: Technologies for performing a secure firmware update include a compute device that includes a memory device to store firmware update payload, one or more devices that have direct memory access (DMA) to the memory, a DMA remap module, and a firmware update module. The DMA remap module is to create a memory isolation domain for each of the one or more devices. Each memory isolation domain comprises a physical address space in the memory that is mutually exclusive to the physical address spaces of the other memory isolation domains. The firmware update module is to (i) analyze the firmware update payload to identify one or more of the devices associated with the firmware update payload and (ii) move the firmware update payload to the memory isolation domains of each associated device to enable secure transmission of the firmware update payload to the associated devices.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Nicholas J. Adams, Krishnakumar Narasimhan, Vincent J. Zimmer
  • Patent number: 10496444
    Abstract: By assigning a physically continuous memory area to a virtual storage apparatus operated on an OS, the performance of the virtual storage apparatus is secured. A processor operates an OS, and the processor executes a plurality of processes on the OS. The plurality of processes includes a first virtual storage apparatus. The first virtual storage apparatus executes an I/O process, and includes a cache for storing data that is subjected to the I/O process. The processor assigns a resource in a computer to the plurality of processes, and the processor creates area information that indicates physical addresses assigned to the processes in a memory. On the basis of the area information, the processor selects a continuous area, which is a physically continuous area from the memory and assigns the continuous area to the cache.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: December 3, 2019
    Assignee: HITACHI, LTD.
    Inventors: Sachie Tajima, Masakuni Agetsuma, Takanobu Suzuki, Akihiko Araki
  • Patent number: 10489088
    Abstract: A storage device includes a nonvolatile semiconductor memory module, and a host interface for connection to a host that is external to the storage device. The host interface includes a first interface circuit conforming to Serial Peripheral Interface (SPI) and a second interface circuit conforming to an interface standard different from SPI. Output terminals of the first interface circuit are connected to input terminals of the second interface circuit, and output terminals of the second interface circuit are connected to input terminals of the nonvolatile semiconductor memory module.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: November 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shunsuke Kodera, Yoshio Furuyama
  • Patent number: 10482044
    Abstract: To realize DMA data transfer between a host computer and another computer even in the case that the host computer and the another computer are each equipped with a CPU, a memory, and so forth independently. A computer communicably connected with a first computer including a first memory and a driver for controlling a device, the computer comprising: the device; and a second memory, wherein a first DMA transfer is executed based on a DMA transfer request received from the driver, a second DMA transfer is executed to transfer data existing at a transfer destination address of the first DMA transfer between the first memory and the second memory, and the transfer destination address is detected as a result of executing the first DMA transfer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: November 19, 2019
    Assignee: NEC CORPORATION
    Inventor: Masahiko Takahashi
  • Patent number: 10474598
    Abstract: A microcomputer is provided for each of industrial apparatuses to synchronously control them and includes a CPU, a peripheral module, and a communication interface. The peripheral module controls an external apparatus based on a specified control parameter. The communication interface includes a time register that is synchronized with the other apparatuses in time series. The communication interface issues a CPU interrupt and a peripheral module interrupt to the CPU and the peripheral module, respectively, if a successively settled correction time matches the time register. In response to the peripheral module interrupt, the peripheral module changes the control parameter from a current value to an update value. In response to the CPU interrupt, the CPU starts an update program to calculate the next update value for the control parameter and writes the calculated value to the peripheral module.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Suzuki, Yuichi Takitsune
  • Patent number: 10474648
    Abstract: Metadata is stored within a database for each of a plurality of objects in different frames associated with a structure descriptor (e.g., a container directory entry, etc.). The frames are part of a metadata page and each comprising an object and a header specifying a version identifier for the object and a size of the object. The structure descriptor initially is built for a first build identifier. Thereafter, upon the structure descriptor changing from the first build identifier to a second build identifier, at least one of the objects that require migration is identified. The identification is based on the version identifier for the object being different from the second build identifier. In response, the identified objects are migrated from their corresponding frame to a new frame. The new frame includes the objects and new headers that include a version identifier equal to the second build identifier.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: November 12, 2019
    Assignee: SAP SE
    Inventors: Ivan Schreter, Dirk Thomsen
  • Patent number: 10474600
    Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Krishna T. Malladi, Hongzhong Zheng