Direct Memory Accessing (dma) Patents (Class 710/22)
  • Patent number: 11550586
    Abstract: A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: January 10, 2023
    Assignee: Deep Vision Inc.
    Inventors: Mohamed Shahim, Raju Datla, Rehan Hameed, Shilpa Kallem
  • Patent number: 11550660
    Abstract: A method includes providing an interposition driver, and context switching into a kernel associated with a persistent memory using the interposition driver to create a consistent view of the persistent memory.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 10, 2023
    Assignee: Red Hat, Inc.
    Inventor: Jeffrey E. Moyer
  • Patent number: 11545062
    Abstract: In some examples, an electronic device comprises a voltage supply circuit to provide a reference voltage usable to discharge pixels in a display device; and a scaler circuit coupled to the voltage supply circuit. The scaler circuit is to buffer first and second frames and dynamically control the voltage supply circuit to modify the reference voltage based on a frequency of the first frame differing from a frequency of the second frame.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: January 3, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yi-Fan Lin, Kai-Chieh Chang, Chang-Chih Yeh
  • Patent number: 11544194
    Abstract: A method of performing a copy-on-write on a shared memory page is carried out by a device communicating with a processor via a coherence interconnect. The method includes: adding a page table entry so that a request to read a first cache line of the shared memory page includes a cache-line address of the shared memory page and a request to write to a second cache line of the shared memory page includes a cache-line address of a new memory page; in response to the request to write to the second cache line, storing new data of the second cache line in a second memory and associating the second cache-line address with the new data stored in the second memory; and in response to a request to read the second cache line, reading the new data of the second cache line from the second memory.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: January 3, 2023
    Assignee: VMware, Inc.
    Inventors: Irina Calciu, Andreas Nowatzyk, Pratap Subrahmanyam
  • Patent number: 11544395
    Abstract: A system and method for providing transactional data privacy while maintaining data usability, including the use of different obfuscation functions for different data types to securely obfuscate the data, in real-time, while maintaining its statistical characteristics. In accordance with an embodiment, the system comprises an obfuscation process that captures data while it is being received in the form of data changes at a first or source system, selects one or more obfuscation techniques to be used with the data according to the type of data captured, and obfuscates the data, using the selected one or more obfuscation techniques, to create an obfuscated data, for use in generating a trail file containing the obfuscated data, or applying the data changes to a target or second system.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: January 3, 2023
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Shenoda Guirguis, Alok Pareek, Stephen Wilkes
  • Patent number: 11537457
    Abstract: A method of offloading performance of a workload includes receiving, on a first computing system acting as an initiator, a first function call from a caller, the first function call to be executed by an accelerator on a second computing system acting as a target, the first computing system coupled to the second computing system by a network; determining a type of the first function call; and generating a list of parameter values of the first function call.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: December 27, 2022
    Assignee: INTEL CORPORATION
    Inventors: Pradeep Pappachan, Sujoy Sen, Joseph Grecco, Mukesh Gangadhar Bhavani Venkatesan, Reshma Lal
  • Patent number: 11531623
    Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Jayanth N. Rao, Murali Sundaresan
  • Patent number: 11520717
    Abstract: An integrated circuit having a data processing engine (DPE) array can include a plurality of memory tiles. A first memory tile can include a first direct memory access (DMA) engine, a first random-access memory (RAM) connected to the first DMA engine, and a first stream switch coupled to the first DMA engine. The first DMA engine may be coupled to a second RAM disposed in a second memory tile. The first stream switch may be coupled to a second stream switch disposed in the second memory tile.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: December 6, 2022
    Assignee: Xilinx, Inc.
    Inventors: David Clarke, Peter McColgan, Zachary Dickman, Jose Marques, Juan J. Noguera Serra, Tim Tuan, Baris Ozgul, Jan Langer
  • Patent number: 11520906
    Abstract: A computer-readable medium comprises instructions that, when executed, cause a processor to execute an untrusted workload manager to manage execution of at least one guest workload.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: David M. Durham, Siddhartha Chhabra, Ravi L. Sahita, Barry E. Huntley, Gilbert Neiger, Gideon Gerzon, Baiju V. Patel
  • Patent number: 11513716
    Abstract: A technique for maintaining synchronization between two arrays includes assigning one array to be a preferred array and the other array to be a non-preferred array. When write requests are received at the preferred array, the writes are applied locally first and then applied remotely. However, when write requests are received at the non-preferred array, such writes are applied remotely first and then applied locally. Thus, writes are applied first on the preferred array and then on the non-preferred array, regardless of whether the writes are initially received at the preferred array or the non-preferred array.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: November 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Nagasimha Haravu, Alan L. Taylor, David Meiri, Dmitry Nikolayevich Tylik
  • Patent number: 11507298
    Abstract: Example computational storage systems and methods are described. In one implementation, a storage drive controller includes a non-volatile memory subsystem to process multiple commands. Multiple versatile processing arrays are coupled to the non-volatile memory subsystem. The multiple versatile processing arrays can process multiple in-situ tasks. A host direct memory access module provides direct access to at least one memory device.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: November 22, 2022
    Assignee: PETAIO INC.
    Inventors: Fan Yang, Changyou Xu, Lingqi Zeng
  • Patent number: 11500440
    Abstract: Examples include a computing system including a network input/output (I/O) device, the network I/O device including a microcontroller, a network controller, and a proxy mode monitor to enter a proxy mode by causing transfer of control of the network controller from a processor to the microcontroller without resetting the network controller, and to exit the proxy mode by causing transfer of control of the network controller from the microcontroller to the processor without resetting the network controller.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Boon Leong Ong, Girish J. Shirasat, Suraj A. Gajendra, Alok Anand
  • Patent number: 11483853
    Abstract: Methods, systems, and devices for wireless communications are described for identifying a file having a set of packets that are configured to be processed together. The base station may determine a segmentation scheme for the file based on a size of the file and identify a batch of assignments for communicating the file via a batch of transmissions based on the segmentation scheme. The base station may communicate the file via the batch of transmissions with a user equipment (UE) during the batch of assignments. Additional techniques are described herein for a UE to identify that the UE is storing a file in a buffer at the UE. The UE may transmit an indication to the base station that the buffer includes the file. In some cases, the UE may indicate a size of the file.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: October 25, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Prashanth Haridas Hande, Wanshi Chen, Linhai He, Naga Bhushan, Jay Kumar Sundararajan
  • Patent number: 11475152
    Abstract: A computer system for securing computer files from modification may include a processor; a first data storage area operatively coupled to the processor; a non-volatile second data storage area; and a control circuit. The second data storage area may be physically separate from the first data storage area. The second data storage area may store files that are executable by the processor, including executable files of an operating system configured to save temporary files on the at least a first data storage area. The control circuit may operatively couple the second data storage area to the processor, and may be operable in a first mode configured to block commands received from the processor and configured to modify the second data storage area from being communicated to the second data storage area. In a second mode, all commands may be allowed to the first and second data storage areas.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: October 18, 2022
    Assignee: CRU Data Security Group, LLC
    Inventors: Larry Hampel, Randal Barber
  • Patent number: 11461041
    Abstract: A storage device includes; a nonvolatile storage including a first region and a second region, a storage controller controlling operation of the nonvolatile storage, and a buffer memory connected to the storage controller. The storage controller stores user data received from a host device in the second region, stores metadata associated with management of the user data and generated by a file system of the host device in the first region, loads the metadata from the first region to the buffer memory in response to address information for an index node (inode) associated with the metadata, and accesses the target data in the second region using the metadata loaded to the buffer memory.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junghoon Kim, Seonghun Kim, Hongkug Kim, Sojeong Park
  • Patent number: 11461052
    Abstract: A storage system has two submission queue doorbell registers associated with a submission queue in a host. The storage system fetches and executes a command from the submission queue only in response to both submission queue doorbell registers being written. The second submission queue doorbell register may be visible (and directly written to) by the host or invisible (and indirectly written to) by the host. The use of two submission queue doorbell registers for a single submission queue can be used as a protection mechanism to protect an administration command submission queue of a child controller in a multiple physical function Non-Volatile Memory Express (NVMe) device (MFND).
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: October 4, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11455264
    Abstract: During a memory reallocation process, it is determined that a set of memory pages being reallocated are each enabled for a Direct Memory Access (DMA) operation. Prior to writing initial data to the set of memory pages, a pre-access delay is performed concurrently for each memory page in the set of memory pages.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: September 27, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jaime Jaloma, Mark Rogers, Arnold Flores, Gaurav Batra
  • Patent number: 11422861
    Abstract: A data processing method implemented by a computer device, includes generating a target task including a buffer application task or a buffer release task, when the target task is the buffer application task, a first buffer corresponding to the buffer application task is used when the second task is executed, or when the target task is the buffer release task, a second buffer corresponding to the buffer release task is used when the first task is executed, obtaining a buffer entry corresponding to the target task after a preceding task of the target task is executed and before a successive task of the target task is executed, where the buffer entry includes a memory size of a buffer corresponding to the target task, a memory location of the buffer, and a memory address of the buffer, and executing the target task to apply for or release the buffer.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: August 23, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiong Gao, Wei Li, Ming Zheng, Hou Fun Lam
  • Patent number: 11409636
    Abstract: The present disclosure discloses a debug unit, comprising: a write register configured to store kernel write data written by a kernel of a processor, wherein the processor is communicatively coupled to a debugger configured to read the kernel write data, wherein the kernel write data is associated with a kernel write flag bit to indicate data validity of the kernel write data; and a control unit including circuitry configured to control access to the write register by the kernel of the processor and the debugger based on data validity indicated by the kernel write flag bit. The present disclosure further discloses a corresponding processor including the debug unit, a corresponding debugger communicatively coupled to the processor, and a corresponding debug system including the processor coupled to the debugger.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 9, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Taotao Zhu, Chen Chen
  • Patent number: 11411885
    Abstract: A user can set or modify operational parameters of a data volume stored on a network-accessible storage device in a data center. For example, the user may be provided access to a data volume and may request a modification to the operational parameters of the data volume. Instead of modifying the existing data volume, the data center can provision a new data volume and migrate data stored on the existing data volume to the new data volume. While the data migration takes place, the existing data volume may block input/output (I/O) requests and the new data volume may handle such requests instead. Once the data migration is complete, the data center may deallocate the data blocks of the existing data volume such that the data blocks can be reused by other data volumes.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: August 9, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Pieter Kristian Brouwer, Marc Stephen Olson, Nachiappan Arumugam, Michael Thacker, Vijay Prasanth Rajavenkateswaran, Arpit Tripathi, Danny Wei
  • Patent number: 11410264
    Abstract: Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: James E. Akiyama, John Howard, Murali Ramadoss, Gary K. Smith, Todd M. Witter, Satish Ramanathan, Zhengmin Li
  • Patent number: 11379595
    Abstract: Masking a data rate of transmitted data is disclosed. As data is transmitted from a production site to a secondary site, the data rate is masked. Masking the data rate can include transmitting at a fixed rate, a random rate, or an adaptive rate. Each mode of data transmission masks or obscures the actual data rate and thus prevents others from gaining information about the data or the data owner from the data transfer rate.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: July 5, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Amos Zamir, Jehuda Shemer, Kfir Wolfson
  • Patent number: 11379394
    Abstract: A hardware based block moving controller of an active device such as an implantable medical device that provides electrical stimulation reads a parameter data from a block of memory and then writes the parameter data to a designated register set of a component that performs an active function. The block of memory may include data that specifies a size of the block of memory to be moved to the register set. The block of memory may also include data that indicates a number of triggers to skip before moving a next block of memory to the register set. A trigger that causes the block moving controller to move the data from the block of memory to the register set may be generated in various ways such as through operation of the component having the register set or by a separate timer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: July 5, 2022
    Assignee: MEDTRONIC, INC.
    Inventors: Robert W. Hocken, Wesley A. Santa, Christopher M. Arnett, Jalpa S. Shah, Joel E. Sivula
  • Patent number: 11373013
    Abstract: Technologies for secure I/O include a compute device having a processor, a memory, an input/output (I/O) device, and a filter logic. The filter logic is configured to receive a first key identifier from the processor, wherein the first key identifier is indicative of a shared memory range includes a shared key identifier range to be used for untrusted I/O devices and receive a transaction from the I/O device, wherein the transaction includes a second key identifier and a trust device ID indicator associated with the I/O device. The filter logic is further configured to determine whether the transaction is asserted with the trust device ID indicator indicative of whether the I/O device is assigned to a trust domain and determine, in response to a determination that the transaction is not asserted with the trust device ID indicator, whether the second key identifier matches the first key identifier.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 28, 2022
    Assignee: INTEL CORPORATION
    Inventors: Luis Kida, Krystof Zmudzinski, Reshma Lal, Pradeep Pappachan, Abhishek Basak, Anna Trikalinou
  • Patent number: 11372645
    Abstract: Deferred command execution by a command processor (CP) may be performed based on a determination that at least one command of a primary buffer is located between a first link of the primary buffer and a second link of the primary buffer. The first link and the second link may be to one or more secondary buffers that includes a set of commands. The CP may initiate, before executing, a fetch of a first set of commands in the set of commands based on the first link, a fetch of the at least one command of the primary buffer, and a fetch of a second set of commands in the set of commands based on the second link. After initiating the fetch of the second set of commands, the CP may execute the first set of commands, the at least one command of the primary buffer, and the second set of commands.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 28, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Nigel Poole, Joohi Mittal
  • Patent number: 11366444
    Abstract: To enable acquisition of operation information of CNC corresponding to periodic operation of PLC, even when the CNC is unable to respond due to the timing of machining, the loading status, etc. The PLC device includes: a special instruction control unit that sets, to a special instruction for acquiring operation information indicating an operation state of a control device from the control device controlling an industrial machine, a cyclic time for causing the control device to periodically acquire and retain the operation information in a case in which the control device is unable to respond, and transmits to the control device the special instruction in which the cyclic time is set; and an acquisition unit that acquires the operation information acquired on the basis of the cyclic time from the control device.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: June 21, 2022
    Assignee: FANUC CORPORATION
    Inventors: Nao Onose, Mitsuru Mochizuki
  • Patent number: 11354244
    Abstract: Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 7, 2022
    Assignee: Intel Germany GmbH & Co. KG
    Inventors: Ritesh Banerjee, Jiaxiang Shi, Ingo Volkening
  • Patent number: 11354260
    Abstract: Autonomous memory access (AMA) controllers and related systems, methods, and devices are disclosed. An AMA controller includes waveform circuitry configured to autonomously retrieve waveform data stored in a memory device and pre-process the waveform data without intervention from a processor. The AMA controller is configured to provide the pre-processed waveform data to one or more peripheral devices.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: June 7, 2022
    Assignee: Microchip Technology Incorporated
    Inventor: Jacob Lunn Lassen
  • Patent number: 11321249
    Abstract: Embodiments of the present invention include a drive-to-drive storage system comprising a host server having a host CPU and a host storage drive, one or more remote storage drives, and a peer-to-peer link connecting the host storage drive to the one or more remote storage drives. The host storage drive includes a processor and a memory, wherein the memory has stored thereon instructions that, when executed by the processor, causes the processor to transfer data from the host storage drive via the peer-to-peer link to the one or more remote storage drives when the host CPU issues a write command.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Oscar P. Pinto, Robert Brennan
  • Patent number: 11281610
    Abstract: Embodiments of the present disclosure relate to a method, a device, and a computer program product for managing data transfer. A method for managing data transfer is provided, including: if determining that a request to transfer a data block between a memory and a persistent memory of a data storage system is received, obtaining a utilization rate of a central processing unit of the data storage system; and determining, from a first transfer technology and a second transfer technology and at least based on the utilization rate of the central processing unit, a target transfer technology for transferring a data block between the memory and the persistent memory, the first transfer technology transferring data through direct access to the memory, and the second transfer technology transferring data through the central processing unit. Therefore, the embodiments of the present disclosure can improve the data transfer performance of the storage system.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 22, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Shuguang Gong, Long Wang, Tao Chen, Bing Liu
  • Patent number: 11275600
    Abstract: Distributed I/O virtualization includes receiving, at a first physical node in a plurality of physical nodes, an indication of a request to transfer data from an I/O device on the first physical node to a set of guest physical addresses. An operating system is executing collectively across the plurality of physical nodes. It further includes writing data from the I/O device to one or more portions of physical memory local to the first physical node. It further includes mapping the set of guest physical addresses to the written one or more portions of physical memory local to the first physical node.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: March 15, 2022
    Assignee: TidalScale, Inc.
    Inventors: Leon Dang, Keith Reynolds, Isaac R. Nassi
  • Patent number: 11269888
    Abstract: A data storage system implements techniques to efficiently store and retrieve structured data. For example, structured data is transformed into correlated segments, which are then redundancy coded and archived in a correlated fashion. The characteristics of the redundancy code used enable flexible handling of the archived data without excessive latency.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 8, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Umar Farooq, Rishabh Animesh
  • Patent number: 11262926
    Abstract: A computing system may generate a directed graph to access data stored in multiple locations or blocks of a data storage device or system. Cost values may be determined for each of multiple paths between nodes, representing the blocks or subsets of data. In some cases, nodes having a cost value between them that is less than a threshold may be combined into a single node. A master path, linking at least two of the multiple paths, between a start node and an end node, may be generated by iteratively selecting paths with a lowest cost. The number of paths considered for determining the lowest path cost may be limited by a complexity parameter, so as to optimize the path to access the data without introducing unbeneficial computational complexity.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: March 1, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Rishabh Animesh, Jan Dean Larroza Catarata, Siddharth Shah
  • Patent number: 11256459
    Abstract: This invention provides a data processing apparatus operable to execute processing requested by an application, where the apparatus comprises a processing unit configured to, if there is an instruction for processing, execute the processing in accordance with a command list indicated by the instruction; and a control unit configured to, upon receiving a request for processing from the application, generate a command list corresponding to the request and instruct the processing unit to perform the processing, wherein the processing unit comprises a switching unit configured to, upon receiving, from the control unit, a second instruction during execution of a command list for a first instruction, switch to execution of a command list for the second instruction at a timing of execution of a command that is a control point preset in the command list for the first instruction.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 22, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadayuki Ito
  • Patent number: 11249461
    Abstract: The present invention allows a communication mode in which to communicate with a detection section to be easily and conveniently changed in a motor control device. A slave device (90) includes: a network communication section (120) configured to communicate with a PLC (100) via a communication network; an FB signal obtaining section configured to obtain an FB signal from a detection section; and a setting communication section (140) configured to receive communication mode information of an FB through another communication path different from the communication network. The FB signal obtaining section includes a reconfigurable device and is capable of changing a communication mode of the FB signal obtaining section by reconfiguring the reconfigurable device. The slave device (90) reconfigures the reconfigurable device in accordance with the communication mode information in a case where the setting communication section (140) receives the communication mode information.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: February 15, 2022
    Assignee: OMRON CORPORATION
    Inventor: Takeshi Kiribuchi
  • Patent number: 11243714
    Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory storage to store data, a volatile memory storage, and a host interface layer to receive requests from a host machine. An SSD controller may manage reading data from and writing data to the flash memory storage, with a flash translation layer to translate between Logical Block Addresses and Physical Block Addresses, a flash memory controller to access the flash memory storage, a volatile memory controller to access the volatile memory storage, and an orchestrator to send instructions to a Data Movement Interconnect (DMI). The DMI may include at least two kernels, a Buffer Manager, a plurality of ring agents associated with the kernels and the Buffer Manager to handle messaging, a Data Movement Manager (DMM) to manage data movement, at least two data rings to move data between the ring agents, and a control ring to share commands and acknowledgments between the ring agents and the DMM.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: February 8, 2022
    Inventors: Ramdas P. Kachare, Jimmy K. Lau
  • Patent number: 11237970
    Abstract: A computing system, method and apparatus to cache a portion of a data block. A processor can access data using memory addresses in an address space. A first memory can store a block of data at a block of contiguous addresses in the space of memory address. A second memory can cache a first portion of the block of data identified by an item selection vector. For example, response to a request to cache the block of data stored in the first memory, the computing system can communicate the first portion of the block of data from the first memory to the second memory according to the item selection vector without accessing a second portion of the block of data. Thus, different data blocks in the first memory of a same size can be each cached in different cache blocks of different sizes in the second memory.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11238940
    Abstract: Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Pollio, Giuseppe Vito Portacci, Mauro Luigi Sali, Alessandro Magnavacca
  • Patent number: 11232053
    Abstract: A direct memory access (DMA) system can include a memory configured to store a plurality of host profiles, a plurality of interfaces, wherein two or more of the plurality of interfaces correspond to different ones of a plurality of host processors, and a plurality of data engines coupled to the plurality of interfaces. The plurality of data engines are independently configurable to access different ones of the plurality of interfaces for different flows of a DMA operation based on the plurality of host profiles.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: January 25, 2022
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Darren Jue, Ravi Sunkavalli, Akhil Krishnan, Tao Yu, Kushagra Sharma
  • Patent number: 11231987
    Abstract: A debugging tool, such as may take the form of a software daemon running in the background, can provide for the monitoring of utilization of access mechanisms, such as Direct Memory Access (DMA) mechanisms, for purposes such as debugging and performance improvement. Debugging tools can obtain and provide DMA utilization data, as may include statistics, graphs, predictive analytics, or other such information. The data can help to pinpoint issues that have arisen, or may arise, in the system, and take appropriate remedial or preventative action. Data from related DMAs can be aggregated intelligently, helping to identify bottlenecks where the individual DMA data might not. A debugging tool can store state information as snapshots, which may be beneficial if the system is in a state where current data is not accessible. The statistics and predictive analytics can also be leveraged to optimize system-performance.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 25, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Benita Bose, Ron Diamant, Georgy Zorik Machulsky, Alex Levin
  • Patent number: 11210393
    Abstract: A technology for mutually isolating accessors of a shared electronic device from leakage of context data after a context switch comprises: on making the shared electronic device available to the plurality of accessors, establishing a portion of storage as an indicator location for the shared electronic device; when a first accessor requests use of the shared electronic device, writing at least one device-reset-required indicator to the indicator location; on switching context to a new context, after context save, when a second accessor requests use of the shared electronic device, resetting context data of the shared electronic device to a known state and reconciling the first device-reset-required indicator and a second device-reset-required indicator for the new context.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 28, 2021
    Assignee: ARM IP LIMITED
    Inventors: Milosch Meriac, Alessandro Angelino
  • Patent number: 11210218
    Abstract: A method for memory address mapping in a disaggregated memory system includes receiving an indication of one or more ranges of host physical addresses (HPAs) from a compute node of a plurality of compute nodes, the one or more ranges of HPAs including a plurality of memory addresses corresponding to different allocation slices of the disaggregated memory pool that are allocated to the compute node. The one or more ranges of HPAs are converted into a contiguous range of device physical addresses (DPAs). For each DPA, a target address decoder (TAD) is identified based on a slice identifier and a slice-to-TAD index. Each DPA is mapped to a media-specific physical element of a physical memory unit of the disaggregated memory pool based on the TAD.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: December 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Siamak Tavallaei, Ishwar Agarwal, Vishal Soni
  • Patent number: 11199992
    Abstract: The present disclosure generally relates to a method and device for detecting patterns in host command pointers. When a new command is received by a storage device from a host computer, host command pointers sent to the storage device are analyzed to detect any patterns within the host command pointers. If a pattern is detected, the storage device can store the host command pointers in a reduced pointer storage structure. Thereafter, the storage device can perform the command indicated by the host command pointers using the reduced pointer storage structure.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 14, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Elkana Richter, Shay Benisty
  • Patent number: 11194745
    Abstract: One example method includes receiving an IO request from an application, determining if an affinity policy applies to the application that transmitted the IO request, when an affinity policy applies to the application, directing the IO request to a specified site of a replication system, when no affinity policy applies to the application, determining if a lag in replication of the IO request from a primary site to a replication site is acceptable, if a lag in replication of the IO request is acceptable, processing the IO request using performance based parameters and/or load balancing parameters, and if a lag in replication of the IO request is not acceptable, either directing the IO request to a most up to date replica site, or requesting a clone copy of a volume to which the IO request was initially directed and directing the IO request to the cloned copy.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: December 7, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mohamed Abdullah Gommaa Sohail, Said Tabet
  • Patent number: 11188486
    Abstract: The present disclosure relates to the technical field of a multi-chip system, and provides a master chip, a salve chip, and an inter-chip DMA transmission system. The master chip is connected to the slave chip through at least one first transmission channel (17) and a second transmission channel (18). The master chip includes a DMA controller (2) and an MCU (3). For each of the first transmission channels, when it is detected that any first transmission channel (17) is in an idle state, the MCU (3) configures one of a plurality of first peripherals (12) of the slave chip into a DMA mode. The DMA controller (2) is configured to receive, through the first transmission channel (17), a DMA request (req_s_0-req_s_N) generated by the first peripheral (12) in the DMA mode, and obtain a DMA data of the first peripheral (12) through the second transmission channel (18).
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 30, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Zhibing Liang, Yifan Li, Zekai Chen
  • Patent number: 11182092
    Abstract: The present disclosure provides a new and innovative system, methods and apparatus for PRI overhead reduction for virtual machine migration. In an example, a system includes a memory and a hypervisor. The memory includes a plurality of memory addresses on a source host. The hypervisor is configured to generate a migration page table associated with the memory. The hypervisor is also configured to receive a migration command to copy data from a portion of the memory to a destination host. A first range of memory addresses includes data copied from the portion of the memory and a second range of memory addresses includes data that is not copied. The hypervisor is also configured to modify the migration page table to include a page table entry associated with the first range of memory addresses being migrated from the source host to the destination host.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 23, 2021
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Amnon Ilan
  • Patent number: 11176064
    Abstract: Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn't require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 16, 2021
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Saurabh Garg, Vladislav V. Petkov
  • Patent number: 11169926
    Abstract: A memory system, a memory controller and an operating method of the memory controller. The memory controller may include a host interface configured to communicate with a host; a memory interface configured to communicate with a memory device; and a control circuit configured to control an operation of the memory device. The control circuit may selectively determine to use a cache for an operation indicated by a command received from the host, depending on a number of memory dies, of a plurality of memory dies in the memory device, detected to be in an activated state.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung-Gu Ji, Byeong-Gyu Park
  • Patent number: 11163513
    Abstract: An image forming apparatus includes a first processor, a second processor, a data transfer portion, a consistency determination portion, an abnormality determination portion, a re-transfer control portion, and an abnormality processing portion. The data transfer portion transfers data via a bus between a storage medium and the second processor. The consistency determination portion determines whether or not there is consistency between data before and after a transfer by the data transfer portion. The abnormality determination portion, upon determination that there is consistency, determines whether or not there is abnormality in the data transfer process. The re-transfer control portion, upon determination that there is no consistency, causes the data transfer portion to re-transfer the data.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: November 2, 2021
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Yuichi Sugiyama, Hideo Tanii
  • Patent number: 11163913
    Abstract: Technologies for secure I/O include a compute device having a processor, a memory, an input/output (I/O) device, and a filter logic. The filter logic is configured to receive a first key identifier from the processor, wherein the first key identifier is indicative of a shared memory range includes a shared key identifier range to be used for untrusted I/O devices and receive a transaction from the I/O device, wherein the transaction includes a second key identifier and a trust device ID indicator associated with the I/O device. The filter logic is further configured to determine whether the transaction is asserted with the trust device ID indicator indicative of whether the I/O device is assigned to a trust domain and determine, in response to a determination that the transaction is not asserted with the trust device ID indicator, whether the second key identifier matches the first key identifier.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Luis Kida, Krystof Zmudzinski, Reshma Lal, Pradeep Pappachan, Abhishek Basak, Anna Trikalinou