Direct Memory Accessing (dma) Patents (Class 710/22)
  • Patent number: 11188486
    Abstract: The present disclosure relates to the technical field of a multi-chip system, and provides a master chip, a salve chip, and an inter-chip DMA transmission system. The master chip is connected to the slave chip through at least one first transmission channel (17) and a second transmission channel (18). The master chip includes a DMA controller (2) and an MCU (3). For each of the first transmission channels, when it is detected that any first transmission channel (17) is in an idle state, the MCU (3) configures one of a plurality of first peripherals (12) of the slave chip into a DMA mode. The DMA controller (2) is configured to receive, through the first transmission channel (17), a DMA request (req_s_0-req_s_N) generated by the first peripheral (12) in the DMA mode, and obtain a DMA data of the first peripheral (12) through the second transmission channel (18).
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 30, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Zhibing Liang, Yifan Li, Zekai Chen
  • Patent number: 11182092
    Abstract: The present disclosure provides a new and innovative system, methods and apparatus for PRI overhead reduction for virtual machine migration. In an example, a system includes a memory and a hypervisor. The memory includes a plurality of memory addresses on a source host. The hypervisor is configured to generate a migration page table associated with the memory. The hypervisor is also configured to receive a migration command to copy data from a portion of the memory to a destination host. A first range of memory addresses includes data copied from the portion of the memory and a second range of memory addresses includes data that is not copied. The hypervisor is also configured to modify the migration page table to include a page table entry associated with the first range of memory addresses being migrated from the source host to the destination host.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 23, 2021
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Amnon Ilan
  • Patent number: 11176064
    Abstract: Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn't require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 16, 2021
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Saurabh Garg, Vladislav V. Petkov
  • Patent number: 11169926
    Abstract: A memory system, a memory controller and an operating method of the memory controller. The memory controller may include a host interface configured to communicate with a host; a memory interface configured to communicate with a memory device; and a control circuit configured to control an operation of the memory device. The control circuit may selectively determine to use a cache for an operation indicated by a command received from the host, depending on a number of memory dies, of a plurality of memory dies in the memory device, detected to be in an activated state.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung-Gu Ji, Byeong-Gyu Park
  • Patent number: 11163913
    Abstract: Technologies for secure I/O include a compute device having a processor, a memory, an input/output (I/O) device, and a filter logic. The filter logic is configured to receive a first key identifier from the processor, wherein the first key identifier is indicative of a shared memory range includes a shared key identifier range to be used for untrusted I/O devices and receive a transaction from the I/O device, wherein the transaction includes a second key identifier and a trust device ID indicator associated with the I/O device. The filter logic is further configured to determine whether the transaction is asserted with the trust device ID indicator indicative of whether the I/O device is assigned to a trust domain and determine, in response to a determination that the transaction is not asserted with the trust device ID indicator, whether the second key identifier matches the first key identifier.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Luis Kida, Krystof Zmudzinski, Reshma Lal, Pradeep Pappachan, Abhishek Basak, Anna Trikalinou
  • Patent number: 11163513
    Abstract: An image forming apparatus includes a first processor, a second processor, a data transfer portion, a consistency determination portion, an abnormality determination portion, a re-transfer control portion, and an abnormality processing portion. The data transfer portion transfers data via a bus between a storage medium and the second processor. The consistency determination portion determines whether or not there is consistency between data before and after a transfer by the data transfer portion. The abnormality determination portion, upon determination that there is consistency, determines whether or not there is abnormality in the data transfer process. The re-transfer control portion, upon determination that there is no consistency, causes the data transfer portion to re-transfer the data.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: November 2, 2021
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Yuichi Sugiyama, Hideo Tanii
  • Patent number: 11138132
    Abstract: Technologies for secure I/O data transfer with an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment. The trusted execution environment may generate an authentication tag based on a memory-mapped I/O transaction, write the authentication tag to a register of the accelerator, and dispatch the transaction to the accelerator. The accelerator performs a cryptographic operation associated with the transaction, generates an authentication tag based on the transaction, and compares the generated authentication tag to the authentication tag received from the trusted execution environment. The accelerator device may initialize an authentication tag in response to a command from the trusted execution environment, transfer data between host memory and accelerator memory, perform a cryptographic operation in response to transferring the data, and update the authentication tag in response to transferrin the data.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 5, 2021
    Assignee: INTEL CORPORATION
    Inventors: Reshma Lal, Alpa Narendra Trivedi, Luis Kida, Pradeep M. Pappachan, Soham Jayesh Desai, Nanda Kumar Unnikrishnan
  • Patent number: 11132319
    Abstract: Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Christopher Wing Hong Ngau, Hooi Kar Loo, Poh Thiam Teoh, Shashitheren Kerisnan, Maxim Dan, Chee Siang Chow
  • Patent number: 11134021
    Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: September 28, 2021
    Assignee: INTEL CORPORATION
    Inventors: Jonathan Kenny, Niall D. McDonnell, Andrew Cunningham, Debra Bernstein, William G. Burroughs, Hugh Wilkinson
  • Patent number: 11126522
    Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: September 21, 2021
    Assignee: NXP USA, Inc.
    Inventors: Benny Michalovich, Ron Bar, Eran Glickman, Dmitriy Shurin
  • Patent number: 11119704
    Abstract: In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Zhenyu Zhu, Mikal Hunsaker, Karthi R. Vadivelu, Rahul Bhatt, Kenneth P. Foust, Rajesh Bhaskar, Amit Kumar Srivastava
  • Patent number: 11106622
    Abstract: An operating system (OS) may communicate with a basic input/output system (BIOS) at OS runtime to inform the BIOS of a firmware update storage location. A method may begin with receiving, by an OS, an update for a firmware of an information handling system. The OS may select a memory for storage of the firmware update and may store the firmware update in the selected memory. The OS may then store a location of the firmware update in a portion of a memory accessible by both the OS and the BIOS.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 31, 2021
    Assignee: Dell Products L.P.
    Inventors: Krishnakumar Narasimhan, Santosh Hanamant Gore, Reveendra Babu Madala
  • Patent number: 11093180
    Abstract: A RAID storage multi-operation command system includes a RAID storage controller device that generates a multi-operation command including a multi-operation command role and a plurality of addresses, and transmits the multi-operation command, and also includes a RAID storage device that is coupled to the RAID storage controller device. The RAID storage device receives the multi-operation command from the RAID storage controller device, and identifies a plurality of operations that are associated in a database with the multi-operation command role included in the multi-operation command. The RAID storage device then performs the plurality of operations using the plurality of addresses included in the multi-operation command, which may include retrieving first data located in a first address, retrieving second data located in a second address, performing an XOR operation on the first and second data to produce third data, and writing the third data to one or more third addresses.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 17, 2021
    Assignee: Dell Products L.P.
    Inventors: Gary Benedict Kotzur, William Emmett Lynn, Kevin Thomas Marks, Chandrashekar Nelogal, James Peter Giannoules
  • Patent number: 11093276
    Abstract: Embodiments of the present disclosure provides systems and methods for batch accessing. The system includes a plurality of buffers configured to store data; a plurality of processor cores that each have a corresponding buffer of the plurality of buffers; a buffer controller configured to generate instructions for performing a plurality of buffer transactions on at least some buffers of the plurality of buffers; and a plurality of data managers communicatively coupled to the buffer controller, each data manager is coupled to a corresponding buffer of the plurality of buffers and configured to execute a request for a buffer transaction at the corresponding buffer according to an instruction received from the buffer controller.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: August 17, 2021
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Qinggang Zhou, Lingling Jin
  • Patent number: 11082367
    Abstract: A circuit includes a buffer configured to receive a first Flexible Ethernet (FlexE) frame having 66b blocks including 66b overhead blocks and 66b data blocks, wherein the buffer is configured to accumulate the 66b overhead blocks and the 66b data blocks; a mapping circuit configured to map four x 66b overhead blocks from the buffer into a 257b overhead block and to map a sequence of four x 66b data blocks from the buffer into a 257b data block; and a transmit circuit configured to transmit a second FlexE frame having 257b blocks from the mapping circuit. The mapping circuit can be configured to accumulate four 66b blocks of a same kind from the buffer for mapping into a 257b block, where the same kind is one of overhead and a particular calendar slot n where n=0-19.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 3, 2021
    Assignee: Ciena Corporation
    Inventors: Sebastien Gareau, Eric S. Maniloff
  • Patent number: 11080190
    Abstract: Embodiments of the present disclosure relate to an apparatus comprising a memory and at least one processor. The at least one processor is configured to monitor one or more processing threads of a storage device. Each of the one or more processing threads includes two or more cache states. The at least one processor also updates one or more data structures to indicate a subject cache state of each of the one or more processing threads and detect an event that disrupts at least one of the one or more processing threads. Further, the processor determines a cache state of the at least one of the one or more processing threads contemporaneous to the disruption event using the one or more data structures and performs a recovery process for the disrupted at least one of the one or more processing threads.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: August 3, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Kaustubh Sahasrabudhe, Steven Ivester
  • Patent number: 11068423
    Abstract: Provided is a control device that includes: a communication unit; one or more functional units; and a communication line connecting the communication unit and the one or the plurality of functional units. The communication unit includes: a computation processing unit in which a processor executes one or more tasks; a communication circuit which handles the transmission and reception of communication frames via the communication line; and a control circuit connected to the computation processing unit and the communication circuit. The control circuit includes: a first Direct Memory Access (DMA) core for accessing the computation processing unit; a second DMA core for accessing the communication circuit; and a controller which, in response to a trigger from the computation processing part, provides sequential commands to the first DMA core and the second DMA core in accordance with a predefined descriptor table.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: July 20, 2021
    Assignee: OMRON Corporation
    Inventors: Masaichi Takai, Yasuhiro Nishimura
  • Patent number: 11055174
    Abstract: Disclosed are devices, systems and methods for improving performance of a block of a memory device. In an example, performance is improved by implementing soft chipkill recovery to mitigate bitline failures in data storage devices. An exemplary method includes encoding each horizontal row of cells of a plurality of memory cells of a memory block to generate each of a plurality of codewords, and generating a plurality of parity symbols, each of the plurality of parity symbols based on diagonally positioned symbols spanning the plurality of codewords.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Chenrong Xiong, Aman Bhatia, Yu Cai, Fan Zhang
  • Patent number: 11016912
    Abstract: A memory controller according to example embodiments of the inventive concept includes a system bus, a first direct memory access (DMA) engine configured to write data in a buffer memory through the system bus, a snooper configured to output notification information indicating whether the data is stored in the buffer memory by snooping around the system bus, and a second direct memory access (DMA) engine configured to transmit the data written in the buffer memory to a host in response to the notification information from the snooper.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co.,, Ltd.
    Inventor: JunBum Park
  • Patent number: 11003606
    Abstract: A direct memory access (DMA) controller, includes circuitry configured to load a DMA transfer descriptor configured to define which memory elements within a contiguous block of n memory elements are to be included in a given DMA transfer. The circuitry is further configured to, based on the DMA transfer descriptor, determine whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, including a determination that two or more non-contiguous sub-blocks of memory elements within the contiguous block of n memory elements are to be transferred. The circuitry is further configured to, based on the determination of whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, perform the DMA transfer of memory elements determined to be included within the given DMA transfer.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 11, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Laurentiu Birsan, Manish Patel, Joseph Triece
  • Patent number: 10997496
    Abstract: A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. Compressed-sparse data is received for input to a processing element, wherein the compressed-sparse data encodes non-zero elements and corresponding multi-dimensional positions. The non-zero elements are processed in parallel by the processing element to produce a plurality of result values. The corresponding multi-dimensional positions are processed in parallel by the processing element to produce destination addresses for each result value in the plurality of result values. Each result value is transmitted to a destination accumulator associated with the destination address for the result value.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: May 4, 2021
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, Angshuman Parashar, Joel Springer Emer, Stephen William Keckler, Larry Robert Dennison
  • Patent number: 10969983
    Abstract: A method for implementing NVMe over fabrics includes generating, by a terminal, a NVMe instruction, where the NVMe instruction indicates a data read operation or a data write operation. The method further includes sending, by the terminal by using remote direct memory access (RDMA), the NVMe instruction to a submission queue (SQ) that is stored in a server. When the NVMe instruction indicates the data read operation, the method includes receiving, by the terminal by using the RDMA, to-be-read data sent by the server. Alternatively, when the NVMe instruction indicates the data write operation, the method includes sending, by the terminal, to-be-written data to the server by using the RDMA. The method further includes receiving, by the terminal, an NVMe completion instruction sent by using the RDMA by the server; and writing, by the terminal, the NVMe completion instruction into a completion queue (CQ) that is set in the terminal.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: April 6, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Shiping Deng, Hongguang Liu, Haitao Guo, Xin Qiu
  • Patent number: 10962972
    Abstract: A safety architecture system includes, in one aspect, a first stage comprising a primary unit that generates primary data for performing normal system functionality; a secondary unit that generates secondary data for performing alternative system functionality; a primary safety gate coupled to the primary unit, with the primary safety gate providing the primary data as a primary output responsive to a determination of validity of the primary data; and a secondary safety gate coupled to the secondary unit, with the secondary safety gate providing the secondary data as a secondary output responsive to a determination of validity of the secondary data. The system also includes an output selector that is coupled to both the primary safety gate and the secondary safety gate of the first stage, with the output selector providing a system output responsive to the determinations of the validities of the primary data and the secondary data.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: March 30, 2021
    Assignee: Carnegie Mellon University
    Inventors: Philip Koopman, Michael D. Wagner, Justin Ray, Aaron Kane
  • Patent number: 10956336
    Abstract: Aspects of the invention include receiving a request to transfer data from a first storage device, coupled to a sending server, to a second storage device, coupled to a receiving server. The data is transferred from the first storage device to the second storage device in response to the request. The transferring includes allocating a first temporary memory on the sending server and moving the data from the first storage device to the first temporary memory. The transferring also includes initiating a remote direct memory access (RDMA) between the first temporary memory and a second temporary memory on the second server. The RDMA causes the data to be transferred from the first temporary memory to the second temporary memory independently of an operating system executing on a processor of the sending server or the receiving server. The transferring further includes receiving a notification that the transfer completed.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mengze Liao, Yang Liu, Jiang Yu
  • Patent number: 10949242
    Abstract: Disclosed by the present invention are a running method for an embedded type virtual device and a system, an embedded type device being divided into a managing process, a plurality of real-time modules and a plurality of non-real-time modules. The managing process reading a configuration file, loading real-time and non-real-time module libraries of each processor and completing initialization interaction by means of a virtual controller area network (CAN) bus and first in, first out (FIFO) communication. The managing process starting a real-time thread and serially scheduling real-time task according to a task period setting relation. The managing process starting a plurality of non-real-time threads, calling a period task of a non-real-time module and carrying out parallel communication with a plurality of debugging clients. The real-time modules exchange data with each other by means of a virtual data bus, and the real-time modules exchange data with the non-real-time modules by means of a sharing memory.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 16, 2021
    Assignees: NR ELECTRIC CO., LTD, NR ENGINEERING CO., LTD
    Inventors: Hongjun Chen, Qiang Zhou, Jifeng Wen, Jiuhu Li, Dongfang Xu, Guanghua Li, Wei Liu, Dewen Li, Lei Zhou, Tianen Zhao
  • Patent number: 10949357
    Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: March 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sriramakrishnan Govindarajan, Gregory Raymond Shurtz, Mihir Narendra Mody, Charles Lance Fuoco, Donald E. Steiss, Jonathan Elliot Bergsagel, Jason A. T. Jones
  • Patent number: 10949546
    Abstract: A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jin Chung, Jae-Chul Park, Ki-Seok Bae, Jong-Hoon Shin, Yun-Ho Youm, Hye-Soo Lee, Hong-Mook Choi, Jin-Su Hyun
  • Patent number: 10942682
    Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: March 9, 2021
    Assignee: RAMBUS INC.
    Inventors: Michael L. Takefman, Maher Amer, Riccardo Badalone
  • Patent number: 10942672
    Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Shrinivas Venkatraman, Eng Hun Ooi, Sahar Khalili, Dimpesh Patel, Kuan Hua Tan
  • Patent number: 10936513
    Abstract: The invention introduces a method for executing host input-output (IO) commands, performed by a processing unit of a device side when loading and executing program code of a first layer, at least including: receiving a host IO command from a host side through a frontend interface; generating a slot bit table (SBT) including an entry according to the host IO command; creating a thread of a second layer; and sending addresses of callback functions and the SBT to the thread of the second layer, thereby enabling the thread of the second layer to call the callback functions according to the IO operation of the SBT for driving the frontend interface to interact with the host side to transmit user data read from a storage unit to the host side, or receive user data to be programmed into the storage unit from the host side.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 2, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Shen-Ting Chiu
  • Patent number: 10939261
    Abstract: Aspects of the present disclosure provide techniques for routing internet protocol (IP) and non-IP packets in cellular vehicle-to-everything devices that can be transmitted over the air via cellular or side-link device-to-device (D2D) communication systems without the need for the applications (e.g., automotive applications) to modify its operations. Specifically, an application (automotive application or web browser) may use default Application Programming Interface (API) that is typically used for regular cellular communication without modifying its operations to differentiate between IP and non-IP packets. Instead, in accordance with present disclosure, logical data paths may be dynamically adjusted to map services associated with the packets with an appropriate media access control (MAC) flow such that the modem receiving the packet may process and route the packet to target end-destination.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 2, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Tom Chin, Juan Zhang, Ajith Tom Payyappilly
  • Patent number: 10936511
    Abstract: Systems and methods for providing capability of access to distributed memory blocks using a global address scheme in a programmable logic device. Each of the distributed memory blocks includes routing circuitry that receives data, and in a first mode, decodes whether the data is intended for a respective distributed memory block. In a second mode, the data may bypass routing circuitry. Furthermore, the data may be received at the distributed memory block via cascade connections of distributed memory blocks in a column and/or via register in the programmable fabric of the programmable logic device.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Chee Hak Teh
  • Patent number: 10936517
    Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Joerg Walter
  • Patent number: 10929339
    Abstract: A data processing system and method include processing circuitry configured to receive sensor data from a plurality of field devices and convert the sensor data to field data, receive a first source file having first field data exported from a first editor, receive a second source file having second field data exported from a second editor, filter the first and second field data according to one or more conditions, generate multiple worksheets based upon the one or more conditions of the filtered first and second field data, extract the filtered first and second field data from source fields of the first source file and the second source file and map the extracted first and second field data into related worksheet fields of the multiple worksheets, and export the multiple worksheets having the mapped and extracted first and second field data in an export file.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 23, 2021
    Assignee: Yokogawa Electric Corporation
    Inventors: Haydee Lavisores PleƱos, Acelython Ordillo Navarro, Ying Tzu Huang
  • Patent number: 10922068
    Abstract: Updating firmware in an programmable integrated circuit (IC) includes determining, using a processor of a computer, a base address register (BAR) of an accelerator card from a device data file, wherein the accelerator card includes a programmable IC and is connected to the computer via a communication bus, mapping, using the processor, a feature PROM and a flash programmer circuit of the programmable IC to local memory of the computer using the BAR, and reading, over the communication bus, the feature PROM on the programmable IC to determine a programming mode for programming an external flash memory coupled to the flash programmer circuit. Based on the programming mode and using the processor, firmware is provided to the flash programmer circuit on the programmable IC via the communication bus. The flash programmer circuit is configured to program the firmware into the external flash memory.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 16, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ryan F. Radjabi, Hem C. Neema, Sonal Santan, Yenpang Lin
  • Patent number: 10922038
    Abstract: A memory control method receives a read request data set including a management ID and requesting reading of data from a memory, transmits read data that is read corresponding to the read request, stores write data temporarily in a write buffer, stores the read data read from the memory temporarily in a read buffer, stores write control data and read control data in an arbitration queue, executes an arbitration that determines a priority order of processing taking the write control data and the read control data that are stored in the arbitration queue as targets, and matches an order of transmitting a plurality of pieces of read data that are read from the memory corresponding to the read control data selected based on the determined priority order and are associated with an identical management ID to an order of receiving the read request data set.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: February 16, 2021
    Assignee: Kyocera Document Solutions Inc.
    Inventors: Masayoshi Nakamura, Dongpei Su
  • Patent number: 10909043
    Abstract: A direct memory access controller, configured to be used in a computing node of a system on chip (SoC), includes: (1) an input buffer for receiving packets of data coming from an input/output interface of the computing node; (2) a write control module for controlling writing of data extracted from each packet to a local memory of the computing node shared by at least one processor other than the direct memory access controller; and (3) an arithmetic logic unit for executing microprograms. The write control module is configured to control the execution by the arithmetic logic unit of at least one microprogram including instruction lines for arithmetic and/or logical calculation concerning only storage addresses for storing the data received by the input buffer for a reorganization of the data in the shared local memory. Optionally, at least one microprogram may be stored in a register, and at least two operating modes (e.g.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 2, 2021
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Yves Durand, Christian Bernard
  • Patent number: 10901910
    Abstract: The invention relates to a method for transferring data between a computer program executed by a processor and an input/output device using a memory accessible by the computer program and the input/output device. An operating system provides a trigger address range in a virtual address space assigned to the computer program. A page fault is caused by accessing the trigger address by the computer program. A page fault handler handling the page fault acquires information for identifying the data to be transferred using the trigger address. The acquired information is provided to the input/output device and the identified data is transferred between the memory and the input/output device.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Christoph Raisch, Carsten Otte, Matthias Brachmann, Marco Kraemer
  • Patent number: 10877693
    Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Nadav Bonen, Julius Mandelblat, Nir Sucher
  • Patent number: 10871901
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: December 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Patent number: 10866737
    Abstract: Techniques and mechanisms for exchanging information between a solid state drive (SSD) and a write-in-place non-volatile memory via a host device. In an embodiment, access control information defines state of the SSD, where the access control information determines and/or is based on an access by the host device to other non-volatile memory of the SSD. The access control information includes address conversion information defining a correspondence of a logical address with a physical address for a location of the other non-volatile memory of the SSD. At least some of the access control information is stored by the SSD to the write-in-place non-volatile memory for later retrieval by the SSD. In another embodiment, the SSD signals that a commit operation is to be performed to flush any cached or buffered access control information into the write-in-place non-volatile memory.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Anand S. Ramalingam, James A. Boyd, Myron Loewen
  • Patent number: 10860218
    Abstract: Example implementations relate to determining a device wear-rate. An example system for determining a device wear-rate can include a plurality of filter drivers to: monitor system requests for I/O associated with a device of the system and transmit information associated with the system requests to a filter manager. The system can also include the filter manager to catalog the information, a service to collate the information across a plurality of machine configurations and workloads, and a processor to determine a wear-rate of the device based on an analysis of the collated information.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: December 8, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Christoph J Graham, Thomas J Flynn, Virginia Quance Herrera
  • Patent number: 10853308
    Abstract: A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 1, 2020
    Assignee: Xilinx, Inc.
    Inventors: Ramesh R. Subramanian, Ravinder Sharma, Jayaram Pvss, Michael Zapke, Manjunath Chepuri
  • Patent number: 10838896
    Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: November 17, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Brian Jason Karguth, Charles Lance Fuoco, Samuel Paul Visalli, Michael Anthony Denio
  • Patent number: 10838654
    Abstract: When contents of UFSHCI standard are directly implemented in a UFS host, a problem may occur such that read/write operations of a UFS device stop or contents of data are destroyed. A semiconductor device has a UFS host controller that performs data transfer with a universal flash storage (UFS) device. The semiconductor device includes a Run-Stop register that sets the UFS host controller into a processing possible state, a Door bell register that instructs the UFS host controller to perform transfer, and a ready bit that indicates whether or not the UFS host controller can perform processing of transfer request. When the Run-Stop register is cleared while the data transfer is in process, the UFS host controller prevents a next data transfer from being registered until the data transfer is completed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 17, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Daisuke Mizoguchi
  • Patent number: 10788991
    Abstract: Providing access to a data storage resource. A storage subsystem comprising one or more storage address units and is associated with one or more access interfaces is identified. An address-interface correlation guideline is identified that defines a combination of rules that govern which access interfaces are used to access storage address units. A target address unit identification is received from a requesting system. A processor determines which storage address units a requesting system requests to access to based on the received target address unit identification. The target address unit identification is associated with at least one of the storage address units. The requesting system is provided with access to the storage address units using access interfaces that are determined based on a target interface conclusion.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sergio Reyes, Brian C. Twichell
  • Patent number: 10783103
    Abstract: A signature is generated to indicate a direct memory access (DMA) operation involving a transfer, by a DMA engine, of data between a host memory circuit and an endpoint memory circuit of an endpoint processor circuit. First descriptors of the DMA engine are defined relative to the endpoint memory circuit or host memory circuit. A signature is received that indicates that second descriptors have been configured by the endpoint processor circuit. In response to receiving the endpoint signature, the DMA engine is enabled to begin the DMA operation.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 22, 2020
    Assignee: Xilinx, Inc.
    Inventors: Sunita Jain, Bharat Kumar Gogada, Ravikiran Gummaluri
  • Patent number: 10769086
    Abstract: A recording medium to be used by being connected to a digital device includes a local bus, a plurality of recording units, an information storage unit, and a communication unit. The local bus has a plurality of switches or bridges. The plurality of recording units are connected to the local bus. The information storage unit stores information indicating a bus configuration of the local bus. The communication unit is used for transferring the information to and from the digital device. After the recording medium is inserted into the digital device, the bus configuration of the local bus is reconstructed based on the information acquired from the communication unit via the information storage unit by the digital device.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: September 8, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hideaki Yamashita, Takeshi Otsuka, Masanori Mitsuzumi
  • Patent number: 10761982
    Abstract: An efficient data storage device is disclosed, which uses a microprocessor and at least one volatile memory to operate a non-volatile memory. The microprocessor allocates the volatile memory to provide a cache area. According to an asynchronous event request (AER) issued by a host, the microprocessor uses the cache area to collect sections of write data requested by the host, programs the sections of write data collected in the cache area to the non-volatile memory together, and reports failed programming of the sections of write data to the host by AER completion information.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 1, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Ming-Hung Chang, Fang-I Peng
  • Patent number: 10761733
    Abstract: A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: September 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno