Abstract: A method for accessing a shared resource is provided. An assigned usage rate is received from a resource coordinator and a desired usage rate is determined. When it is determined that the desired usage rate is higher than the assigned usage rate, a shared resource may be accessed at an enhanced usage rate if a usage reserve has been accumulated. When a shared resource is accessed at an enhanced usage rate, the usage reserve is decremented by an amount based on a difference between the enhanced usage rate and the assigned rate. When there is no usage reserve accumulated, access to the shared resource is limited to the assigned usage rate. When the desired usage rate is not higher than the assigned usage rate, a shared resource is accessed at the desired usage rate. When the desired usage rate is less then the assigned usage rate, the usage reserve is accumulated up to a reserve maximum. The reserve maximum may be based on configuration data.

Abstract: It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started.

Abstract: A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first device when it is determined that the first device should release the bus.

Abstract: In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency.

Abstract: A network interface device minimizes access latency in initiating a DMA transfer request by selectively supplying a long bit comparison result, generated in a write controller configured for writing data into a buffer memory, directly to a read controller based on a determination that the buffer memory stores less than one complete frame. The media access controller determines the length of the data frame, and supplies the determined length to the write controller. The write controller compares the determined length to a prescribed threshold, and outputs a long bit value for storage in a buffer memory location contiguous with the stored data frame. The long bit can then be used to select a receive buffer threshold optimized for larger frames.

Abstract: An integrated circuit, configured for connection to an SCSI bus includes a strobe assertion edge triggered glitch filter. Input data latches are controlled by the strobe assertion edge gated with a strobe enable signal and the inverted and delayed Q output of a flip-flop. Once a valid strobe assertion edge is detected, it is used latch data bus signals into the data latches. Following a defined delay period through a delay stage, the data latch strobe is masked from any further transition until the strobe enable signal is again affirmatively asserted by an SR latch. The masking period is defined upon receipt of a valid strobe assertion edge and maintained for a first period by the combination of the SR latch, a flip-flop and a delay stage. The latch strobe mask is maintained for a second period by a strobe masking extension circuit made up of series-connected flip-flops.

Abstract: A data access control system for reading/writing data from/to an array of storage units, which is resilient to read/writing errors to avoid lost data, while meeting the realtime requirements. Consecutive data blocks are stored in a plurality of storage units in a distributed manner by using a striping technique. A time slot vacancy monitor checks the present activities of the storage units to find a vacant time slot during which no data read/write operations are scheduled. A data read/write controller finds a particular data block that is scheduled to be read out of/written the storage units just after the vacant time slot has expired. When such a data block is found, the data read/write controller prefetches that data block during the vacant time slot. If a read/write error is encountered during the prefetch of the data block, the data read/write controller attempts read/write retry operations in the remaining period of the vacant time slot until the scheduled data output time comes.

Abstract: A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller initiates a speculative data transfer cycle after the notification. The DMA Controller aborts the speculative data transfer cycle if the slave device does not request another data transfer within a predetermined time.

Abstract: The data processing circuit has a self-timed instruction execution unit, which operates asynchronously, signalling the completion of processes and starting subsequent processes in response to such signalling. In order to satisfy real time constraints upon program execution ready signals generated after completion of selected instructions are gated with a timer signal before they are used to start a next instruction. In an embodiment, the amount of time left between the ready signal is used to start a next instruction is measured and used to regulate a power supply voltage of the instruction execution unit so that it is just high enough to make the instruction execution unit sufficiently fast to meet the real time constraints.

Abstract: A file system in a computer for managing buffer areas. A buffer area includes file input and output data and is divided into a plurality of areas for each application object such as system data and user data. Each divided buffer area is independently managed by a buffer management processing unit for controlling the acquisition and release of buffers requested. A circuit for designating a block size and a lower limit value of an assignable block is provided for each buffer area divided according to an application object to realize effective use of buffer areas and a reduction in the waiting time for the acquisition of buffers.

Abstract: An apparatus and method are implemented to track and manage system cycles stolen from a data processor by other processors in a multiprocessor data processor system. The apparatus and method maximize data throughput and minimize unused cycle resources within the multiprocessor data processing system.

Abstract: A data processing device having a DMA function for controlling DMA transfer, comprises a DMA unit, a CPU, a bus arbitration unit for controlling bus-using right of the DMA unit or the CPU, and an interruption controller for supplying an interruption request signal. The DMA unit includes a register, a comparator for making a comparison between a priority of a DMA transfer and a priority set on an interruption request, and a sequencer for deciding whether the DMA transfer is to be executed, canceled, or suspended in the operation state of a DMA unit according to the comparison result of the comparator.

Abstract: An information handling system transfers command blocks between a host processing side having a host processing unit and a host memory and a local processing side having a local processing unit and a local memory. The command blocks are transferred from the host processing side to the local processing side by storing the host address of the command block in a local side register set. Upon storing the host address a transfer signal is given to a command block transfer controller to start a command block transfer without the local processor unit intervention.

Abstract: A data processing unit capable of solving a conventional problem in that a CPU cannot acquire the right of using a bus as long as a DMAC (Direct Memory Access Controller) has that right, and hence the operating ratio of the CPU reduces. A CPU bus is kept disconnected from the DMAC bus as long as the CPU disables the access request to a memory connected to the DMAC bus, and is connected to a DMAC bus in response to the access request unless the DMAC has the right of using a DMAC bus.

Abstract: A computer is provided having a bus interface unit between a CPU bus and a memory bus. The bus interface unit includes a memory controller and a read/write queue manager. The memory controller dispatches, or removes read requests or write requests from respective read or write requests queues depending on various modes of operation. Typically, the read requests are dispatched or removed either singularly or as a programmed series of read requests prioritized over write requests unless the write request queue is almost full. If the write request queue is almost full, then write request are removed either singularly or in a series before servicing the read request queue. The number of read or write request being removed from their respective queues can be programmed within a configuration register operably coupled to a controller arranged between the read and write request queues. The memory controller determines how many requests will be serviced within possibly a lengthy series of requests.

Abstract: The present invention provides a method and apparatus whereby a single engine can manage multiple DMA queues and related functions for a mass storage subsystem such as a RAID array. By operating the engine at a suitably high clock rate, the key buses may be time multiplexed such that each bus operates at substantially its optimum frequency to maintain high efficiency of data throughput. To improve performance further, the DMA addressing function is allocated additional phases whenever the remaining buses have not requested access to the RAID engine.