Abstract: A system, computer-implementable method, and computer-readable medium for improving sequential serial attached small computer system interface storage device performance. According to a preferred embodiment, a microprocessor within a target device receives a collection of tasks from at least one initiator device via a collection of initiator paths. The target device is a cyclic non-volatile memory medium. The microprocessor queues the collection of tasks according to a collection of task list. Each task list corresponds to a respective initiator path. The microprocessor combines the collection of tasks in an execution queue. The collection of tasks on the execution queue is reordered based on a priority scheme. The microprocessor executes the collection of tasks from the execution queue.

Abstract: A system, a controller, and a method thereof for transmitting data stream from a host to a peripheral device with a chip are provided. At least a part of a data stream is transmitted from the host to the peripheral device. Then, the host inerrably receives a response message generated by the chip by executing a plurality of read commands. The data stream and the response message have corresponding write tokens, and the write token of the data stream is compared with the write token of the response message to verify the accuracy of the response message.

Abstract: A key activity detection method, applied in an electronic device having at least a first key and a digital I/O pin, includes: switching the digital I/O pin to a first operation mode, so that a voltage of the digital I/O pin is decreased to a ground voltage; switching the digital I/O pin to a second operation mode, so that the voltage of the digital I/O pin is increased; measuring a first charge period of the voltage of the digital I/O pin; counting a first appearance times of the first charge period; judging whether the first key is stably activated according to the first appearance times of the first charge period.

Abstract: An efficient transfer of data including a plurality of data sections is achieved. In a data transfer system including a first DMA 1142 of a channel control unit 11 and an MP 122 of a processor unit 12 that sets a transfer parameter in the first DMA 1142, while CKD format data 1400 is transferred from a cache memory 14 to a memory 113 of the channel control unit 11, the MP 122 acquires a C field 1411 from the cache memory 14 and sets a transfer parameter in the first DMA 1142 on the basis of the acquired C field 1411, the transfer parameter having attached thereto the C field 1411 and being used for transferring a K field 1412 from the cache memory 14 to the memory 113. The first DMA 1142 retrieves the C field 1411 attached to the transfer parameter, stores the C field 1411 in the memory 113, and transfers the K field from the cache memory 14 to the memory 113 according to the transfer parameter.

Abstract: Provided is a storage device of a serial attached small computer system interface/serial advanced technology attachment (SAS/SATA) type, which provides data storage/reading services through an SAS/SATA interface. The SAS/SATA type storage device includes: a memory disk unit which includes a plurality of memory disks provided with a plurality of volatile semiconductor memories; an SAS/SATA host interface unit which interfaces between the memory disk unit and a host; and a controller unit which adjusts synchronization of a data signal transmitted/received between the SAS/SATA host interface unit and the memory disk unit to control a data transmission/reception speed between the SAS/SATA host interface unit and the memory disk unit.

Abstract: A data processing apparatus includes a register file having a set of registers for storing data values for processing by processing circuitry. The apparatus has first shift circuitry arranged to receive a data value from the register and selection circuitry is responsive to a second control signal to select between the first shifted data value and a load data value received from a memory. Second shift circuitry is arranged to receive the data value selected by the selection circuitry and is responsive to a third control signal indicating a second shift amount S2 of a x (n+1) bit positions to generate a second shifted data value by shifting bit values within the received selected data value by the second shift amount S2, where a is zero or an integer. The second shift circuitry is then operable to output the second shifted data value to the register file.

Abstract: Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described.

Abstract: Systems and methods for requesting and receiving data from an enterprise information system are described. In accordance with one embodiment, the connector system includes an application server managed connection factory for receiving a data request, and a load balancer for assigning an enterprise information system server connection to the request.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for live media playback adaptive buffer control. For example, when media accumulated in the live buffer exceeds a user-configured threshold, media can be played out faster. In this manner, the media player is configured not to discard media packets, but rather to render the buffered media faster to slowly eliminate accumulated backlog. Preventing unbounded buffer accumulation may be desirable in applications like video surveillance, live video broadcast, webcast, and the like.

Abstract: A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller.

Abstract: [Object] To make it possible to control a CEC-non-compliant device connected to a television receiver by using a remote control sender of the television receiver. [Solving Means] The fact that a physical address [2000] is a device (Recording Device) that a photo player 370B controls in place of the physical address [2000] is set by a user in the photo player 370B. In accordance with this setting, the photo player 370B decides a logical address {1} as a CEC-controlled Recording Device. When the user operates a disc recorder 210B that is a CEC-non-compliant device by using a remote control sender 277, a television receiver 250B generates a CEC control command addressed to the disc recorder 210B. The photo player 370B detects the CEC control command, converts the CEC control command into an infrared remote control command, and sends the infrared remote control command from an infrared sending unit 384 to the disc recorder 210B.

Abstract: Disclosed is a wireless remote network management system for interfacing a series of remote devices (e.g., computers, servers, networking equipment, etc.) to one or more user workstations. The system is multifunctional to allow multiple users to control remote devices through serial access or keyboard, video, and cursor control device access via wireless and hard-wired connections. The remote devices are preferably coupled to a wireless-enabled remote management unit through a chain of computer interface modules, and each user workstation includes a wireless user station coupled to a keyboard, a video monitor and a cursor control device. The remote management unit and user stations preferably communicate via a wireless network, which enables a user workstation to access, monitor and control any of the remote devices.

Abstract: A cable connection support apparatus has a structure in which a master apparatus and a slave apparatus are connected to both ends of a plurality of cables, and each apparatus is connected to each cable by a connecting terminal. The master apparatus and the slave apparatus are grounded. The master apparatus makes, for each connected cable, an inquiry about a position of a terminal of the slave apparatus to which the cable is connected, and inspects for inter-continuity, grounded connection, and unintentional disconnection. The connection destinations and inspection results are displayed on a display apparatus. Consequently, the connection condition for each cable wire in a cable can be confirmed.

Abstract: Provided are systems and methods to communicate data transfer of data between a disk device and an external storage device. A host can generate a control command to communicate with an external storage device, and a disk device to receive the control command from a host to identify and communicate with an external storage device when connected to the external storage device and to configure the external storage device by assigning an ID code to each storage area of the external storage device.

Abstract: An HDMI™ (High-Definition Multimedia Interface) switch includes a CEC (Consumer Electronics Control) processor for controlling high-definition audio-visual (AV) equipment. The CEC processor accepts user commands and translates them to control HDMI devices over HDMI; the translations can be manufacturer specific so that devices with different CEC implementations can be combined in a single system. CEC communications between HDMI devices is precluded or at least controlled to avoid problems due to incompatible CEC implementations and unwanted interactions. The CEC processor causes the HDMI switch to appear as an HDMI source to HDMI sink devices and as an HDMI sink to HDMI source devices for the purposes of assigning physical addresses. While CEC is designed to handle AV systems having only one sink (display), the novel HDMI switch provides for CEC-controlled AV systems with multiple displays, e.g., in different rooms.

Abstract: Techniques are disclosed involving the exchange of information with multiple modems. For instance, an apparatus includes a host device, a plurality of modems, and a serial connection to transfer information between the host device and the plurality of modems. The information may include data associated with one or more user applications and commands for the plurality of modems. The serial connection may be a Universal Serial Bus (USB) connection.

Abstract: The techniques introduced here include storage systems including a storage controller configured to access data and a storage subsystem including a storage device having n ports, where n is an integer greater than one, and where the storage device is configured to store the data and to make the data available to the storage controller via each of the n ports. The storage systems also include a communication fabric configured to couple the storage controller to each of the n ports of the storage device via m paths, where m is an integer greater than n, so that the storage system is configured to tolerate failure in up to m?1 paths through the communication fabric, such that the data in the storage device remains accessible to the storage controller even in the presence of failure in up to m?1 paths of the m paths.

Abstract: A signal processing apparatus and method for processing an input signal. A first signal processing unit processes the input signal, and an expansion unit adds a second signal processing unit. A detecting unit detects whether the one or more additional second signal processing units has been added on to the expansion unit. A communication unit performs data transfers between the first signal processing unit and second additional signal processing unit via wireless communication, and a control unit coordinates the first signal processing unit and the one or more additional signal processing units.

Abstract: Prior to customer use of a device, communication with the device is allowed via multiple pins of an external interface of the device. One or more pins of the multiple pins via which communication with the device is to be prevented during customer use of the device are identified. The one or more pins are monitored, and a remedial action is taken if particular activity is detected on the one or more pins. Various different remedial actions can be taken, such as resetting or disabling the device.

Abstract: This document discusses, among other things, a system and method for switching serialized video information (e.g., non-packet-based video information) and Universal Serial Bus (USB) information (e.g., packet-based information) to a common output (e.g., to a physical USB interface).

Abstract: A controller is provided with a first memory area and a second memory area, where a pre-update software is stored with the first memory area as the active area and an updated software is downloaded with the second memory area as an inactive memory area. A microprocessor for simulations performs a simulation of the control of the operation of a field device using the updated software that has been downloaded. The execution status of the simulation can be monitored using a host computer. If the evaluation result of the state of execution of the simulation by an operator is “Pass,” then an activate command is sent to the controller. As a result, the active/inactive are switched in the controller.

Abstract: A data storage device comprises a data storage medium and a connector that provides an interface between the data storage medium and a host device. The connector has a shape that substantially conforms to an internal storage interconnect standard. The connector comprises a first set of electrical contacts that substantially conform to the internal storage interconnect standard, and a second set of contacts configured to provide connectivity with the host device in accordance with an external storage interconnect standard. Also described are cables for connecting the data storage device to a host via the external storage interconnect standard as well as an interconnect detector.

Abstract: A programmable network component for use in a plurality of network devices with a shared architecture, where the programmable network component includes an interface with an external processing unit to provide management interface control between the external processing unit and a network device. The programmable network component also includes a plurality of internal busses each of which is coupled to the programmable network component and to at least one network component. The programmable network component further includes a plurality of external buses each of which is coupled to the programmable network component and to at least one physical interface. The programmable network component is configured to support a plurality of protocols for communication with a plurality of physical interface components and comprises a plurality of programmable registers for determining the status of the plurality of physical interfaces.

Abstract: An expansion card is provided that allows resources allocated to the expansion card to be shared with a different card. The expansion card comprises a coupling device that couples the expansion card to a data processing system. The expansion card also includes an identifier data structure that when queried by the data processing system, identifies the expansion card as a resource sharing expansion card. The data processing system reallocates one or more resources allocated to the expansion card to a different card coupled to the data processing system.

Abstract: A data storage device comprises a data storage medium; an interface between the data storage medium and a host device configured to provide connectivity according to a plurality of storage interconnect standards. The data storage device also includes a interconnect detector configured to determine the presence of a physical connection to the host device and identify an interconnect standard of the host device, wherein the interconnect standard of the host device is one of the plurality of storage interconnect standards; and a controller configured to: receive an indication of the interconnect standard of the physical connection from the interconnect detector, receive data access commands in accordance with the interconnect standard from the host device via the connector; process the data access commands by accessing the data storage medium; and send a response to the data access commands in accordance with the interconnect standard to the host via the connector.

Abstract: A hand-held test meter for use with an analytical test strip configured for the determination of an analyte in a bodily fluid sample includes a USB interface, a microcontroller block configured for boot strap loading (BSL) of data into the hand-held test meter via a serial signal and a circuit disruption avoidance block. The circuit disruption avoidance block includes a USB to serial bridge sub-block with (i) a USB input(s), (ii) a serial output(s) configured to provide a serial signal for BSL of data to the microcontroller block; and (iii) a plurality of general purpose input/outputs (GPIO). The circuit disruption avoidance block also includes a BSL enable gate/buffer sub-block. At least two of the GPIO are configured to provide BSL control signals to the microcontroller block via the BSL enable gate/buffer sub-block and the USB to serial bridge sub-block is configured to send the data to the microcontroller block via the at least one serial output.

Abstract: A memory expansion blade for a multi-protocol architecture, includes dual inline memory modules (DIMMs) and a multi-protocol memory controller coupled to the DIMMs and operable to control operations of the DIMMs. The multi-protocol memory controller includes one or more memory channel controllers, with each of the memory channel controllers coupled to a single channel of DIMM, and where the DIMM in each single channel operate according to a specific protocol. The controller further includes a protocol engine coupled to the memory channel controllers, where the protocol engine is configurable to accommodate one or more of the specific protocols, and a system interface coupled to the protocol engine and configurable to provide electrical power and signaling appropriate for the specific protocols.

Abstract: An interface circuit includes: a first transmitting section transmitting a first signal as an in-phase signal to an external device through a transmission path; and a second transmitting section transmitting a clock signal, which is synchronized with the first signal to be transmitted by the first transmitting section, as a differential signal to the external device through the transmission path.

Abstract: The present invention provides a method and apparatus for identifying a desired device handle in a computer system such as a personal computer running Linux™. The desired device handle is capable of facilitating or providing for interaction with a desired peripheral device, such as a USB™ device. The invention comprises providing a database containing information associating device handles with peripheral devices. A first portion of the database is scanned for information associated with the desired peripheral device. This information is used in determining a second portion of the database, which is scanned for information indicative of the desired device handle. The desired device handle is then identified.

Abstract: After reading data from a memory in response to a read request received from a bus master and burst transferring the read data, a memory interface 100 continues to read and store (i.e., continuously reads and stores) data starting from an address that follows all of addresses of the read data. Upon receiving a new read request from the bus master within a predetermined time, the memory interface 100 determines whether a difference between an address specified by a previous read request and an address specified by a new read request falls within a predetermined range. If it is determined positively, the memory interface 100 successively transfers the stored data in response to the new read request. If it is determined negatively, or if the reception of the new read request is not performed within the predetermined time, the memory interface 100 terminates the continuous data read.

Abstract: In general, techniques are described for performing work conserving packet scheduling in network devices. For example, a network device comprising queues that store packets and a control unit may implement these techniques. The control unit stores data defining hierarchically-ordered nodes, which include leaf nodes from which one or more of the queues depend. The control unit executes first and second dequeue operations concurrently to traverse the hierarchically-ordered nodes and schedule processing of packets stored to the queues. During execution, the first dequeue operation masks at least one of the selected ones of the leaf nodes from which one of the queues depends based on scheduling data stored by the control unit. The scheduling data indicates valid child node counts in some instances. The masking occurs to exclude the node from consideration by the second dequeue operation concurrently executing with the first dequeue operation, which may preserve work in certain instances.

Abstract: A storage array includes at least one target and a logical unit having a logical unit number. The storage array is configured to receive input defining a host group comprising at least one initiator and receive input defining a target group comprising the at least one target. The host group, target group and logical unit number define a view entry. The storage array is further configured to apply the view entry to the logical unit to provide a logical unit inventory that is provisioned for the at least one initiator.

Abstract: A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the signal levels in a specific way when controlling two existing data or select lines, an expansion input and/or output device can generate a strobe and/or enable signal internally. This internal strobe and/or enable signal is then used to store output data or enable input data. The host controller typically utilizes software or firmware to control the data transitions, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.

Abstract: A device system and method is disclosed. The device includes a first USB port configured to couple with a USB port on a camera, and circuitry configured to send USB signals to the camera and/or to receive USB signals from the camera, and to operate in USB Host mode, and/or USB OTG (on the go) mode, as the camera operates in Device mode. The device may also include a second USB port configured to couple with a PDA. The circuitry may be further configured to send USB signals to the PDA and/or to receive USB signals from the PDA, and to operate in USB Host mode, and/or USB OTG mode, as the PDA operates in Device mode.

Abstract: A universal serial bus (USB) communication system, the communication system including: (a) at least one asynchronous transmission queue manager configured to queue, in at least one asynchronous transmission queue, information for asynchronous transmission through at least one asynchronous pipe; (b) at least one guaranteed transmission queue manager configured to insert into at least one queue information for transmission through a dedicated pipe utilized by the communication system; wherein the at least one queue is selected from the at least one asynchronous transmission queue, at least one periodic transmission queue and at least one additional queue; and (c) a transmitter configured to transmit information through the at least one asynchronous pipe and the dedicated pipe, wherein the transmitting through the dedicated pipe is prioritized over the transmitting at the at least one asynchronous pipe, wherein the transmitting at the dedicated pipe is irrespective of time in which information for transmission a

Abstract: A remote console unit includes a signal processing apparatus that receives an image signal from a computer main body and also sends and receives various signals other than the image signal to and from the computer main body through a cable for general purpose. Data input and/or output can be performed remotely to and from the computer main body through the cable.

Abstract: A data system includes an article such as footwear, model car or toy, an electronic module carried by said article, the electronic module having a microprocessor and a data storage device to which the user can selectively store and retrieve data, a data input to the electronic module configured for the user to input and store data on the data storage device, a controller in electronic communication with the electronic module for controlling data output, and an audio output device in electronic communication with the electronic module for receiving data output from the electronic module.

Abstract: A hub apparatus provided by the present invention comprises an OTG (on-the-go) control module and at least one USB port and a linking module. The OTG control module has a buffer and be coupled to the USB port and the linking module. When the host apparatus and the peripheral apparatus link with the hub apparatus, the OTG control module captures a data, which is asserted by a user through the host apparatus, from the peripheral apparatus via the USB port, and saves the captured data into the buffer, so as to move the data saved into the buffer to the host apparatus via a data transmission for responding a data capturing requirement from the host apparatus.

Abstract: Architecture that allows programmatic association of devices to sessions and redirects input to the desired session. When the solution is active, input from the devices is not realized by the standard operating system input stack, thereby allowing even reserved key sequences such as Ctrl-Alt-Del to be intercepted and redirected to a desired session. Moreover, in addition to redirecting input to a specific session, the architecture facilitates the filtering of input from unwanted/unmapped devices, the interception and filtering or redirection of reserved key sequences such as Ctrl-Alt-Del, and the maintenance of input state for each session.

Abstract: A computer system including a management computer for managing the entire system, an integral apparatus, and a high-level connecting device for connecting the management computer and the integral apparatus is designed so that the management computer retains integral apparatus internal configuration information, configuration information about an integral apparatus to be introduced, that indicates the configuration of the integral apparatus that may possibly be introduced to the system, and lifetime information indicating lifetime of the integral apparatus; obtains connectivity guarantee information indicating whether connectivity between the computer and the storage apparatus is guaranteed or not; selects an integral apparatus to be removed from the system by referring to the lifetime information; selects an integral apparatus to be introduced to the system by referring to the integral apparatus internal configuration information, the configuration information about the integral apparatus to be introduced, an

Abstract: Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The I/O device driver determines whether the pending queue is sorted and responds to a determination that the pending queue is sorted, determining if queued I/O requests exceed the maximum ordered queue length. Responding to a determination that the pending queue exceeds the maximum ordered queue length, the I/O device driver adds the I/O request based on a high pointer, and points the high pointer to the I/O request.

Abstract: An adapter card for testing the functionality of a particular interface configuration may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with an information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting data between the electronic components and the information handling system device. The adapter card may include firmware for setting an indicator and causing the control logic to report a memory requirement to the information handling system device larger than a programmed memory space expected by the control logic.

Abstract: An electronic device includes a communication bus having a physical layer for interacting with a peripheral device. The physical layer is configured to be adjacent to a link layer on the peripheral device. The electronic device further includes a connector at a junction of the physical layer and the link layer. Communication through the communication bus is maintained through the physical layer when the link layer of the peripheral device is disconnected from the physical layer at the connector.

Abstract: Disclosed is a method and a SAS controller device that abstract access from one or more virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller (i.e., unique for the SAS controller such that other replicates/clones on other virtual ports have a different SAS address).

Abstract: Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.

Abstract: The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.

Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Abstract: Disclosed is provided an apparatus and a method for operating a macro command and inputting a macro command, wherein the apparatus including a storing unit storing control signals received from a control device for selecting of a menu item of a host device, a creating unit creating the macro command combined with the control signals, and an executing unit reading the macro command and executing functions corresponding to the respective menu item of the host device according to a combination sequence of the control signals included in the read macro command.

Abstract: Mechanisms to address the situation where an input/output (I/O) fabric is shared by more than one logical partition (LPAR) and where each LPAR can share with the other LPARs an I/O adapter (LOA) are provided. In particular, each LPAR is assigned its own separate address space to access a virtual function (VF) assigned to it such that each LPAR's perception is that it has its own independent IOA. Each VF may be shared across multiple LPARs. Facilities are provided for management of the shared resources of the IOA via a Physical Function (PF) of the IOA by assignment of that PF to an I/O Virtualization Management Partition (IMP). The code running in the IMP acts as a virtual intermediary to the VFs for fully managing the VF error handling, VF reset, and configuration operations. The IMP also acts as an interface to the PF for accessing common VF functionality.

Abstract: A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the signal levels in a specific way when controlling two existing data or select lines, an expansion input and/or output device can generate a strobe and/or enable signal internally. This internal strobe and/or enable signal is then used to store output data or enable input data. The host controller typically utilizes software or firmware to control the data transitions, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.