Abstract: A USB peripheral device with a power connector, such as a card reader, which serves as a peripheral device when it is connected to a host device such as a smart phone, while which can directly charge the host device when a charger is plugged in, is disclosed. The peripheral device has a USB connector and a controller. The ID, D+, D? and VBUS pins of the USB connector are connected to the controller and the power connector through a plurality of relays depending upon whether the power connector is connected by a charger or not. The peripheral device can be automatically switched to serve as a B-device or a power bridge transferring power from the charger to the host device.

Abstract: An information processing method includes calculating a reception estimated time when the data are received based on a last reception time of the data and a reception time interval of the data for transfer source devices; calculating a shift completion estimated time based on a shift time period necessary to shift an assignment of a data transfer process of a transfer source device of the plurality of the transfer source devices from the transfer processing device to another transfer processing device; and transferring the assignment of the data transfer process from the transfer processing device to the another transfer processing device, the assignment of the data transfer process being relevant to a transfer source device having the calculated reception estimated time later than the shift completion estimated time and closer to the shift completion estimated time than any other transfer source devices.

Abstract: A server of an elastic computing cloud system includes a block device driver apparatus and at least a block device service apparatus. The server implements a hot deployment for a storage service, such that an upgrade of the storage service may be performed without interrupting the storage service. The block device driver apparatus maintains a waiting queue and a pending queue for each storage service. In response to determining a storage service will perform an upgrade, the block device driver apparatus stops processing data write/read requests that are maintained in the pending queue for the service, and puts the data write/read requests that are currently processed in the pending queue back to the waiting queue for re-dispatching, thus realizing completion of processing the upgrade of the storage service in the elastic computing cloud system without interrupting the storage service.

Abstract: A communication method to transfer user operation information includes, if a user's operation is input through the electronic device, and if the electronic device then receives a command from a host device while the electronic device is connected to the host device, transmitting information to the host device notify the host device of the user's operation. Therefore, it is possible for a user to command the host device to perform a frequently used function through a simple operation of the electronic device, without a need to be aware of the complex usage of an application.

Abstract: A computerized switching system for coupling a workstation to a remotely located computer. A signal conditioning unit receives keyboard and mouse signals generated by a workstation and generates a data packet which is transmitted to a central crosspoint switch. The packet is routed through a crosspoint switch to another signal conditioning unit located at a remotely located computer. The second signal conditioning unit applies the keyboard and mouse commands to the keyboard and mouse connectors of the computer as if the keyboard and mouse were directly coupled to the remote computer. Video signals produced by the remote computer are transmitted through the crosspoint switch to the workstation. Horizontal and vertical sync signals are encoded on to the video signals to reduce the number of cables that extend between the workstation and the remote computer.

Abstract: A computer system including a management computer for managing the entire system, an integral apparatus, and a high-level connecting device for connecting the management computer and the integral apparatus is designed so that the management computer retains integral apparatus internal configuration information, configuration information about an integral apparatus to be introduced, that indicates the configuration of the integral apparatus that may possibly be introduced to the system, and lifetime information indicating lifetime of the integral apparatus; obtains connectivity guarantee information indicating whether connectivity between the computer and the storage apparatus is guaranteed or not; selects an integral apparatus to be removed from the system by referring to the lifetime information; selects an integral apparatus to be introduced to the system by referring to the integral apparatus internal configuration information, the configuration information about the integral apparatus to be introduced, an

Abstract: There is provided an apparatus including a plurality of modules. Each module includes a storage unit configured to store a waiting ID and a specific ID of the module, a communication unit configured to transmit and receive packets to and from a bus, and a processing unit configured to process data of a packet which includes a valid flag indicating that the packet is valid, wherein the communication unit takes in data held by a packet which has an ID that coincides with the waiting ID, and stores the processed data in a packet which includes the valid flag indicating invalid and an ID coincident with the specific ID, and transmits the packet.

Abstract: A multi-service processing method, including: configuring different cores of a multi-core processor to process different services; and sending received packets to the cores in the pre-defined service processing sequence. The multi-core processor apparatus, includes the configuration management unit, the packet distributing unit, and the multi-core processor. The method and apparatus can save investments in devices while implementing multiple service processing functions.

Abstract: Systems, methods and computer program products for generic device integration within an auto-id system. The system includes an auto-id node operable to collect data emitted by one or more automatic data acquisition devices, process the data, and make the data available to one or more enterprise applications, user interfaces, or other auto-id nodes. The auto-id node includes a device integration layer that is operable to handle communication between the auto-id node and different types of automatic data acquisition devices, device controllers, or device management systems.

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract: The present invention pertains to a graphics processing unit. The graphics processing unit includes a graphics processing core configured for graphics processing. A single-ended I/O interface configured to implement single-ended communication with a frame buffer memory is included in the graphics processing unit. The graphics processing unit further includes a differential I/O interface having a first portion and a second portion. In a first configuration, the first portion and the second portion implement a PCI-Express interface with a computer system. In a second configuration, the first portion implements a PCI-Express interface with the computer system and the second portion implements differential communication with a coupled device.

Abstract: A method and system that allows a host system application to securely communicate with a legacy device is provided. A redirector software module receives data that is destined for a host system serial COM port. Data is secured and re-directed to a legacy device via a network port instead of the serial COM port. Conversely, data destined for the host system is provided to a device server via a server COM port by the legacy serial device. The data can be encrypted and sent to the host system via the network. The redirector software module decrypts the encrypted data and presents it to the consumer application as if the data had arrived via the local COM port.

Abstract: Described are techniques for indicating a state associated with a device. A request is received over a path for information about a device. A response to the request is sent. The response indicates a state regarding the device on the path. The response has a response status of good and a payload of a varying size. The payload is truncated at a location prior to that at which a device identifier for the device is expected. In accordance with the response, a state regarding the device on the path is determined.

Abstract: A system for operating multiple independent terminals of grouped, locally connected input and output devices through a single graphical user interface layer running on a computer comprising an event queue module for receiving each input command from each input device; an event handler module for receiving the input commands from the event queue module and directing input commands from specific input devices via corresponding socket/listeners of the single graphical user interface layer to corresponding ones of multiple pointers, focuses and client applications based on predetermined associations between grouped devices and respective ones of the socket/listeners; and an output module for directing output commands from each socket/listener to respective ones of the output devices based on the predetermined associations.

Abstract: This disk array subsystem includes a data input/output unit for inputting and outputting data in and from the network, a connecting unit for connecting the data input/output unit and a plurality of storage apparatuses, and a control unit for controlling the input and output of data in and from the network. The control unit includes a logical link setting unit for zoning at least one or more physical links among a plurality of physical links for inputting and outputting data between the data input/output unit and the connecting unit, or between the connecting unit and the connecting unit into at least one or more logical links, and setting a plurality of logical links to one physical link; and a link unit for simultaneously multiplexing the data to a plurality of the logical links set with the logical link setting unit, and linking the data to the physical link.

Abstract: Embodiments provide unique and novel systems and methods for deleting data on removable drives. In embodiments, the removable drives store data that may be erased such that the data is considered destroyed but that allows the removable drive to be reused. The archiving system can determine which data should be erased. Then, the data is digitally shredded on sector boundaries of the removable drives such that the reclaimed memory cannot be read to decipher the erased data. In alternative embodiments, data is written across sector boundaries such that two or more files may occupy a single sector. A journal area allows for copying the data in a sector with two or more files, digitally shredding the sectors in the removable drive, and rewriting the data that was not to be digitally shredded to the original location of the data.

Abstract: A technique for user notification involves modifying a title associated with a process to include information about an event that calls for user notification. A method according to the technique may include running a process, processing an event, generating a string of characters that includes information associated with the event, and displaying the string of characters as a title associated with the process. A system constructed according to the technique may include a client, a title array, an event processing engine, and a title provisioning engine.

Abstract: An expansion input/output device includes a body having a receiving space, an input unit, a second transmission unit, and a third transmission unit. A handheld electronic device can be received in the receiving space and functions as a computation processing center. The expansion input/output device integrates an input function of the input unit to provide a user-friendly input interface, and sends an audio/video signal of the handheld electronic device from a first transmission unit of the handheld electronic device to an external display device through the second transmission unit and the third transmission unit to provide a large display view. The expansion input/output device expands the applicability and integration capacity of the handheld electronic device and enhances ease of use thereof.

Abstract: There are provided a CPU connection circuit and a method by two CPUs by alternately conducting a changeover between two buffers disposed there between to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.

Abstract: A diagnostic extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module and an intercepting decoder chip that receives the chip-select (CS) from the motherboard that selects the memory module for access. When CS is activated, the intercepting decoder chip illuminates a visual indicator on the extender card, allowing a user to locate a memory module being accessed. The exact translation or mapping from logical addresses of test programs to physical addresses of the memory modules is not needed, since the visual indicator shows which memory module is really being accessed, regardless of proprietary address mapping by north bridge chips. Operating system memory accesses are filtered out by a counter that counts accesses during a period set by a timer. When the number of accesses exceeds a threshold, the visual indicator is lit.

Abstract: A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

Abstract: Methods and apparatus are provided for allowing a component such as a processor on a programmable chip efficient access to properly transformed data an embedded memory. Circuitry is provided with the read data port associated with an embedded memory. The circuitry can be used to perform both static bit width configuration of an embedded memory as well as perform data transformation or data alignment of embedded memory read data. The circuitry can allow efficient data transformations including selection of half words and bytes as well as perform sign extension and zero extension of memory read data.

Abstract: There is provided an electronic system (10) comprising one or more functionality devices (16, 20, 21) and an electronic device adapted so that the one or more functionality devices (16, 20, 21) are locatable in proximity to the electronic device. The electronic device is operable to recognize the presence of the one or more functionality devices (16, 20, 21). Upon recognition of said one or more functionality devices (16, 20, 21), the electronic device is operable to perform one or more additional functionality features associated with said one or more functionality devices while said one or more functionality devices are in close proximity to the electronic device.

Abstract: A method is described for coalescing input/output (IO) interrupts to a virtual machine (VM) running on a host computer. At a virtualization layer of the host computer that supports execution of the VM receives an IO interrupt in response to a completion of an IO request of the VM, wherein a transmission of the IO request by the VM to an IO device bypasses the virtualization layer. The virtualization layer then determines whether the VM has responded to a most recently delivered IO interrupt to the VM by the virtualization layer, and drops the IO interrupt if the VM has not responded to the most recently delivered IO interrupt, thereby failing to deliver the IO interrupt to the VM.

Abstract: A PLC of building block type includes a switch module incorporating a switch part having N-to-N switch function between serial communication lines with a plurality of lines and a plurality of device modules individually incorporating device systems with various advanced-function device module characteristics. A CPU system having CPU functions of the PLC may be incorporated in the switch module, the switch module incorporating the CPU system and the plurality of device modules being connected together into a single body in a building block structure through module-connecting mechanisms. Dedicated serial communication lines each with a single line or a plurality of lines connect between the switch module incorporating the CPU system and each of the plurality of device modules such that a star-shaped serial communication network is formed with the switch module incorporating the CPU system as a central node and each of the plurality of device modules as a peripheral node.

Abstract: In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

Abstract: A message tracking and verifying system for verifying the correctness of messages being passed may comprise a tracking module for tracking a request message and a verifying module for verifying a response message. The tracking module may be configured to store a calculated source address and a calculated response address range. The verifying module may be configured to obtain an actual source address from the response message and an actual response address range for the response message. The correctness of the response message is determined based on the comparison of the calculated source address with the actual source address and the comparison of the calculated response address range with the actual response address range.

Abstract: An expansion card is provided that allows resources allocated to the expansion card to be shared with a different card. The expansion card comprises a coupling device that couples the expansion card to a data processing system. The expansion card also includes an identifier data structure that when queried by the data processing system, identifies the expansion card as a resource sharing expansion card. The data processing system reallocates one or more resources allocated to the expansion card to a different card coupled to the data processing system.

Abstract: A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

Abstract: A method for determining filter coefficients for a mismatched filter is disclosed. The method includes generating a code sequence having a code length, determining a length of the filter, and performing a modified least mean squares (LMS) algorithm. The length of the filter corresponds to coefficients of a transfer function of the filter, and the length of the filter is not equal to the code length. The filter coefficients are iteratively adjusted in the LMS algorithm until an error signal for each of the filter coefficients is below a threshold value.

Abstract: This solution relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a cell computing system. The invention provides a high performance machine vision system over the prior art and provides a method for executing image processing applications on a Cell and BPE3 image processing system. Moreover, implementations of the invention provide a machine vision system and method for distributing and managing the execution of image processing applications at a fine-grained level via a PCIe connected system. The hybrid system is replaced with the BPE3 and the switch is also eliminated from the prior in order to meet over 1 GB processing requirement.

Abstract: The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.

Abstract: A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

Abstract: A technique for automatically establishing device IDs for devices in a daisy chain cascade arrangement. For each device, a write ID operation is initiated at the device to cause the device to enter a generate/write ID mode. While in this mode, a first value is input to the device. The device generates a second value from the first value. The device outputs the generated second value from the device to a next device in the daisy chain cascade which uses the second value as a first value for the next device. The device then establishes its ID from the first value. The process is repeated for all devices in the daisy chain cascade arrangement.

Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.

Abstract: A communication control device in an audio visual device system has disconnection detection unit for detecting that an audio visual device is disconnected from the audio visual device system, device detection unit for detecting an audio visual device which has not acquired a logical address according to a device type, and control unit for performing control for causing the audio visual device without a logical address to acquire a logical address, when disconnection of a audio visual device is detected by the disconnection detection unit. With this configuration, in an audio visual device system in which an upper limit is set to the number of logical addresses according to a device type, it is possible to cause an audio visual device which cannot acquire a logical address according to the device type to acquire a logical address when it is made available.

Abstract: An electronic apparatus includes a first unit having a first power switch for turning on/off a data processing part, a hard disk drive device, a power supply part and the electronic apparatus, a second unit that is separated from the first unit, is supplied with the power from the power supply part in the first unit, and has a drive device of a detachable recording media and a second power switch having the same function as that of the first power switch, and a cable for communicating data between the first unit and the second unit and supplying power from the power supply part of the first unit to the second unit.

Abstract: An apparatus and method implemented in hardware and embedded software that improves performance, scalability, reliability, and affordability of Storage Area Network (SAN) systems or subsystems. The apparatus contains host computers (application servers, file servers, computer cluster systems, or desktop workstations), SAN controllers connected via a bus or network interconnect, disk drive enclosures with controllers connected via network interconnect, and physical drive pool or cluster of other data storage devices that share I/O traffic, providing distributed high performance centrally managed storage solution. This approach eliminates I/O bottlenecks and improves scalability and performance over the existing SAN architectures.

Abstract: A multi-protocol memory controller includes one or more memory channel controllers. Each of the memory channel controllers coupled to a single channel of DIMM, where the DIMM in each single channel operate according to a specific protocol. A protocol engine is coupled to the memory channel controllers. The protocol engine is configurable to accommodate one or more of the specific protocols. Finally, a system interface is coupled to the protocol engine and is configurable to provide electrical power and signaling appropriate for the specific protocols.

Abstract: A technique for sharing a fabric to facilitate off-chip communication for on-chip units includes dynamically assigning a first unit that implements a first communication protocol to a first portion of the fabric when private fabrics are indicated for the on-chip units. The technique also includes dynamically assigning a second unit that implements a second communication protocol to a second portion of the fabric when the private fabrics are indicated for the on-chip units. In this case, the first and second units are integrated in a same chip and the first and second protocols are different. The technique further includes dynamically assigning, based on off-chip traffic requirements of the first and second units, the first unit or the second unit to the first and second portions of the fabric when the private fabrics are not indicated for the on-chip units.

Abstract: The host interface module is configured to receive a plurality of I/O request which includes an associated priority; create an I/O request queue for each associated priority; define a threshold value for the queue length for each of the plurality of I/O request queues; and determine if the queue length for one of the plurality of the I/O request queue corresponding to the associated priority is less than the defined threshold value for the queue length for the one of the plurality of the I/O request queues. If the queue length of the one of the plurality of I/O request queues is more than the defined threshold value for the queue then the host interface module is further configured to rejecting the I/O request and sending a queue full message; wherein the threshold value for the queue length is based on the processing rate of the I/O requests in the plurality of the I/O request queues.

Abstract: Methods and systems for advancing to another service from a plurality of services in a digital radio broadcast receiver are described. The methods and systems include the steps of receiving an instruction to advance to another service from a man-machine interface of the digital radio broadcast receiver, selecting an entry from a set of entries stored in a memory of the digital radio broadcast receiver responsive to the instruction, wherein each entry identifies a service, and wherein at least some of said services correspond to services identified as receivable, tuning to a first service identified by the selected entry, rendering content received on the first service at the digital radio broadcast receiver, and updating the set of entries stored in the memory of the digital radio broadcast receiver based on at least one criteria.

Abstract: An STB (104), which reduces operating load of a user and causes a television (101) and an amplifier (102) to be appropriately linked, includes: a receiving unit (204) which receives a broadcast signal including an application program written in Java (registered trademark); a Java VM (403) which executes the application program; a CEC (401b4) which performs HDMI-CEC-compliant communication between each of the television (101) and the amplifier (102); and a device control library (405e) which performs conversion between data handled by an application program and data communicated by the CEC (401b4), so that the television (101) and the amplifier (102) can be controlled by the application program executed by the Java VM (403).

Abstract: A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output.

Abstract: An input port is assigned to a SAS expander device. An output port is assigned to the SAS expander device. The output port and the input port are defined to be paired with each other as a primary subtractive port. Only a SAS initiator address is programmed in the route table of the SAS expander. An OPEN command is sent out the output port upon receiving the OPEN command into the input port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device. An OPEN command is sent out the input port upon receiving the OPEN command into the output port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device.

Abstract: A computer motherboard includes a display controller, a digital visual interface integrated (DVI-I) connector, and a switching unit. The switching unit includes four first terminals, two second terminals, and a control terminal. Two of the first terminals are respectively connected to clock and data pins of a first display data channel (DDC) of the display controller, the other two first terminals are respectively connected to clock and data pins of a second DDC of the display controller, and the second terminals are respectively connected to DDC clock and DDC data pins of the DVI-I connector. The control terminal is connected to a hot plug detect pin of the DVI-I connector to detect a voltage and correspondingly control the second terminals to be respectively connected to the two first terminals connected to the clock and data pins of the first DDC or the second DDC.

Abstract: In a presentation system, a source device provides uncompressed presentation content in an HDMI format. A first conversion device converts the uncompressed presentation content to an uncompressed second format and entirely transmits the uncompressed presentation content in the second format along an electrically conductive member. A second conversion device receives the uncompressed presentation content in the second format from the conductive member and converts the uncompressed presentation content to the HDMI format. For example, the conductive member may be that of a coaxial cable.

Abstract: A method, apparatus, and program product retrieve data for a task utilizing demand-based direct memory access (“DMA”) requests. The method comprises, prior to the execution thereof, analyzing a first portion of a task to determine whether data required for execution thereby is stored in a local memory, and, in response to determining that the data required for execution by the first portion of the task is not stored in the local memory, proactively issuing a first DMA request for the data required for execution by the first portion of the task. The method further comprises, in response to determining that the first DMA request is not complete, determining whether to proactively analyze a second portion of the task prior to the execution thereof for a determination whether data required for execution thereby is stored in the local memory.

Abstract: A control device having an output pin expansion function and an output pin expansion method thereof are provided. The method includes: connecting at least a shift register unit having a plurality of data transmission pins to a control unit such that the shift register unit can receive strobe signals, a multi-bit data stream, clock signals and enable signals generated by the control unit; sending an enable signal by the control unit so as to allow the shift register unit to shift and store each bit of a multi-bit data stream according to a clock signal generated by the control unit; and sending a strobe signal by the control unit so as to allow the shift register unit to output the multi-bit data in parallel format as opposed to the received serial format through the plurality of data transmission pins, thereby allowing a processing device to interface with more devices (such as LED state indicators) than its fixed number of dedicated output pins would conveniently allow, thus saving costs and board space.

Abstract: Exemplary embodiments relate to a method for swapping PPRC secondary device definitions from a subchannel set other than zero to subchannel set zero. The method comprises identifying a PPRC primary and secondary device, wherein the PPRC primary device definitions reside at subchannel set zero and the PPRC secondary device definitions reside at a subchannel set other than subchannel set zero, initiating a PPRC device definition substitution operation to substitute the PPRC primary device definitions within the subchannel set where the PPRC secondary device definition resides and substitute the PPRC secondary device definitions within the subchannel set where the PPRC primary device definitions resides, storing the control block information for each PPRC device whose device definitions are to be substituted, and storing the PPRC primary device definitions within the subchannel set where the PPRC secondary device definition resides and storing the PPRC secondary device definitions within subchannel set zero.