Abstract: In some embodiments, a wireless device (e.g., a cell phone) has a transceiver, a processor, and a memory. The processor store periodic downlink (DL) data received from the transceiver in a periodic DL buffer in the memory, aperiodic DL data received from the transceiver in an aperiodic DL buffer in the memory, periodic uplink (UL) data in a periodic UL buffer in the memory, and aperiodic UL data in an aperiodic UL buffer in the memory. The processor determines in what order to handle the stored data in the periodic and aperiodic DL and UL buffers and handles the stored data in the determined order.

Abstract: An assessment of computing system performance may include evaluating, within a time window, the average latency of operations of a certain type and size with respect to a peer performance model constructed for operations of the same type and size. Such evaluation may result in the determination of a peer performance score. The peer performance score may be used to label performance characteristics of the computing system that are measured within the same time window. A library of such performance characteristics labeled with respective peer performance scores may be constructed by examining multiple computing systems, and such library may be used to construct one or more symptom models. Each symptom model may map a performance characteristic to a symptom severity score, which indicates the severity of a symptom of the computing system.

Abstract: An USB multiplexing single-wire interface unit comprises a D+ pin, a D? pin, a control bit register for USB and single-wire interface modes and a USB controller, the USB controller comprises an EOP detection module and a single-wire interface EOP detection module. The USB mode or the single-wire interface mode is selected according to mode identification of the control bit register for USB and single-wire interface modes, an output of the EOP detection module is selected as a USB EOP trigger signal in the USB mode, and an output of the single-wire interface EOP detection module is selected as a USB EOP trigger signal in the single-wire interface mode.

Abstract: Electronic devices are disclosed. In some implementations, an electronic device includes a device interface to provide an interface to a host and detect link information associated with a bandwidth provided by the device interface in communicating with the host, a processor coupled to the device interface to be in communication with the host, and structured to be operable to control operations of the electronic device in response to a request received from the host through the device interface, and a clock generator coupled to provide the device interface and the processor with clock signals to be used to operate the device interface and the processor. The processor is configured to adjust frequencies of the clock signals based on the link information.

Abstract: Provided is a signal processing device including a communication unit which receives packets transmitted from an event-driven vision sensor including a sensor array including sensors generating event signals when a change in intensity of incident light is detected, a buffer memory in which the packets are temporarily stored, and a readout control unit which forcibly reads out the packets from the buffer memory in a case in which predetermined conditions are satisfied.

Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.

Abstract: A transmitter device includes a transmitter circuit, a voltage generator circuit, and a calibration circuit. The transmitter circuit is configured to selectively operate in a calibration mode or a normal mode in response to a first control signal, in which the transmitter circuit has a first output terminal and a second output terminal. The voltage generator circuit is configured to generate a bias voltage, in which the bias voltage has a first level in the calibration mode and has a second level in the normal mode, and the first level is different from the second level. The calibration circuit is configured to be turned on in the calibration mode according to the bias voltage and a second control signal, in order to calibrate a level of the first output terminal and a level of the second output terminal.

Abstract: Aspects for Long Short-Term Memory (LSTM) blocks in a recurrent neural network (RNN) are described herein. As an example, the aspects may include one or more slave computation modules, an interconnection unit, and a master computation module collectively configured to calculate an activated input gate value, an activated forget gate value, a current cell status of the current computation period, an activated output gate value, and a forward pass result.

Abstract: A broadcast subsystem of a processor system includes: a set of broadcast buses, each broadcast bus in the set of broadcast buses electrically coupled to a subset of primary memory units in the set of primary memory units; a primary memory unit queue: configured to store a first set of data transfer requests associated with the set of primary memory units; and electrically coupled to the data buffer a broadcast scheduler: electrically coupled to the primary memory unit queue; electrically coupled to the set of broadcast buses; and configured to transfer source data from the data buffer to a target subset of primary memory units in the set of primary memory units via the set of broadcast buses based on the set of data transfer requests stored in the primary memory unit queue.

Abstract: A device receives priority data identifying priorities relevant to a configuration of an application and receives feature data identifying features related to the priorities. The device identifies technology services based on a machine learning-driven analysis of the priorities and features, and includes data identifying the technology services as part of the reference architecture. The device provides data identifying the reference architecture for display via an interface, and receives data identifying technology services that have been selected by a user. The device updates scores associated with the reference architecture based on the selected technology services. A subset of the scores may be updated to reflect one or more degrees to which one or more cloud service providers offer the selected technology services. The device provides data identifying the updated scores for display via the interface to allow the scores to be used to select a particular cloud service provider.

Abstract: Methods, systems, and processes to simplify networking setup complexity for security agents implemented in cybersecurity computer environments are disclosed. A request with an intentionally bad Transport Layer Security (TLS) handshake is transmitted from an agent to a server. An indication is received from the server that the request has been rejected. A Round Trip Time (RTT) of the request and rejection of the request is determined. The server is then pinged based on the RTT. The subsequent pinging does not require whitelisting of an additional port and does not negatively interact with network intermediaries that support protocol detection.

Abstract: An information handling system includes a USB-C port and a USB-C power delivery controller. The USB-C power delivery controller includes connection preference information, and is configured to detect that a device has been plugged into the USB-C port, determine that the device supports a first connection type and a second connection type, determine that the first connection type has a higher connection priority than the second connection type, and establish a connection between the information handling system and the device utilizing the second connection type based upon the connection preference information.

Abstract: A method for a system includes forming within an app running upon a user smart-device, an ephemeral ID having data associated with a server and anonymous data, outputting the ephemeral ID to a first receiver associated with a first computer and to a second receiver associated with a second computer system separate from the first, receiving from the first receiver an identifier and a nonce, providing the identifier and the nonce to the server, receiving from the server a token associated with the first computer system authorizing access to the first computer system but not the second computer system by the user smart-device, storing the token for facilitated authentication of the user smart-device, and providing the token to the first receiver.

Abstract: A storage management technique involves: determining a spare degree of physical storage space of a file system and access characteristics of the file system; determining, using a provision operation classification model and based on the spare degree and the access characteristics, a target storage provision operation to be performed for the file system from multiple storage provision operations, wherein the multiple storage provision operations include at least a storage space expansion operation and a storage space reclamation operation, and the provision operation classification model characterizes an association relationship between different spare degrees and different access characteristics of the file system and the multiple storage provision operations; and performing the determined target storage provision operation for the file system. Accordingly, a better balance is achieved between storage efficiency and I/O performance.

Abstract: The present disclosure generally relates to efficient transfer layer packet (TLP) fragmentation in a data storage device. For an unaligned read from host flow, an amount of data sufficient to be aligned is transferred to the memory device from the host while the remainder of the data is stored in cache of the data storage device to be delivered to memory device at a later time. For an unaligned write to host flow, the unaligned data is written to cache and at a later time the cache will be flushed to the host device. In both cases, while the total data would be unaligned, a portion of the data is placed in cache so that the data not placed in cache is aligned. The data in cache is delivered at a later point in time.

Abstract: A policy-based printing system is implemented to allow access to a private domain to print using a public domain. The private domain includes private servers that store documents. The public domain includes servers and a printing device. A public policy server uses a domain list and a protocol connection with a private authentication server to validate a user and identify which private domain to access. The public policy server receives requests from the printing device to process a print job of a document in the private domain. A mobile device is used to coordinate the retrieval and printing of the document using an application. A kiosk may be used to send the document to the printing device from the mobile device.

Abstract: Scalable segment cleaning for log-structured file systems (LFSs) includes determining counts of segment cleaners and virtual nodes, with each virtual node being associated with a plurality of objects. Each virtual node is assigned to a selected segment cleaner. Based at least on the assignments, performing, for each virtual node, segment cleaning of the objects by the assigned segment cleaner. A portion, less than all, of the virtual nodes are reassigned to a newly selected segment cleaner based on a change of the count of the segment cleaners and/or a change of the count of the virtual nodes. Based at least on the reassignments, segment cleaning of the objects is performed, for each reassigned virtual node, by the reassigned segment cleaner. In some examples, the objects comprise virtual machine disks (VMDKs) and the segment cleaning uses a segment usage table (SUT) to track segment usage and identify segment cleaning candidates.

Abstract: Apparatus and method for selective overwrite protection of data stored in a non-volatile memory (NVM) with fine precision. In some embodiments, a write command is received from a host device to write one or more blocks of data having associated logical addresses to the NVM. A read operation is performed in response to the write command to read a tag value associated with each block. The write command is disallowed in response to the tag value indicating a protected version of the block having the associated logical address is already stored at the selected location. The tag value may be a key version value indicative of a version of an encryption key used to encrypt user data in the data block and whether the block is write-protected.

Abstract: NFC terminal devices and corresponding integrated circuit cards (ICCs) use NFC Type 4 tags as a protocol interface for complex or encrypted communication protocols that are not natively supported by the NFC terminal devices. A smartphone acting as an NFC terminal may block applications and/or protocols other than NFC data exchange formatted (NDEF) messages. An ICC applet supporting an advanced function uses designated memory locations for the transfer of commands normally supported at an application level. Both the terminal side and the ICC applet may check the designated memory locations for updated data in the absence of protocol-level message controls.

Abstract: Database-aware snapshotting is disclosed. It is determined that a first snapshot of a database having a plurality of shards should be taken. Each shard has a corresponding snapshot sidecar container of a plurality of snapshot sidecar containers. A consensus state among the plurality of snapshot sidecar containers that the first snapshot should be taken is determined. A snapshot controller is directed to take the first snapshot of the database, the first snapshot generating a shard volume snapshot for each shard of a plurality of shards. Subsequent to the snapshot controller taking the first snapshot of the database, each snapshot sidecar container is informed to allow activity on the corresponding shard.

Abstract: Disclosed herein are systems and method for protecting an endpoint device from malware. In one aspect, an exemplary method comprises performing, by a light analysis tool of the endpoint, a light static analysis of a sample, terminating the process and notifying the user when the process is malware, performing light dynamic analysis when the process is not malware based on the light static analysis, when the process is clean based on the light dynamic analysis, enabling the process to execute, when the process is malware, terminating the process and notifying the user, and when the process is suspicious pattern, suspending the process, setting a level of trust, sending the sample to a sandbox, terminating the process and notifying the user when the process is a malware based on received final verdict, enabling the process to resume executing when the process is determined as being clean based on the final verdict.

Abstract: Provided is a compatibility promotion method, storage medium, and system for HDMI. The method comprises steps of reading EDID to be analyzed of a display device; defining a situation 1 as the existence of non-standard timing of EDID to be analyzed; defining a situation 2 as the bandwidth of the resolution supported by the display is greater than a maximum bandwidth of a HDMI intermediate device; if the EDID to be analyzed meets the situation 1, after modifying the timing of the EDID to be analyzed into an HDMI standard timing, and then forwarding the modified EDID same to an input source device; if the EDID to be analyzed meets the situation 2, modifying a color depth sampling format and a color format of a resolution greater than a maximum bandwidth of the HDMI intermediate device in the EDID to be analyzed to be within a supported bandwidth range.

Abstract: Memory of a storage system is made available (i.e., exposed) for use as host memory of a host, for example, as an extension of the main memory of the host. The host may be directly connected to an internal fabric of the data storage system. Portions of the storage system memory (SSM) may be allocated for use as host memory, and this may be communicated to the host system. The host OS and applications executing thereon then may make use of the SSM as if it were memory of the host system, for example, as second-tier persistent memory. The amount of SSM made available may be dynamically increased and decreased. The SSM may be accessed by the host system as memory; i.e., in accordance with memory-based instructions, for example, using remote direct memory access instructions. The SSM may be write protected using mirroring, vaulting and other techniques.

Abstract: One of the various aspects of the invention is related to suggesting various techniques for improving the tamper-resistibility of hardware. The tamper-resistant hardware may be advantageously used in a transaction system that provides the off-line transaction protocol. Amongst these techniques for improving the tamper-resistibility are trusted bootstrapping by means of secure software entity modules, a new use of hardware providing a Physical Unclonable Function, and the use of a configuration fingerprint of a FPGA used within the tamper-resistant hardware.

Abstract: An integrated circuit includes a plurality of configurable units, each configurable unit having two or more corresponding sections. The plurality of configurable units is arranged in a serial arrangement to form a chain of sections of the configurable units. A data bus is connected to the plurality of configurable units which communicates data at a clock rate. The chain of sections is to receive and write a series of tensors at the clock rate at a first end section of the chain of sections, and sequentially propagate the series of tensors through individual sections within the chain of sections at the clock rate. The chain of sections is to output the series of tensors at a second end section of the chain of sections. The chain of sections is to also output the series of tensors at an intermediate section of the chain of sections.

Abstract: A storage device having an improved operation speed includes a memory device and a memory controller for controlling the memory device. The memory controller includes: a Device-To-Host (DTH) information generator configured to generate DTH information to be transferred to a host, a host memory accessor configured to provide the host with the DTH information received from the DTH information generator and an interrupt signal generator configured to output, to the host, an interrupt signal notifying that the DTH information has been provided to the host, based on a request from the host memory accessor.

Abstract: Many signal processing, machine learning and scientific computing applications require a large number of multiply-accumulate (MAC) operations. This type of operation is demanding in both computation and memory. Process in memory has been proposed as a new technique that computes directly on a large array of data in place, to eliminate expensive data movement overhead. To enable parallel multi-bit MAC operations, both width- and level-modulating memory word lines are applied. To improve performance and provide tolerance against process-voltage-temperature variations, a delay-locked loop is used to generate fine unit pulses for driving memory word lines and a dual-ramp Single-slope ADC is used to convert bit line outputs. The concept is prototyped in a 180 nm CMOS test chip made of four 320×64 compute-SRAMs, each supporting 128× parallel 5 b×5 b MACs with 32 5 b output ADCs and consuming 16.6 mW at 200 MHz.

Abstract: Method for creating and managing programmable logic controller (PLC) solution comprises connecting existing PLC solution to a cloud network, and connecting from a user device to a virtualization server. A graphical representation of a pin layout of a PLC is displayed on a GUI on the user device. An input comprising selection of a first pin, a sensor or an actuator configured to be coupled with the PLC via the first pin, and a parameter for the operation of the selected sensor or the selected actuator is received on the GUI. The received input is sent from the user device to the virtualization server. An executable PLC application for execution on the PLC is received on the user device. The PLC application is configured to operate and/or monitor the PLC according to the received input. The PLC application is sent to the PLC for being deployed on the PLC.

Abstract: Apparatuses relating to periodic Universal Serial Bus (USB) transaction scheduling at fractional bus intervals are described. In one embodiment, an apparatus includes a receptacle to receive a plug of a first device and a second device; a transceiver circuit coupled to the receptacle; and a controller circuit to: switch between a first mode for a first class of data transfers and a second mode for a second class of data transfers, wherein the first class preempts the second class of data transfers, schedule a data transfer with the transceiver circuit for a first endpoint of the first device at a first service interval of a bus interval when in the first mode, and schedule a data transfer with the transceiver circuit for a second, different endpoint of the second device at a second service interval that is smaller than the first service interval when in the first mode.

Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.

Abstract: An electronic system includes a host device and a storage device including a first memory device of a volatile type and a second memory device of a nonvolatile type. The first memory device is accessed by the host device through a memory-mapped input-output interface and the second memory device is accessed by the host device through a block accessible interface. The storage device provides a virtual memory region to the host device such that a host-dedicated memory region having a first size included in the first memory device is mapped to the virtual memory region having a second size larger than the first size.

Abstract: Systems and methods are provided for upgrading wireless network devices, such as access points (APs). When a first AP needs an upgrade, a network controller of the first AP may identify and select a neighbor AP. The radio(s) of the neighbor AP can be split into multiple logical radios, at least one of which includes a backup virtual AP (VAP). The backup VAP can support client devices originally supported by the first AP, allowing those client devices to roam to the neighbor AP while the first AP is upgrading, and without needing to re-associate with the neighbor AP. From the client device perspective, it appears as though they are still being supported by the first AP. Upon upgrading the first AP, the client devices can roam back to the first AP (without needing to re-associate with the first AP). No downtime is experienced, and no RF holes are generated.

Abstract: An electronic control unit includes a first non-volatile memory configured such that a control program is written thereto; a second non-volatile memory configured such that an identifier is written thereto; and a processor. The identifier is for verifying whether the control program is correct. The processor chooses either an identifier contained in advance in the control program or an identifier written in the second non-volatile memory, depending on how and/or whether the identifier is written in the second non-volatile memory. The processor verifies whether the control program is correct based on the chosen identifier.

Abstract: The present disclosure advantageously provides a system and method for protocol layer tunneling for a data processing system. A system includes an interconnect, a request node coupled to the interconnect, and a home node coupled to the interconnect. The request node includes a request node processor, and the home node includes a home node processor. The request node processor is configured to send, to the home node, a sequence of dynamic requests, receive a sequence of retry requests associated with the sequence of dynamic requests, and send a sequence of static requests associated with the sequence of dynamic requests in response to receiving credit grants from the home node. The home node processor is configured to send the sequence of retry requests in response to receiving the sequence of dynamic requests, determine the credit grants, and send the credit grants.

Abstract: The embodiments herein creates DCT mechanisms that initiate a DCT at the time the updated data is being evicted from the producer cache. These DCT mechanisms are applied when the producer is replacing the updated contents in its cache because the producer has either moved on to working on a different data set (e.g., a different task) or moved on to working on a different function, or when the producer-consumer task manager (e.g., a management unit) enforces software coherency by sending Cache Maintenance Operations (CMO). One advantage of the DCT mechanism is that because the direct cache transfer takes place at the time the updated data is being evicted, by the time the consumer begins its task, the updated contents have already been placed in its own cache or another cache within the cache hierarchy.

Abstract: A non-destructive testing (NDT) system can provide a tree model of an inspection on a display of an NDT device and on a web page configured in a web browser on a computing device coupled to the NDT device. Inspection data acquired using the NDT device can be provided in real-time as the inspection data is associated with a node configured in the tree model. The NDT system can generate an inspection tree model based on an inspection template including a template tree model. Defect properties, inspection instructions, and/or image transforms can be applied to nodes of the template tree model such that the generated inspection tree model includes the applied defect properties, inspection instructions, and/or image transforms, which can then be applied to the inspection data acquired at the inspection point location corresponding to each node.

Abstract: A fault detection system including one or more sensors onboard a vehicle to detect a characteristic of the vehicle and generate sensor signals corresponding to the characteristic, a processor onboard the vehicle to receive the sensor signals, generate one or more fast Fourier transform vectors based on the sensor signals so that the one or more fast Fourier transform vectors are representative of the characteristic, generate an analysis model from a time history of the fast Fourier transform vectors, and determine, using the analysis model, a degree to which the one or more fast Fourier transform vectors could have been generated by the analysis model, and an indicator to communicate an operational status of the vehicle to an operator or crew member of the vehicle based on the degree to which the one or more fast Fourier transform vectors could have been generated by the analysis model.

Abstract: Methods, systems and computer program products for monitoring delivered packages are provided. Aspects include receiving, by a co-processor, a data stream and performing processing on the data stream. Aspects also include writing, by the co-processor, a data record into the output buffer. Based on a determination that the data record should replace a most recently stored data record in a cache, aspects include providing, by the co-processor to the cache controller, an instruction for the cache controller to write the data record to a location in the cache obtained from a most recently used address register. Based on a determination that the data record should not replace the most recently stored data record in the cache, aspects include writing, by the cache controller, the data record to an available location in the cache.

Abstract: Systems and methods for force-supplying cached API call data are disclosed. A system may comprise a memory storing instructions and at least one processor configured to execute instructions to perform operations including: receiving initial order data from a user device, the initial order data comprising a product identifier, a user identifier, and a promotion identifier; determining an initial reduction amount based on the received product identifier and promotion identifier; mapping the initial reduction amount to a cache identifier; caching the initial order data and the cache identifier; receiving an order request from a device associated with the user identifier, the order request being associated with the promotion identifier; calling an API to complete the order request; detecting a failure of the API attempting to complete the order request; retrieving the cache identifier; determining a final reduction amount; and completing the order request using the final reduction amount.

Abstract: A storage array for providing data storage services includes persistent storage and a storage array manager. The persistent storage stores data. The storage array manager obtains a request for solicited data using a request queue corresponding to a requesting host; responds, based on the solicited data, to the request using a response queue corresponding to the requesting host; makes a determination that the request implicates multiple hosts; and in response to the determination: distributes unsolicited data, based on the request, to the multiple hosts using the data stored in the persistent storage.

Abstract: In some examples, a system comprises a memory device for storing instructions and a processor which executes instructions causing the system to perform operations comprising receiving an instruction to transfer a state of a first device to a second device, and packaging information relating to the state of the first device in a file. The packaging of the information relating to the state of the first device includes recording each application executing on the first device in a list maintained in the file, and transferring the file containing information relating to the state of the first device to the second device, either directly or indirectly based on an availability of connections between the first device and the second device. The file, when processed by the second device, causes the second device to reproduce the state of the first device. In some example, reproducing the state of the first device includes the second device downloading, from one or more of the locations, one or more of the applications.

Abstract: The invention introduces a non-transitory computer program product for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

Abstract: In a method, identifiers are obtained of N to-be-upgraded nodes. An upgrade sequence of the N to-be-upgraded nodes is set according to the identifiers of the N to-be-upgraded nodes. A backup node of each to-be-upgraded node is determined according to the upgrade sequence of the N to-be-upgraded nodes, to obtain node backup information. A backup node of the Xth to-be-upgraded node is at least one node in a set that includes a to-be-upgraded node prior to the Xth to-be-upgraded node and a to-be-upgraded node following the (X+[Z+1])th to-be-upgraded node. Z is a ratio of a time required by the Xth to-be-upgraded node for migrating back service data to an online upgrade time of the Xth to-be-upgraded node. The node backup information is sent to the N to-be-upgraded nodes.

Abstract: A board work machine control device, which appropriately executes the real-time tracing while reducing the processing load, includes a processor configured to control a board work machine and a tracing data output device configured to output tracing data which is outputted from the processor to an exterior, and the tracing data output device includes a tracing register configured to temporarily store the tracing data which is outputted from the processor; a ring buffer where for the tracing data which is temporarily stored in the tracing register to be written, and an output control section configured to reduce the tracing data for the output on a real-time basis.

Abstract: Methods and systems for enabling sizing of storage array resources are provided. Resources of a storage array can include, for example, cache, memory, SSD cache, central processing unit (CPU), storage capacity, number of hard disk drives (HDD), etc. Generally, methods and systems are provided that enable efficient predictability of sizing needs for said storage resources using historical storage array use and configuration metadata, which is gathered over time from an install base of storage arrays. This metadata is processed to produce models that are used to predict resource sizing needs to be implemented in storage arrays with certainty that takes into account customer-to-customer needs and variability. The efficiency in which the sizing assessment is made further provides significant value because it enables streamlining and acceleration of the provisioning process for storage arrays.

Abstract: Embodiments of the inventive concepts disclosed herein are directed to systems and methods for using field-loadable input/output (I/O) tables. An avionics hardware unit may include one or more processors. An operational software of the avionics hardware unit may perform a plurality of operations for processing avionics data in safety or data-integrity driven applications. An I/O table may be loaded onto the avionics hardware. The I/O table may be selected from a plurality of I/O tables loadable onto the avionics hardware for operation with the operational software. The selected I/O table may include a configuration of rules. The rules may be assigned according to the configuration to each of the plurality of operations to configure the behavior of the respective operations for processing the avionics data. The configuration may be different from that of others of the plurality of I/O tables in configuring the plurality of operations of the operational software.

Abstract: A method for controlling an SSD (Solid State Disk), performed by a processing unit when loading and executing a driver, including: obtaining a data access command including information indicating a namespace, a command type, and a logical storage address; determining one of a plurality of storage mapping tables according to the namespace; reading a physical location corresponding to the logical storage address from the determined storage mapping table; generating a data access request including information indicating a request type and the physical location; and issuing the data access request to a SSD.

Abstract: A computing system is disclosed. The computing system according to one embodiment of the present disclosure comprises: a memory device for storing an application program; a processor for executing a loader for loading data of the application program into a memory space allocated for execution of the application program; a local memory having a width corresponding to the size of a register of the processor; and a constant memory having a width smaller than that of the local memory, wherein, according to the size of constant data included in the application program, the processor loads the constant data into one of the local memory and the constant memory.

Abstract: In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.

Abstract: A control system for a heating, ventilation, and/or air conditioning (HVAC) system having control circuitry includes a microcontroller, a memory that stores a plurality of addresses, a communication bus configured to communicatively couple the microcontroller and a device of a plurality of devices of the HVAC system, and a fault register. The plurality of addresses includes a plurality of compatible addresses, a plurality of incompatible addresses, or any combination thereof. The microcontroller is programmed to monitor a signal address of a signal on the communication bus. The microcontroller is programmed to compare the signal address with the plurality of addresses, detect a fault event, and record the fault event in the fault register. Detection of the fault event includes the signal address not corresponding to a compatible address, the signal address corresponding to an incompatible address, or any combination thereof.