Abstract: There are provided a signal generator capable of flexibly increasing the number of taps while realizing high-speed emphasis switching and an emphasis switching method using the signal generator. A signal generator includes: an emphasis addition circuit including at least one finite impulse response (FIR) filter unit that generates an emphasis waveform pattern by adding an emphasis to a pattern of a pulse amplitude modulation (PAM) signal including multi-values which are two or more values; and a tap value setting unit that switches M tap values C(0), C(?1), . . . , and C(1?M) and sets the M tap values C(0), C(?1), . . . , and C(1?M) to each FIR filter unit according to an emphasis switching request from a DUT 100. The FIR filter unit is configured on an FPGA or an ASIC.

Abstract: Techniques are disclosed for the use of local buffers integrated into the execution units of a vector processor architecture. The use of local buffers results in less communication across the interconnection network implemented by vector processors, and increases interconnection network bandwidth, increases the speed of computations, and decreases power usage.

Abstract: Apparatuses, systems, and techniques to indicate contextual information to be used by available logical processors. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to indicate a first set of contextual information to be used by a first subset of available processors.

Abstract: Disclosed is bandwidth allocation method for a PCIe external plug-in card. The method comprises: configuring a south bridge chip to successively connect to a connector, an adapter card and a PCIe external plug-in card by means of an I2C bus, wherein the PCIe external plug-in card stores preset configuration information; in response to a system being powered on, the south bridge chip acquiring, by means of the I2C bus, the preset configuration information stored in the PCIe external plug-in card; and the south bridge chip determining a target bandwidth according to the preset configuration information, and allocating a bandwidth to the PCIe external plug-in card on the basis of the target bandwidth.

Abstract: A transfer processing device includes an arithmetic instruction number acquisition circuit, a buffer circuit, a transfer information acquisition circuit, and a software processing unit. The arithmetic instruction number acquisition circuit acquires a transfer instruction number corresponding to transfer information which is information related to the next transfer destination of an arithmetic instruction. The buffer circuit is arranged between the arithmetic instruction number acquisition circuit and the transfer information acquisition circuit, and temporarily stores and relays the arithmetic instruction and the arithmetic instruction number supplied from the arithmetic instruction number acquisition circuit to the transfer information acquisition circuit. The transfer information acquisition circuit acquires transfer information on the basis of the arithmetic instruction number, and gives the acquired transfer information to the arithmetic instruction.

Abstract: Disclosed herein are systems, methods, and computer-readable media for upgrading vSmart controllers. In one aspect, a method includes an edge router receiving a notification from a vSmart controller that an upgrade to the controller will occur. The notification can be dynamically triggered by a centralized network management system. In some embodiments, the vSmart controller can run as a virtual machine (VM) and maintains a control plane connection with one or more edge routers in an overlay network. In response to the notification, a length of time of an expiry timer in which the edge router attempts to connect to the vSmart controller can be increased, and the edge router can connect to the vSmart controller once the increased length of time has passed.

Abstract: Embodiments of the present disclosure provide a method for starting a computing device, a computing device, and a program product. The method includes: acquiring type information on a plurality of host bus adapter (HBA) cards of the computing device; determining a first group of HBA cards in the plurality of HBA cards based on the type information; and starting an operating system of the computing device by preventing scanning of disks connected to the first group of HBA cards. In this way, the number of storage apparatuses that need to be scanned before starting the operating system is reduced, and the starting of the operating system of the computing device is accelerated.

Abstract: A method and apparatus are disclosed for enhancing operable functionality of input source code files from a software program by preprocessing input source code files with codeword processing operations to generate a plurality of preprocessed input source code files, identifying candidate code snippets by pruning one or more preprocessed input source code files that do not meet a similarity threshold measure for library functions stored in the system library, and identifying at least a first validated code snippet from the one or more candidate code snippets that matches a first library function stored in the system memory on the basis of at least first and second matching metrics.

Abstract: A storage system that has blades and fabric modules connects to a customer legacy network that has a first, active switch and a second, passive switch. A first link aggregation group (LAG) is configured active and includes ports of the first, active switch that connect via links to the first and second fabric modules of the storage system. A second LAG is configured passive and includes ports of the second, passive switch that connect via links to the first and second fabric modules. A multi-chassis link aggregation group (MLAG, MCLAG or MC-LAG) is configured and includes ports of the first and second fabric modules that connect via links to the first and second switches.

Abstract: The multi-path server comprises four circuits. Each circuit comprises a PCH, an extended module, a switch module, and a CPU. An extended module in the first circuit is connected to a switch module in the second circuit, a switch module in the third circuit, and a switch module in the fourth circuit. An extended module in the third circuit is connected to a switch module in the fourth circuit. A switch module performs switching action according to a target partition instruction, and a PCH performs in-place action according to the target partition instruction, such that each said circuit forms a target partition, and PMSYNC signals are interconnected in the target partition. A multi-path server signal interconnection system is also provided.

Abstract: An apparatus configured to allow data values to be written into the plurality of memory cells of the memory device at a first speed upon connecting to a first host via a first configuration of the plurality of connectors; and allow data values to be written into the plurality of memory cells at a second speed faster than the first speed, upon connecting to a second host via a second configuration of the plurality of connectors.

Abstract: Method for managing the state of buttons of peripheral devices of computers of any type (including smartphones, tablets, etc.) is considered in the context of safe management by the corresponding segment of the user interface in the automatic or remote mode without direct tactile communication with the user, but at his desire. Manipulation with buttons on peripheral devices is carried out by the button state change agent which is built in directly the peripheral device who in turn is controlled on the channel of interaction of the computer and the peripheral device means of the software of the computer. Based on the technical result of using appropriately implemented additional user interfaces are also claimed methods of remote management of the computer, interactions between applications and also implementations of the answering machine, PBX and the VoIP-Cell gateway on the basis of smartphones.

Abstract: There are provided a connecting method and an electrical component unit for connecting between a plurality of electrical devices and a determination unit configured to determine a state for each of the plurality of electrical devices. The connecting method includes: providing wire harnesses having a plurality of types for each of which the number of input terminals is different, the wire harnesses being provided with a connector in which an input circuit is built, the input circuit having the input terminals respectively connected to the plurality of electrical devices and outputting a serial signal; selecting one wire harness of the wire harnesses, the one wire harness including the number of the input terminals corresponding to the number of the plurality of electrical devices; and connecting between the plurality of electrical devices and the determination unit via the one wire harness.

Abstract: Techniques are provided for persistent memory file system reconciliation. As part of the persistent memory file system reconciliation, high level file system metadata associated with a persistent memory file system of persistent memory is reconciled. Client access to the persistent memory file system is inaccessible until reconciliation of the high level file system metadata has completed. A first scanner is executed to traverse pages of the persistent memory in order to fix local inconsistencies associated with the pages. A local inconsistency of a first set of metadata or data of a page is fixed using a second set of metadata or data of the page. The first scanner is executed asynchronously in parallel with processing client I/O directed to the persistent memory file system.

Abstract: A memory device A memory device can include a serial interface (IF) configured to receive an operational code (op code) of no less than 16-bits and provide a plurality of acknowledgement values in response to the received op code. Controller circuits can generate the plurality of acknowledgement values, including first and second acknowledgement values in response to an operation indicated by the op code being completed, and first and third acknowledgement values in response to an operation indicated by the op code not being completed. Memory circuits can be configured to execute the operation indicated by the op code to access the nonvolatile memory cells, and indicate to the controller circuits whether or not the operation was completed. The first, second and third acknowledgement values can be different multi-bit values. Corresponding methods and systems are also disclosed.

Abstract: A broadcast subsystem of a processor system includes: a set of broadcast buses, each broadcast bus in the set of broadcast buses electrically coupled to a subset of primary memory units in the set of primary memory units; a primary memory unit queue: configured to store a first set of data transfer requests associated with the set of primary memory units; electrically coupled to the data buffer a broadcast scheduler: electrically coupled to the primary memory unit queue; electrically coupled to the set of broadcast buses; and configured to transfer source data from the data buffer to a target subset of primary memory units in the set of primary memory units via the set of broadcast buses based on the set of data transfer requests stored in the primary memory unit queue.

Abstract: The present invention provides a switching method of a universal serial bus (USB) switch element for an in-vehicle host system. According to a switching command, a hub controller of a switch device controls a switch element to switch from a device mode to a host mode, so that one of multiple mobile terminals connected to the switch element is in the host mode; or alternatively, the switch element is controlled to be switched from the host mode to the device mode so that multiple peripheral devices are in the device mode.

Abstract: A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.

Abstract: An image forming apparatus includes a controller configured to perform a storage printing process that includes storing print data in a dedicated memory, which is a portable memory set as a storage destination to store the print data in the storage printing process when attached to a dedicated port among a plurality of ports, and causing a print engine to perform printing according to the print data stored in the dedicated memory in response to an operation received via a user interface, prior to the storage printing process, set one of the plurality of ports as the dedicated port, in response to a portable memory being attached to a port, determine whether the portable memory is the dedicated memory and the port is the dedicated port, and provide a notification when determining that the portable memory is the dedicated memory but the port is not the dedicated port.

Abstract: According to one embodiment, a memory system includes nonvolatile memory including a plurality of memory areas and a memory controller. A read operation includes a first operation of reading data from a memory cell array and a second operation of transmitting at least a part of the read data to the memory controller. The memory controller determines, when executing the read operation in a first memory area and a second memory area in parallel, priorities of the second operation in the first memory area and the second operation in the second memory area based on a result of comparison between (A) a first total time period of the read operation in the first memory area and (B) a second total time of the read operation in the second memory area.

Abstract: An example hierarchical switching device may include sub-switches that form a fully interconnected all-to-all network, wherein the sub-switches comprise external output ports, internal input ports and internal output ports to exchange packets with other sub-switches within the fully interconnected all-to-all network. The switching device may further include a deadlockable storage, a storage partition and a switch controller. The deadlockable storage space is exclusively assigned to an internal input port of the internal input ports of the sub-switch including the deadlockable storage. The storage partition is exclusively assigned to an external output port of the external output ports and exclusively assigned to the internal input port. The switch controller is to route a packet destined for an external output port of a sub-switch through the internal input port of the sub-switch to the deadlockable storage or if the packet corresponds to the external output port, to the storage partition.

Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.

Abstract: A method and apparatus for generating a game character model, a processor, and a terminal are provided. The method includes: a user map corresponding to a two-dimensional user image to be used is acquired; the user map is mapped to an initial map of a game character to obtain a mapped map of the game character; and the mapped map and a game character grid are fused to generate a game character model. The present disclosure solves the technical problem that face mapping and face fusion provided in the related art are generally applied to two-dimensional face images but cannot be applied to a three-dimensional game environment.

Abstract: A communication device may cause a first wireless interface of the communication device to send a first signal in a case where a state of the communication device is a respondent state. The respondent state may be a state in which a Wi-Fi connection is able to be established between the communication device and a terminal device. The first signal may be sent from the first wireless interface before a Bluetooth connection is established between the communication device and a terminal device. The communication device may cause the first wireless interface to send a second signal in a case where a state of the communication device is a non-respondent state. The non-respondent state may be a state in which the Wi-Fi connection is not able to be established. The second signal may be sent from the first wireless interface before the Bluetooth connection is established.

Abstract: A control method for controlling an information processing apparatus configured to generate print data using a first program that is interpreted and executed when operating in the information processing apparatus and a second program that is compiled in advance and is usable from the first program, includes acquiring a first generation logic for generating print data, the first generation logic being modifiable and linked with a printer configured to execute printing; generating a second generation logic by modifying the first generation logic at least partially; generating print data to be printed by the printer using input image data and the second generation logic; and transmitting, to the printer, the print data generated in the generating the print data. The first generation logic is executed using the second program.

Abstract: A computer-implemented method for facilitating large data transfers from a first data management system to a second data management system is disclosed. The method comprises receiving data from the first data management system by a first buffer component, rerouting, upon the first buffer component reaching a predefined fill-level, dynamically the received data to a second buffer component, wherein the second buffer component is adapted to process the rerouted received data, forwarding, by the second buffer component, the rerouted data once the first buffer component is again ready for receiving the rerouted data from the second buffer component, and sending, by a sending component, the data buffered in the first component to the second data management system.

Abstract: A non-destructive testing (NDT) system can provide a tree model of an inspection on a display of an NDT device and on a web page configured in a web browser on a computing device coupled to the NDT device. Inspection data acquired using the NDT device can be provided in real-time as the inspection data is associated with a node configured in the tree model. The NDT system can generate an inspection tree model based on an inspection template including a template tree model. Defect properties, inspection instructions, and/or image transforms can be applied to nodes of the template tree model such that the generated inspection tree model includes the applied defect properties, inspection instructions, and/or image transforms, which can then be applied to the inspection data acquired at the inspection point location corresponding to each node.

Abstract: In one example, a method involves performing an initial discovery process that includes querying a storage array, and identifying, based on the query, one or more hosts that are registered with the storage array. This initial discovery process is performed automatically without requiring user action to identify the one or more hosts. The method additionally includes presenting a list of discovered hosts, receiving a selection input from a user specifying one or more of the hosts in the list, retrieving, from the storage array, information associated with each of the respective hosts, and making the information available to a user.

Abstract: Writing data in a storage system that includes a first type of storage device and a second type of storage device, including: selecting, for one or more unprocessed write requests, a target storage device type from the first type of storage device and the second type of storage device; issuing a first group of write requests to the first type of storage device, the first group of write requests addressed to one or more locations selected in dependence upon an expected address translation to be performed by the first type of storage device; and issuing a second group of write requests to the second type of storage device, the second group of write requests addressed to one or more locations selected in dependence upon a layout of memory in the second type of storage device.

Abstract: A storage system having high reliability and IO processing performance is realized. The storage system includes: a first arithmetic unit configured to receive an input and output request and perform data input and output processing; a first memory connected to the first arithmetic unit; a plurality of storage drives configured to store data; a second arithmetic unit; and a second memory connected to the second arithmetic unit. The first arithmetic unit instructs the storage drive to read data, the storage drive reads the data and stores the data in the second memory, the second arithmetic unit stores the data stored in the second memory in the first memory, and the first arithmetic unit transmits the data stored in the first memory to a request source of a read request for the data.

Abstract: Methods and systems for a networked storage system are provided. One method includes predicting an IOPS limit for a plurality of storage pools based on a maximum allowed latency of each storage pool, the maximum allowed latency determined from a relationship between the retrieved latency and a total number of IOPS from a resource data structure; identifying a storage pool whose utilization has reached a threshold value, the utilization based on a total number of IOPS directed towards the storage pool and a predicted IOPS limit; detecting a bully workload based on a numerical value determined from a total number of IOPS issued by the bully workload for the storage pool and a rising step function; and implementing a corrective action to reduce an impact of the bully workload on a victim workload.

Abstract: A model designer improves the security of a machine learning model in certain embodiments. Instead of storing the model in a central location, the training data used to build and train the model is stored across several different databases and/or datacenters. The training data is divided into portions and stored as a circular linked list across these databases and/or datacenters. The model designer retrieves the training data and incrementally builds and trains the model using the training data. The incremental error and bias of the model is used to locate training data between datacenters. Additionally, fake training data is appended to the circular linked list and the model designer tracks how much training data is used before hitting fake training data.

Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product that involve accessing a storage device. The method includes determining, in response to an access to the storage device via a first path being determined as timeout, whether an error on the first path is of a first error type. The method further includes causing the access to be suspended for at least a scheduled time period if the error on the first path is of the first error type. The method further includes resuming the access via a second path after the scheduled time period expires. With embodiments of the present disclosure, the capability of processing the problem of failure in accessing a storage device and the stability in accessing a storage device can be improved.

Abstract: According to one embodiment, a controller of a memory system executes communication with a host in conformity with a standard of NVM express. When fetching a command from a first submission queue, the controlled of the memory system determine the number of commands to be fetched with the number of free slots among a plurality of slots included in a first completion queue as an upper limit. The controller fetches the determined number of commands from the first submission queue.

Abstract: An imaging apparatus to which an accessory apparatus is attachable includes a camera controller configured to communicate with the accessory apparatus. The camera controller receives first information on a data size receivable by the accessory apparatus, performs a setting for a data size to be transmitted to the accessory apparatus based on the first information, and communicate with the accessory apparatus based on the setting.

Abstract: An image forming apparatus includes a controller configured to perform a storage printing process that includes storing print data in a dedicated memory, which is a portable memory set as a storage destination to store the print data in the storage printing process when attached to a dedicated port among a plurality of ports, and causing a print engine to perform printing according to the print data stored in the dedicated memory in response to an operation received via a user interface, prior to the storage printing process, set one of the plurality of ports as the dedicated port, in response to a portable memory being attached to a port, determine whether the portable memory is the dedicated memory and the port is the dedicated port, and provide a notification when determining that the portable memory is not the dedicated memory but the port is the dedicated port.

Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

Abstract: In some embodiments, a wireless device (e.g., a cell phone) has a transceiver, a processor, and a memory. The processor store periodic downlink (DL) data received from the transceiver in a periodic DL buffer in the memory, aperiodic DL data received from the transceiver in an aperiodic DL buffer in the memory, periodic uplink (UL) data in a periodic UL buffer in the memory, and aperiodic UL data in an aperiodic UL buffer in the memory. The processor determines in what order to handle the stored data in the periodic and aperiodic DL and UL buffers and handles the stored data in the determined order.

Abstract: An assessment of computing system performance may include evaluating, within a time window, the average latency of operations of a certain type and size with respect to a peer performance model constructed for operations of the same type and size. Such evaluation may result in the determination of a peer performance score. The peer performance score may be used to label performance characteristics of the computing system that are measured within the same time window. A library of such performance characteristics labeled with respective peer performance scores may be constructed by examining multiple computing systems, and such library may be used to construct one or more symptom models. Each symptom model may map a performance characteristic to a symptom severity score, which indicates the severity of a symptom of the computing system.

Abstract: An USB multiplexing single-wire interface unit comprises a D+ pin, a D? pin, a control bit register for USB and single-wire interface modes and a USB controller, the USB controller comprises an EOP detection module and a single-wire interface EOP detection module. The USB mode or the single-wire interface mode is selected according to mode identification of the control bit register for USB and single-wire interface modes, an output of the EOP detection module is selected as a USB EOP trigger signal in the USB mode, and an output of the single-wire interface EOP detection module is selected as a USB EOP trigger signal in the single-wire interface mode.

Abstract: Electronic devices are disclosed. In some implementations, an electronic device includes a device interface to provide an interface to a host and detect link information associated with a bandwidth provided by the device interface in communicating with the host, a processor coupled to the device interface to be in communication with the host, and structured to be operable to control operations of the electronic device in response to a request received from the host through the device interface, and a clock generator coupled to provide the device interface and the processor with clock signals to be used to operate the device interface and the processor. The processor is configured to adjust frequencies of the clock signals based on the link information.

Abstract: Provided is a signal processing device including a communication unit which receives packets transmitted from an event-driven vision sensor including a sensor array including sensors generating event signals when a change in intensity of incident light is detected, a buffer memory in which the packets are temporarily stored, and a readout control unit which forcibly reads out the packets from the buffer memory in a case in which predetermined conditions are satisfied.

Abstract: A transmitter device includes a transmitter circuit, a voltage generator circuit, and a calibration circuit. The transmitter circuit is configured to selectively operate in a calibration mode or a normal mode in response to a first control signal, in which the transmitter circuit has a first output terminal and a second output terminal. The voltage generator circuit is configured to generate a bias voltage, in which the bias voltage has a first level in the calibration mode and has a second level in the normal mode, and the first level is different from the second level. The calibration circuit is configured to be turned on in the calibration mode according to the bias voltage and a second control signal, in order to calibrate a level of the first output terminal and a level of the second output terminal.

Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.

Abstract: Aspects for Long Short-Term Memory (LSTM) blocks in a recurrent neural network (RNN) are described herein. As an example, the aspects may include one or more slave computation modules, an interconnection unit, and a master computation module collectively configured to calculate an activated input gate value, an activated forget gate value, a current cell status of the current computation period, an activated output gate value, and a forward pass result.

Abstract: A broadcast subsystem of a processor system includes: a set of broadcast buses, each broadcast bus in the set of broadcast buses electrically coupled to a subset of primary memory units in the set of primary memory units; a primary memory unit queue: configured to store a first set of data transfer requests associated with the set of primary memory units; and electrically coupled to the data buffer a broadcast scheduler: electrically coupled to the primary memory unit queue; electrically coupled to the set of broadcast buses; and configured to transfer source data from the data buffer to a target subset of primary memory units in the set of primary memory units via the set of broadcast buses based on the set of data transfer requests stored in the primary memory unit queue.

Abstract: A device receives priority data identifying priorities relevant to a configuration of an application and receives feature data identifying features related to the priorities. The device identifies technology services based on a machine learning-driven analysis of the priorities and features, and includes data identifying the technology services as part of the reference architecture. The device provides data identifying the reference architecture for display via an interface, and receives data identifying technology services that have been selected by a user. The device updates scores associated with the reference architecture based on the selected technology services. A subset of the scores may be updated to reflect one or more degrees to which one or more cloud service providers offer the selected technology services. The device provides data identifying the updated scores for display via the interface to allow the scores to be used to select a particular cloud service provider.

Abstract: Methods, systems, and processes to simplify networking setup complexity for security agents implemented in cybersecurity computer environments are disclosed. A request with an intentionally bad Transport Layer Security (TLS) handshake is transmitted from an agent to a server. An indication is received from the server that the request has been rejected. A Round Trip Time (RTT) of the request and rejection of the request is determined. The server is then pinged based on the RTT. The subsequent pinging does not require whitelisting of an additional port and does not negatively interact with network intermediaries that support protocol detection.

Abstract: An information handling system includes a USB-C port and a USB-C power delivery controller. The USB-C power delivery controller includes connection preference information, and is configured to detect that a device has been plugged into the USB-C port, determine that the device supports a first connection type and a second connection type, determine that the first connection type has a higher connection priority than the second connection type, and establish a connection between the information handling system and the device utilizing the second connection type based upon the connection preference information.

Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.