Abstract: A communication system for inter-chip communication includes system processors that communicate with one another via data channels of a communication bus. A processor designated as a master processor assumes control of the transmission to the other processor designated as a slave processor. A data channel is operated in a separate physical communication bus for each data communication direction.

Abstract: A memory module includes a counter configured to count a number of commands received from a host to generate a counted number and provide the counted value to the host, a memory device configured to receive an operating frequency and an operating voltage from that host that are determined based on the counted number, and a serial presence detect (SPD) configured to store the operating frequency and operating voltage.

Abstract: Merchant hosted checkout as described herein allows merchants to process mobile payments via a customized user payment interface (“checkout interface”). The merchant hosted checkout provides dynamic user interface (UI) instructions and user input requirements based on the country and mobile network (carrier) associated with each transaction.

Abstract: The present disclosure includes methods and apparatuses for power management. One method includes transferring data between a memory and a controller via an input/output (I/O) bus, and adjusting an amount of power consumed in association with transferring the data by throttling the I/O bus.

Abstract: A solid state disk and a data moving method are disclosed. The SSD includes a storage medium and a control chip, where storage space of the storage medium is divided into at least two blocks for storing data, and the control chip includes: a service processing module sends a moving command to a moving module; and the moving module receives the moving command; read valid data from the source block according to the moving command, and perform ECC checking on the valid data; and write checked data into a blank page of the destination block. The SSD can control movement of data from a source block to a blank page of a destination block; compared with a data moving process in which read and write are separated, a path that data moving passes through is simple and reduce impact of the data moving process on performance of the SSD.

Abstract: Embodiments disclosed herein are related to systems and methods for attributing disk Input/Output (IO) to one or more system entities. A disk IO attribution context is generated that defines disk IO utilization parameters for a system entity. A pointer is attached to the system entity that points to the disk IO attribution context. The pointer is exposed to system components of an underlying computer system. The pointer prompts the system components to report the disk IO utilization parameters when the system components have performed a disk IO operation for the system entity. The disk IO utilization parameters reported by the one or more system components are recorded in the disk IO attribution context.

Abstract: According to one embodiment, a method for queuing a transaction request. The method may include receiving, by a processor, at least one transaction request from a transaction processing system. The method may also include storing the at least one received transaction request in a queue within a 64-bit storage system. The method may further include monitoring a 31-bit storage system. The method may also include determining at least one control block within the monitored 31-bit storage system is available. The method may further include transmitting the at least one stored transaction request to the monitored 31-bit storage system.

Abstract: A processor has an execution pipeline that executes microinstructions and an instruction translator that translates architectural instructions into the microinstructions. The instruction translator has a memory that holds microcode instructions and provides a fetch quantum of a plurality of microcode instructions per clock cycle, a queue that holds microcode instructions provided by the memory, and a branch decoder that decodes the fetch quantum to detect local branch instructions, causes microcode instructions of the fetch quantum up to but not including a first-in-program-order local branch instruction to be written to the queue, and prevents the first-in-program-order local branch instruction and following microcode instructions of the fetch quantum from being written to the queue. Local branch instructions are resolved by the instruction translator rather than the execution pipeline.

Abstract: A method begins with a set of storage units receiving a plurality of sets of non-locking write requests from a plurality of computing devices. The method continues with each storage unit storing an encoded data slice of a respective one of the non-locking write requests of each set and sending a write response regarding the respective one of the non-locking write requests. The method continues with a computing device determining whether a threshold number of write responses regarding a corresponding one of the plurality of sets of non-locking write requests has an expected ordering indication. When the threshold number of write responses has the expected ordering indication, the method continues with the computing device sending a set of write finalize requests to the set of storage units to facilitate finalizing storing the set of encoded data slices of the corresponding one of the plurality of sets of non-locking write requests.

Abstract: Messaging between a companion device and an accessory device is controlled such that different modes of communication may be utilized. The different modes can implement different messaging strategies, each of which is intended for efficient power management, in view of the limited electrical power that is typically available at the accessory device. A received request message for sending from the companion device to the accessory device is sent if predetermined conditions apply, and similarly for messages from the accessory device to the companion device.

Abstract: A computer-implemented method for controlling data transfer for data processing includes: receiving a data set by a first processor; storing the data set in a buffer by the first processor; and transferring, from the buffer to a queue by the first processor, a batch data set including all data sets stored in the buffer during a time interval, under a condition that the queue is not accessed by a second processor while the transferring is being performed, wherein the batch data set is to be processed by the second processor. In the method, the time interval is adjusted depending on a state of the queue.

Abstract: An example method is described to provide fault tolerance in a virtualized computing environment with a first fault domain and a second fault domain. The method may comprise determining whether a first primary virtualized computing instance and a first secondary virtualized computing instance are both in the first fault domain. The method may comprise: in response to determination that the first primary virtualized computing instance and first secondary virtualized computing instance are both in the first fault domain, selecting a second secondary virtualized computing instance from the second fault domain; migrating the first secondary virtualized computing instance from a first host to a second host; and migrating the second secondary virtualized computing instance from the second host to the first host, thereby swapping the first secondary virtualized computing instance in the first fault domain with the second secondary virtualized computing instance in the second fault domain.

Abstract: Provided are a portable device, a wearable device, and a system including the same for setting a reception of a notification message in the wearable device. The portable device includes: a wireless communicator configured to receive, from a wearable device via wireless communication, information regarding a notification setting; and a controller configured to identify an event and to determine, based on the received information, whether to transmit a notification to the wearable device in response to the identified event.

Abstract: Encryption/authentication circuitry includes an encryption portion having a first number of encryption lanes, each encryption lane including a plurality of encryption stages, and keyspace circuitry including a plurality of key lanes corresponding to a predetermined maximum number of channels. Each key lane has key storage stages corresponding to the encryption stages, and includes key memories for the predetermined maximum number of channels. Key channel selection circuitry for each stage selects a key from among the key memories at that stage. An authentication portion includes a second number of authentication lanes, hash key storage for the predetermined maximum number of channels, partial hash state storage for the predetermined number of channels, and hash channel selection circuitry.

Abstract: Random numbers within a processor may be scarce, especially when multiple hardware threads are consuming them. A local random number buffer can be used by an execution core to better manage allocation and consumption of random numbers. The buffer may operate in a number of modes, and allow any hardware thread to use a random number under some conditions. In other conditions, only certain hardware threads may be allowed to consume a random number. The local random number buffer may have a dynamic pool of entries usable by any hardware thread, as well as reserved entries usable by only particular hardware threads. Further, a user-level instruction is disclosed that can be stored in a wait queue in response to a random number being unavailable, rather than having the instruction's request for a random number simply be denied. The random number buffer may also boost performance and reduce latency.

Abstract: A method of locating peripheral device applied to an electronic device is disclosed. The electronic device is connected or electrically connected to a peripheral device. The method includes: obtaining a first location information via a locating unit; when the first connecting unit is connected to the second connecting unit, sending the first location information to the peripheral device; after the first connecting unit and the second connecting unit are separated, obtaining the first location information sent by the second transmitter via the first transmitter; obtaining a second location information via the locating unit; comparing the first location information and the second location information to determine the relative position of the electronic device and the peripheral device.

Abstract: A Thunderbolt sharing console includes a high speed switch electrically coupled to at least one Thunderbolt host, a MCU coupled to the high speed switch, and a Thunderbolt interface chip coupled to the high speed switch, wherein the MCU can be used to control the high speed switch for determining which one of the at least one Thunderbolt host is coupled to the Thunderbolt interface chip.

Abstract: An image processing apparatus includes a decoding unit, a deblocking filter, and a sample adaptive offset processing unit. The decoding unit is configured to perform a decoding process for a coded stream to generate an image. The deblocking filter is configured to store a block, a corresponding block of which on a current edge is not input, in a memory, out of blocks of the image generated by the decoding unit and read the block stored in the memory at timing when the corresponding block is input, to perform a filter process. The sample adaptive offset processing unit is configured to perform a sample adaptive offset process by using a pixel of the block that has been subjected to the filter process by the deblocking filter.

Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A link interface communicatively couples the send component to the receive component. The link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.

Abstract: An MFP receives an electronic mail from a mail server. The MFP prints an image based on an attached file of the received electronic mail. If an abort instruction is not accepted during printing of the image, the electronic mail is deleted from the mail server after printing of the image based on the attached file of the received electronic mail is completed. On the other hand, if the abort instruction is accepted during printing of the image, printing of the image is aborted without deleting the received electronic mail from the mail server.

Abstract: A data processing method executed by a processor included in an information processing device, the data processing method includes reserving a storage area of a memory when a reservation request is detected; acquiring a number of cache misses indicating that desired data is not capable of being read from a storage area to be accessed, the cache misses having occurred in response to a request for access to the storage area; and setting a new storage area so as to shift the new storage area from the reserved storage area when it is determined that the acquired number is larger than or equal to a given value.

Abstract: An information processing apparatus, backup method, and program product that enable efficient differential backup. In one embodiment, an information processing apparatus for files stored in a storage device includes: a metadata management unit for managing metadata of files stored in the storage device; a map generation unit for generating a map which indicates whether metadata associated with an identification value uniquely identifying a file in the storage device is present or absent; and a backup management unit for scanning the metadata to detect files that have been created, modified, or deleted since the last backup, and storing at least a data block and the metadata for a detected file in a backup storage device as backup information in association with the identification value.

Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A link interface communicatively couples the send component to the receive component. The link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.

Abstract: Provided is a method and apparatus for an adaptive context switching for a fast block input/output. The adaptive context switching method may include: requesting, by a process, an input/output device to perform an input/output of data; comparing a Central Processing Unit (CPU) effectiveness based on whether the context switching is performed; and performing the input/output through the context switching to a driver context of the input/output device, or directly performing, by the process, the input/output based on a comparison result of the CPU effectiveness.

Abstract: A method for effectively transmitting data, in which a switch is connected between a plurality host and storage, comprises steps of the following. First, the hosts recognize the storages via the switch, and revise a data transmission path within an original command, meanwhile transforming it into a specific command. Later, the switch receives the specific command, alternatively revises the data transmission path or not, and transforms the specific command into a standard command. The standard command is then transmitted to the storage. After receiving it, the storage is able to search for a corresponding host based on the data transmission path such that data is simply transmitted between the storage and its corresponding host. By employing the proposed method, the present invention is beneficial to reducing system complexity and raising data transmission efficiency.

Abstract: Activation rates of memory locations associated with memory addresses are monitored. The activation rates of the memory locations associated with the memory addresses are regulated. The regulating of the activation rates of the memory locations associated with the memory addresses includes selectively updating a cache with the memory addresses based on the activation rates.

Abstract: A customizable diagnostic meter is provided. The diagnostic meter includes a meter for performing a diagnostic test, wherein the meter includes a housing having a slot, and a module having one or more functions. The slot is configured to receive and removably secure at least a portion of the module. A customizable diagnostic meter kit including two or more modules configured to be inserted in a meter is also provided.

Abstract: A method and a system of standardizing data from devices such as medical simulators. The method includes receiving data from a device, determining by a computer type of information provided in the received data, converting the information into a predetermined format based on the determined type and generating a message based on the determined type, the message comprising the converted information in the predetermined format. In this method, type of the information is different based on a stage of a process in which the received data was provided.

Abstract: An information handling system is provided herein. The information handling system includes a controlling bridge having a plurality of bridge ports and at least one port extender coupled to one of the bridge ports of the controlling bridge to form an extended bridge. The port extender has a plurality of extension ports. The information handling system further includes an access point coupled to the port extender such that a wireless association between the access point and one or more stations appears as a logical bridge port to the controlling bridge and to an access controller system. The access point has a wireless transceiver to communication with the one or more stations. Associated methods are provided herein for providing wireless network access to a local area network.

Abstract: A remote distributed data store may be configured to process data updates received through invocation of a common API with reference to a common schema. A local data store may also be configured to process updates through the common API with reference to the common schema. Updates to the local data store may be mapped from the local data store schema to the common schema, and applied to the distributed data store. Updates to the distributed data store may be mapped from the common schema to the local data store schema. User identity may be verified to limit data synchronization to authorized users.

Abstract: The present application relates to a mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof. The mechanism is operative in an available state and a locked state. The mechanism comprises at least one context register and a bus interface for receiving a request. A filtering unit obtains information relating to a context of the received request. If in the available state, a managing unit loads the context register with the obtained context information; and grants access in response to the received request. If in the locked state, the managing unit detects whether the obtained context information matches with the context information stored in the context register; and if the obtained and stored context information match, grants access in response to the received request. Otherwise, access is denied.

Abstract: A system, device and method are provided for merging information from a plurality of network sources using a mobile device capable. The mobile device receives data of a first type from a first network source, then merges the received data with data of a different type stored at the mobile device to create a merged data set, the merging including matching an identifier associated with the received data against an identifier associated with the stored data. The merged data set is then merged with a data record at a different network source, this merging including matching an identifier associated with the merged data set against an identifier associated with the data record.

Abstract: Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.

Abstract: In a digital mixer, when a patch of a certain channel is changed, values of parameters of one port which has been connected to the certain channel is applied as parameters of a newly connected port, thereby enabling to hand over parameters of the one port which have been set for the certain channel. Further, when a newly connected port is already connected to another channel, the digital mixer asks the user whether or not to apply the parameters of the one port.

Abstract: A JBOD subsystem for providing storage to a host entity. The JBOD subsystem contains at least one external JBOD emulation controller coupled to the host entity for emulating IO operations in response to the IO requests and a set of at least one physical storage device coupled to the JBOD emulation controller for providing storage to the host entity through the JBOD emulation controller. The JBOD emulation controller defines at least one logical media unit (LMU) consisting of sections of the set of physical storage device (PSD) and communicates with the PSD through a point-to-point serial-signal interconnect. As an example, the point-to-point serial-signal interconnect can be a Serial ATA IO device interconnect.

Abstract: Embodiments of a system and method are disclosed. One embodiment is an I2C compatible device. The I2C compatible device includes an SDA interface for connection to an SDA line and a single-line I2C module configured to transmit a sync word from the SDA interface over the SDA line and following the sync word, to transmit I2C data from the SDA interface over the SDA line such that digital data is communicated via a single line. In an embodiment, the sync word is a sync byte+NACK.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame.

Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Abstract: A computer implemented method for predicting preferences of an observer for two images, the method comprising the steps of: receiving the first image and an associated salience map indicating regions of the first image that are likely to be scrutinized by the observer; receiving a content masking map indicating differences between the first image and the second image that the observer is likely to be able to perceive; determining a number of preference measures; and processing the salience map and the content masking map to determine a distribution of a set of values of the preference measures predicting the preferences of the observer for the first image and the second image, the set of values of the preference measures having a number of degrees of freedom.

Abstract: A method for combining storage array copy requests for a disk storage system is disclosed. The method may include receiving a BGC (background copy) request, determining that the BGC request satisfies a set of background copy (BGC) criteria, and adding, based on the determining, the BGC request to a sorted position in the wait accumulation queue (WAQ). The method may also include combining, based on a set of track combining criteria, the BGC request and an adjacent BGC request into a combined BGC request including data locations corresponding to the BGC request and to the adjacent BGC request. The method may also include replacing, in a sorted position in the WAQ, the BGC request and the adjacent BGC request with the combined BGC request, and moving, based on the set of BGC criteria, the combined BGC request to a BGC queue.

Abstract: Universal serial bus (USB) communication systems and methods are disclosed. In particular, aspects of the present disclosure optimize polling and scheduling of bulk data transfers from bulk endpoints connected through a USB connection. By reducing the amount of polling, and by favoring endpoints that are known to have data to transfer, unnecessary signaling is avoided. Reduction in signaling allows more data to be transferred in a shorter amount of time. Reducing the time required for a data transfer may allow for low power modes to be used, which in turn further saves power.

Abstract: A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.

Abstract: The memory module having a plurality of memory chips and a plurality of connections for connecting the memory module to a processor. At least part of the connections is configurable to be grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips (N?2).

Abstract: A communication device includes: a first communication section, a second communication section, a storage section, a determination section, and a control section. The first communication section communicates with a storage device based on predefined interface communication standards to perform data transfer. The second communication section communicates with an external device in a method other than the interface communication standards to perform data transmission. The storage section stores the selected error code that is previously defined to cause a bit error by noise. The determination section determines whether or not an error code indicated by the error information agrees with the selected error code. The control section, upon determination by the determination section that the error codes agrees with each other, gives the first communication section and the second communication section instructions for cancelling the data transfer and performing data re-transfer.

Abstract: Described herein are various systems and methods to automatically decide to aggregate data write requests in a distributed data store. A system initiates outgoing data write requests in synchronization with incoming data store commands, thereby facilitating low-latency read-back of the data. In response to an absence of data read requests, the system automatically changes such that each request includes two or more data sets, thereby breaking synchronization but consequently reducing traffic load on a switching network within the system. If the system later detects data read requests for previously stored data, the system will automatically change back to the original synchronized state, thereby decreasing the latency of accessing stored data. The system alternates between the modes of operation to achieve balance between low latency of data access and reduced traffic load on the switching network.

Abstract: An enhanced serial interface system is disclosed. The system includes a master component and a slave component. The master component is configured to operate in a standard mode and an enhanced mode for communication. The master component includes standard terminals and hybrid terminals. Only the standard terminals are used for communicating in the standard mode. The hybrid terminals and the standard terminals are used for communicating in the enhanced mode. The slave component is configured to operate in the enhanced mode and communicate with the master component.

Abstract: A radio access network (RAN) may determine that a quality-of-service (QOS) load of a first base station exceeds a QOS load high threshold. The RAN may further determine that a set of wireless communication devices (WCDs) served by the first base station are located within a geographic area nearby a second base station. The RAN may additionally determine that the set of WCDs are responsible for at least a predefined portion of the QOS load of the first base station, and may power on the second base station. If at some point a second QOS load of the second base station falls below a QOS load low threshold, the RAN may facilitate handover of at least one of the WCDs served by the second base station from the second base station to the first base station, and may power off the second base station.

Abstract: The virtual computer of the active system includes a memory configured of small regions grouped in a first group and small regions grouped in a second group. When a checkpoint is detected by the checkpoint detection unit, the transfer control unit suspends the virtual computer, copies, to a transfer buffer (not shown), data of the small regions in the first group among the small regions of the memory having been updated after a previous checkpoint, and after inhibiting writing to the small regions in the second group, restarts the virtual computer. Further, the transfer control unit copies data of the small regions, in which writing is inhibited, to the transfer buffer and releases write inhibit, and transfers the data of the small regions, having been copied to the transfer buffer, to the physical computer.

Abstract: Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a dynamic heterogeneous hashing module (DHHM) that includes multiple specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the multiple memory channels. The DHHM also includes a hashing-function selection block. The hashing-function selection block is operable to identify a requesting functional unit originating a current memory request and to select one of the specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.

Abstract: Frames of a video stream can be partitioned using source difference variance based partitioning before encoding. Variances between blocks of a current video frame and blocks of a previous unencoded video frame are determined. The current video frame can be partitioned into varying block sizes depending upon the magnitude of the variances. Blocks with low variance may be combined with other low variance blocks to form larger blocks, while blocks with high variance may be further partitioned into smaller blocks to improve encoding efficiency of the blocks. In cases where partitioning of a frame is unlikely to provide improved efficiency, the variation calculations may be skipped in favor of using fixed partitioning.