Data Transfer Specifying Patents (Class 710/33)
  • Patent number: 11855913
    Abstract: An example hierarchical switching device may include sub-switches that form a fully interconnected all-to-all network, wherein the sub-switches comprise external output ports, internal input ports and internal output ports to exchange packets with other sub-switches within the fully interconnected all-to-all network. The switching device may further include a deadlockable storage, a storage partition and a switch controller. The deadlockable storage space is exclusively assigned to an internal input port of the internal input ports of the sub-switch including the deadlockable storage. The storage partition is exclusively assigned to an external output port of the external output ports and exclusively assigned to the internal input port. The switch controller is to route a packet destined for an external output port of a sub-switch through the internal input port of the sub-switch to the deadlockable storage or if the packet corresponds to the external output port, to the storage partition.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 26, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Nicholas G. McDonald, Darel N. Emmot
  • Patent number: 11847077
    Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: December 19, 2023
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
  • Patent number: 11839820
    Abstract: A method and apparatus for generating a game character model, a processor, and a terminal are provided. The method includes: a user map corresponding to a two-dimensional user image to be used is acquired; the user map is mapped to an initial map of a game character to obtain a mapped map of the game character; and the mapped map and a game character grid are fused to generate a game character model. The present disclosure solves the technical problem that face mapping and face fusion provided in the related art are generally applied to two-dimensional face images but cannot be applied to a three-dimensional game environment.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 12, 2023
    Assignee: NETEASE (HANGZHOU) NETWORK CO., LTD.
    Inventors: Kang Chen, Weidong Zhang
  • Patent number: 11836407
    Abstract: A control method for controlling an information processing apparatus configured to generate print data using a first program that is interpreted and executed when operating in the information processing apparatus and a second program that is compiled in advance and is usable from the first program, includes acquiring a first generation logic for generating print data, the first generation logic being modifiable and linked with a printer configured to execute printing; generating a second generation logic by modifying the first generation logic at least partially; generating print data to be printed by the printer using input image data and the second generation logic; and transmitting, to the printer, the print data generated in the generating the print data. The first generation logic is executed using the second program.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: December 5, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tomohiro Suzuki, Kouta Murasawa
  • Patent number: 11838968
    Abstract: A communication device may cause a first wireless interface of the communication device to send a first signal in a case where a state of the communication device is a respondent state. The respondent state may be a state in which a Wi-Fi connection is able to be established between the communication device and a terminal device. The first signal may be sent from the first wireless interface before a Bluetooth connection is established between the communication device and a terminal device. The communication device may cause the first wireless interface to send a second signal in a case where a state of the communication device is a non-respondent state. The non-respondent state may be a state in which the Wi-Fi connection is not able to be established. The second signal may be sent from the first wireless interface before the Bluetooth connection is established.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: December 5, 2023
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Hirotaka Asakura, Munehisa Matsuda, Takuya Inoue
  • Patent number: 11816110
    Abstract: A computer-implemented method for facilitating large data transfers from a first data management system to a second data management system is disclosed. The method comprises receiving data from the first data management system by a first buffer component, rerouting, upon the first buffer component reaching a predefined fill-level, dynamically the received data to a second buffer component, wherein the second buffer component is adapted to process the rerouted received data, forwarding, by the second buffer component, the rerouted data once the first buffer component is again ready for receiving the rerouted data from the second buffer component, and sending, by a sending component, the data buffered in the first component to the second data management system.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: November 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Felix Beier, Knut Stolze, Reinhold Geiselhart, Luis Eduardo Oliveira Lizardo
  • Patent number: 11790519
    Abstract: A non-destructive testing (NDT) system can provide a tree model of an inspection on a display of an NDT device and on a web page configured in a web browser on a computing device coupled to the NDT device. Inspection data acquired using the NDT device can be provided in real-time as the inspection data is associated with a node configured in the tree model. The NDT system can generate an inspection tree model based on an inspection template including a template tree model. Defect properties, inspection instructions, and/or image transforms can be applied to nodes of the template tree model such that the generated inspection tree model includes the applied defect properties, inspection instructions, and/or image transforms, which can then be applied to the inspection data acquired at the inspection point location corresponding to each node.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 17, 2023
    Assignee: Baker Hughes, A GE Company, LLC
    Inventors: Ritwick Jana, Bryan David Maule, Michael Christopher Domke, thomas Durkee Britton, Robert Scott Lockhart
  • Patent number: 11775557
    Abstract: In one example, a method involves performing an initial discovery process that includes querying a storage array, and identifying, based on the query, one or more hosts that are registered with the storage array. This initial discovery process is performed automatically without requiring user action to identify the one or more hosts. The method additionally includes presenting a list of discovered hosts, receiving a selection input from a user specifying one or more of the hosts in the list, retrieving, from the storage array, information associated with each of the respective hosts, and making the information available to a user.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: October 3, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Sunil Kumar, Vinay Rao, Boaz Michaely, Arieh Don
  • Patent number: 11762764
    Abstract: Writing data in a storage system that includes a first type of storage device and a second type of storage device, including: selecting, for one or more unprocessed write requests, a target storage device type from the first type of storage device and the second type of storage device; issuing a first group of write requests to the first type of storage device, the first group of write requests addressed to one or more locations selected in dependence upon an expected address translation to be performed by the first type of storage device; and issuing a second group of write requests to the second type of storage device, the second group of write requests addressed to one or more locations selected in dependence upon a layout of memory in the second type of storage device.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: September 19, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Peter Kirkpatrick, John Colgrove, Neil Vachharajani
  • Patent number: 11740799
    Abstract: A storage system having high reliability and IO processing performance is realized. The storage system includes: a first arithmetic unit configured to receive an input and output request and perform data input and output processing; a first memory connected to the first arithmetic unit; a plurality of storage drives configured to store data; a second arithmetic unit; and a second memory connected to the second arithmetic unit. The first arithmetic unit instructs the storage drive to read data, the storage drive reads the data and stores the data in the second memory, the second arithmetic unit stores the data stored in the second memory in the first memory, and the first arithmetic unit transmits the data stored in the first memory to a request source of a read request for the data.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: August 29, 2023
    Assignee: HITACHI, LTD.
    Inventors: Takashi Nagao, Yuusaku Kiyota, Hideaki Monji, Tomohiro Yoshihara
  • Patent number: 11740798
    Abstract: Methods and systems for a networked storage system are provided. One method includes predicting an IOPS limit for a plurality of storage pools based on a maximum allowed latency of each storage pool, the maximum allowed latency determined from a relationship between the retrieved latency and a total number of IOPS from a resource data structure; identifying a storage pool whose utilization has reached a threshold value, the utilization based on a total number of IOPS directed towards the storage pool and a predicted IOPS limit; detecting a bully workload based on a numerical value determined from a total number of IOPS issued by the bully workload for the storage pool and a rising step function; and implementing a corrective action to reduce an impact of the bully workload on a victim workload.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: August 29, 2023
    Assignee: NETAPP, INC.
    Inventors: Nir Nossenson, Kai Niebergall, Francisco Jose Assis Rosa, John Jason Sprague, Omri Kessel
  • Patent number: 11726877
    Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product that involve accessing a storage device. The method includes determining, in response to an access to the storage device via a first path being determined as timeout, whether an error on the first path is of a first error type. The method further includes causing the access to be suspended for at least a scheduled time period if the error on the first path is of the first error type. The method further includes resuming the access via a second path after the scheduled time period expires. With embodiments of the present disclosure, the capability of processing the problem of failure in accessing a storage device and the stability in accessing a storage device can be improved.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: August 15, 2023
    Assignee: DELL PRODUCTS L.P.
    Inventors: Bing Liu, Zheng Li
  • Patent number: 11727306
    Abstract: A model designer improves the security of a machine learning model in certain embodiments. Instead of storing the model in a central location, the training data used to build and train the model is stored across several different databases and/or datacenters. The training data is divided into portions and stored as a circular linked list across these databases and/or datacenters. The model designer retrieves the training data and incrementally builds and trains the model using the training data. The incremental error and bias of the model is used to locate training data between datacenters. Additionally, fake training data is appended to the circular linked list and the model designer tracks how much training data is used before hitting fake training data.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: August 15, 2023
    Assignee: Bank of America Corporation
    Inventor: Vijay Kumar Yarabolu
  • Patent number: 11706523
    Abstract: An imaging apparatus to which an accessory apparatus is attachable includes a camera controller configured to communicate with the accessory apparatus. The camera controller receives first information on a data size receivable by the accessory apparatus, performs a setting for a data size to be transmitted to the accessory apparatus based on the first information, and communicate with the accessory apparatus based on the setting.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: July 18, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Atsushi Sugita, Kazumichi Sugiyama
  • Patent number: 11704065
    Abstract: According to one embodiment, a controller of a memory system executes communication with a host in conformity with a standard of NVM express. When fetching a command from a first submission queue, the controlled of the memory system determine the number of commands to be fetched with the number of free slots among a plurality of slots included in a first completion queue as an upper limit. The controller fetches the determined number of commands from the first submission queue.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: July 18, 2023
    Assignee: Kioxia Corporation
    Inventor: Shuichi Watanabe
  • Patent number: 11698762
    Abstract: An image forming apparatus includes a controller configured to perform a storage printing process that includes storing print data in a dedicated memory, which is a portable memory set as a storage destination to store the print data in the storage printing process when attached to a dedicated port among a plurality of ports, and causing a print engine to perform printing according to the print data stored in the dedicated memory in response to an operation received via a user interface, prior to the storage printing process, set one of the plurality of ports as the dedicated port, in response to a portable memory being attached to a port, determine whether the portable memory is the dedicated memory and the port is the dedicated port, and provide a notification when determining that the portable memory is not the dedicated memory but the port is the dedicated port.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: July 11, 2023
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Yutaka Urakawa
  • Patent number: 11681449
    Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: June 20, 2023
    Inventor: Dongsik Cho
  • Patent number: 11647420
    Abstract: In some embodiments, a wireless device (e.g., a cell phone) has a transceiver, a processor, and a memory. The processor store periodic downlink (DL) data received from the transceiver in a periodic DL buffer in the memory, aperiodic DL data received from the transceiver in an aperiodic DL buffer in the memory, periodic uplink (UL) data in a periodic UL buffer in the memory, and aperiodic UL data in an aperiodic UL buffer in the memory. The processor determines in what order to handle the stored data in the periodic and aperiodic DL and UL buffers and handles the stored data in the determined order.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: May 9, 2023
    Assignee: Charter Communications Operating, LLC
    Inventor: Volkan Sevindik
  • Patent number: 11632304
    Abstract: An assessment of computing system performance may include evaluating, within a time window, the average latency of operations of a certain type and size with respect to a peer performance model constructed for operations of the same type and size. Such evaluation may result in the determination of a peer performance score. The peer performance score may be used to label performance characteristics of the computing system that are measured within the same time window. A library of such performance characteristics labeled with respective peer performance scores may be constructed by examining multiple computing systems, and such library may be used to construct one or more symptom models. Each symptom model may map a performance characteristic to a symptom severity score, which indicates the severity of a symptom of the computing system.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: April 18, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Guoli Sun, David Nellinger Adamson, Gurunatha Karaje, Vladimir Semitchev
  • Patent number: 11609876
    Abstract: An USB multiplexing single-wire interface unit comprises a D+ pin, a D? pin, a control bit register for USB and single-wire interface modes and a USB controller, the USB controller comprises an EOP detection module and a single-wire interface EOP detection module. The USB mode or the single-wire interface mode is selected according to mode identification of the control bit register for USB and single-wire interface modes, an output of the EOP detection module is selected as a USB EOP trigger signal in the USB mode, and an output of the single-wire interface EOP detection module is selected as a USB EOP trigger signal in the single-wire interface mode.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: March 21, 2023
    Assignee: NANJING QINHENG MICROELECTRONICS CO., LTD.
    Inventor: Chunhua Wang
  • Patent number: 11586239
    Abstract: Electronic devices are disclosed. In some implementations, an electronic device includes a device interface to provide an interface to a host and detect link information associated with a bandwidth provided by the device interface in communicating with the host, a processor coupled to the device interface to be in communication with the host, and structured to be operable to control operations of the electronic device in response to a request received from the host through the device interface, and a clock generator coupled to provide the device interface and the processor with clock signals to be used to operate the device interface and the processor. The processor is configured to adjust frequencies of the clock signals based on the link information.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: February 21, 2023
    Assignee: SK hynix Inc.
    Inventors: Ku Ik Kwon, Kyeong Seok Kim, Su Ik Park, Yong Joon Joo
  • Patent number: 11553152
    Abstract: Provided is a signal processing device including a communication unit which receives packets transmitted from an event-driven vision sensor including a sensor array including sensors generating event signals when a change in intensity of incident light is detected, a buffer memory in which the packets are temporarily stored, and a readout control unit which forcibly reads out the packets from the buffer memory in a case in which predetermined conditions are satisfied.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: January 10, 2023
    Assignee: Sony Interactive Entertainment Inc.
    Inventor: Yosuke Kurihara
  • Patent number: 11546066
    Abstract: A transmitter device includes a transmitter circuit, a voltage generator circuit, and a calibration circuit. The transmitter circuit is configured to selectively operate in a calibration mode or a normal mode in response to a first control signal, in which the transmitter circuit has a first output terminal and a second output terminal. The voltage generator circuit is configured to generate a bias voltage, in which the bias voltage has a first level in the calibration mode and has a second level in the normal mode, and the first level is different from the second level. The calibration circuit is configured to be turned on in the calibration mode according to the bias voltage and a second control signal, in order to calibrate a level of the first output terminal and a level of the second output terminal.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: January 3, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Liang-Huan Lei, Shih-Hsiung Huang
  • Patent number: 11544207
    Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Paul Stonelake, Bryan Theodore Silbermann, Frank F. Ross
  • Patent number: 11531860
    Abstract: Aspects for Long Short-Term Memory (LSTM) blocks in a recurrent neural network (RNN) are described herein. As an example, the aspects may include one or more slave computation modules, an interconnection unit, and a master computation module collectively configured to calculate an activated input gate value, an activated forget gate value, a current cell status of the current computation period, an activated output gate value, and a forward pass result.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: December 20, 2022
    Assignee: CAMBRICON (XI'AN) SEMICONDUCTOR CO., LTD.
    Inventors: Qi Guo, Xunyu Chen, Yunji Chen, Tianshi Chen
  • Patent number: 11526767
    Abstract: A broadcast subsystem of a processor system includes: a set of broadcast buses, each broadcast bus in the set of broadcast buses electrically coupled to a subset of primary memory units in the set of primary memory units; a primary memory unit queue: configured to store a first set of data transfer requests associated with the set of primary memory units; and electrically coupled to the data buffer a broadcast scheduler: electrically coupled to the primary memory unit queue; electrically coupled to the set of broadcast buses; and configured to transfer source data from the data buffer to a target subset of primary memory units in the set of primary memory units via the set of broadcast buses based on the set of data transfer requests stored in the primary memory unit queue.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 13, 2022
    Assignee: Deep Vision Inc.
    Inventors: Raju Datla, Mohamed Shahim, Suresh Kumar Vennam, Sreenivas Aerra Reddy
  • Patent number: 11526777
    Abstract: A device receives priority data identifying priorities relevant to a configuration of an application and receives feature data identifying features related to the priorities. The device identifies technology services based on a machine learning-driven analysis of the priorities and features, and includes data identifying the technology services as part of the reference architecture. The device provides data identifying the reference architecture for display via an interface, and receives data identifying technology services that have been selected by a user. The device updates scores associated with the reference architecture based on the selected technology services. A subset of the scores may be updated to reflect one or more degrees to which one or more cloud service providers offer the selected technology services. The device provides data identifying the updated scores for display via the interface to allow the scores to be used to select a particular cloud service provider.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: December 13, 2022
    Assignee: Accenture Global Solutions Limited
    Inventors: Sakthikumar Kathiresan, Bibin George Thottikkara, Mukunda Ram Bhuyan, Sudipta Mukhopadhyaya, Srinivasan Sarangarajan
  • Patent number: 11522913
    Abstract: Methods, systems, and processes to simplify networking setup complexity for security agents implemented in cybersecurity computer environments are disclosed. A request with an intentionally bad Transport Layer Security (TLS) handshake is transmitted from an agent to a server. An indication is received from the server that the request has been rejected. A Round Trip Time (RTT) of the request and rejection of the request is determined. The server is then pinged based on the RTT. The subsequent pinging does not require whitelisting of an additional port and does not negatively interact with network intermediaries that support protocol detection.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: December 6, 2022
    Assignee: Rapid7, Inc.
    Inventors: Xi Yang, Paul Miseiko, Bingbin Li
  • Patent number: 11513575
    Abstract: An information handling system includes a USB-C port and a USB-C power delivery controller. The USB-C power delivery controller includes connection preference information, and is configured to detect that a device has been plugged into the USB-C port, determine that the device supports a first connection type and a second connection type, determine that the first connection type has a higher connection priority than the second connection type, and establish a connection between the information handling system and the device utilizing the second connection type based upon the connection preference information.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: November 29, 2022
    Assignee: Dell Products L.P.
    Inventors: Ken Nicholas, Marcin M. Nowak
  • Patent number: 11507286
    Abstract: A storage management technique involves: determining a spare degree of physical storage space of a file system and access characteristics of the file system; determining, using a provision operation classification model and based on the spare degree and the access characteristics, a target storage provision operation to be performed for the file system from multiple storage provision operations, wherein the multiple storage provision operations include at least a storage space expansion operation and a storage space reclamation operation, and the provision operation classification model characterizes an association relationship between different spare degrees and different access characteristics of the file system and the multiple storage provision operations; and performing the determined target storage provision operation for the file system. Accordingly, a better balance is achieved between storage efficiency and I/O performance.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: November 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Sicong Yao, Liang Huang, Ruipeng Yang, Jianhua Shao, Xianlong Liu
  • Patent number: 11509475
    Abstract: A method for a system includes forming within an app running upon a user smart-device, an ephemeral ID having data associated with a server and anonymous data, outputting the ephemeral ID to a first receiver associated with a first computer and to a second receiver associated with a second computer system separate from the first, receiving from the first receiver an identifier and a nonce, providing the identifier and the nonce to the server, receiving from the server a token associated with the first computer system authorizing access to the first computer system but not the second computer system by the user smart-device, storing the token for facilitated authentication of the user smart-device, and providing the token to the first receiver.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 22, 2022
    Assignee: Proxy, Inc.
    Inventors: Denis Mars, Simon Ratner
  • Patent number: 11500581
    Abstract: The present disclosure generally relates to efficient transfer layer packet (TLP) fragmentation in a data storage device. For an unaligned read from host flow, an amount of data sufficient to be aligned is transferred to the memory device from the host while the remainder of the data is stored in cache of the data storage device to be delivered to memory device at a later time. For an unaligned write to host flow, the unaligned data is written to cache and at a later time the cache will be flushed to the host device. In both cases, while the total data would be unaligned, a portion of the data is placed in cache so that the data not placed in cache is aligned. The data in cache is delivered at a later point in time.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: November 15, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Amir Segev
  • Patent number: 11494501
    Abstract: A policy-based printing system is implemented to allow access to a private domain to print using a public domain. The private domain includes private servers that store documents. The public domain includes servers and a printing device. A public policy server uses a domain list and a protocol connection with a private authentication server to validate a user and identify which private domain to access. The public policy server receives requests from the printing device to process a print job of a document in the private domain. A mobile device is used to coordinate the retrieval and printing of the document using an application. A kiosk may be used to send the document to the printing device from the mobile device.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: November 8, 2022
    Assignee: KYOCERA DOCUMENT SOLUTIONS, INC.
    Inventors: Jin Liang, Tai Yu Chen, Michael Ong Martin
  • Patent number: 11494110
    Abstract: Scalable segment cleaning for log-structured file systems (LFSs) includes determining counts of segment cleaners and virtual nodes, with each virtual node being associated with a plurality of objects. Each virtual node is assigned to a selected segment cleaner. Based at least on the assignments, performing, for each virtual node, segment cleaning of the objects by the assigned segment cleaner. A portion, less than all, of the virtual nodes are reassigned to a newly selected segment cleaner based on a change of the count of the segment cleaners and/or a change of the count of the virtual nodes. Based at least on the reassignments, segment cleaning of the objects is performed, for each reassigned virtual node, by the reassigned segment cleaner. In some examples, the objects comprise virtual machine disks (VMDKs) and the segment cleaning uses a segment usage table (SUT) to track segment usage and identify segment cleaning candidates.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: November 8, 2022
    Assignee: VMware, Inc.
    Inventors: Wenguang Wang, Junlong Gao, Vamsi Gunturu
  • Patent number: 11455402
    Abstract: Apparatus and method for selective overwrite protection of data stored in a non-volatile memory (NVM) with fine precision. In some embodiments, a write command is received from a host device to write one or more blocks of data having associated logical addresses to the NVM. A read operation is performed in response to the write command to read a tag value associated with each block. The write command is disallowed in response to the tag value indicating a protected version of the block having the associated logical address is already stored at the selected location. The tag value may be a key version value indicative of a version of an encryption key used to encrypt user data in the data block and whether the block is write-protected.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: September 27, 2022
    Inventor: Jon D. Trantham
  • Patent number: 11455617
    Abstract: NFC terminal devices and corresponding integrated circuit cards (ICCs) use NFC Type 4 tags as a protocol interface for complex or encrypted communication protocols that are not natively supported by the NFC terminal devices. A smartphone acting as an NFC terminal may block applications and/or protocols other than NFC data exchange formatted (NDEF) messages. An ICC applet supporting an advanced function uses designated memory locations for the transfer of commands normally supported at an application level. Both the terminal side and the ICC applet may check the designated memory locations for updated data in the absence of protocol-level message controls.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: September 27, 2022
    Assignee: VISA INTERNATIONAL SERVICE ASSOCIATION
    Inventors: Mustafa Top, Kiushan Pirzadeh
  • Patent number: 11442893
    Abstract: Database-aware snapshotting is disclosed. It is determined that a first snapshot of a database having a plurality of shards should be taken. Each shard has a corresponding snapshot sidecar container of a plurality of snapshot sidecar containers. A consensus state among the plurality of snapshot sidecar containers that the first snapshot should be taken is determined. A snapshot controller is directed to take the first snapshot of the database, the first snapshot generating a shard volume snapshot for each shard of a plurality of shards. Subsequent to the snapshot controller taking the first snapshot of the database, each snapshot sidecar container is informed to allow activity on the corresponding shard.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 13, 2022
    Assignee: Red Hat, Inc.
    Inventors: Huamin Chen, Tomas Smetana
  • Patent number: 11438349
    Abstract: Disclosed herein are systems and method for protecting an endpoint device from malware. In one aspect, an exemplary method comprises performing, by a light analysis tool of the endpoint, a light static analysis of a sample, terminating the process and notifying the user when the process is malware, performing light dynamic analysis when the process is not malware based on the light static analysis, when the process is clean based on the light dynamic analysis, enabling the process to execute, when the process is malware, terminating the process and notifying the user, and when the process is suspicious pattern, suspending the process, setting a level of trust, sending the sample to a sandbox, terminating the process and notifying the user when the process is a malware based on received final verdict, enabling the process to resume executing when the process is determined as being clean based on the final verdict.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: September 6, 2022
    Assignee: Acronis International GmbH
    Inventors: Alexey Kostyushko, Vladimir Strogov, Serguei Beloussov, Stanislav Protasov, Anastasia Pereberina, Nikolay Grebennikov
  • Patent number: 11399120
    Abstract: Provided is a compatibility promotion method, storage medium, and system for HDMI. The method comprises steps of reading EDID to be analyzed of a display device; defining a situation 1 as the existence of non-standard timing of EDID to be analyzed; defining a situation 2 as the bandwidth of the resolution supported by the display is greater than a maximum bandwidth of a HDMI intermediate device; if the EDID to be analyzed meets the situation 1, after modifying the timing of the EDID to be analyzed into an HDMI standard timing, and then forwarding the modified EDID same to an input source device; if the EDID to be analyzed meets the situation 2, modifying a color depth sampling format and a color format of a resolution greater than a maximum bandwidth of the HDMI intermediate device in the EDID to be analyzed to be within a supported bandwidth range.
    Type: Grant
    Filed: March 6, 2022
    Date of Patent: July 26, 2022
    Inventors: Shijie Hong, Yuhua Gu, Hongjian Zhou
  • Patent number: 11392306
    Abstract: Memory of a storage system is made available (i.e., exposed) for use as host memory of a host, for example, as an extension of the main memory of the host. The host may be directly connected to an internal fabric of the data storage system. Portions of the storage system memory (SSM) may be allocated for use as host memory, and this may be communicated to the host system. The host OS and applications executing thereon then may make use of the SSM as if it were memory of the host system, for example, as second-tier persistent memory. The amount of SSM made available may be dynamically increased and decreased. The SSM may be accessed by the host system as memory; i.e., in accordance with memory-based instructions, for example, using remote direct memory access instructions. The SSM may be write protected using mirroring, vaulting and other techniques.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: July 19, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jon I. Krasner, Arieh Don, Yaron Dar
  • Patent number: 11374773
    Abstract: One of the various aspects of the invention is related to suggesting various techniques for improving the tamper-resistibility of hardware. The tamper-resistant hardware may be advantageously used in a transaction system that provides the off-line transaction protocol. Amongst these techniques for improving the tamper-resistibility are trusted bootstrapping by means of secure software entity modules, a new use of hardware providing a Physical Unclonable Function, and the use of a configuration fingerprint of a FPGA used within the tamper-resistant hardware.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 28, 2022
    Inventor: Heinz Kreft
  • Patent number: 11366783
    Abstract: An integrated circuit includes a plurality of configurable units, each configurable unit having two or more corresponding sections. The plurality of configurable units is arranged in a serial arrangement to form a chain of sections of the configurable units. A data bus is connected to the plurality of configurable units which communicates data at a clock rate. The chain of sections is to receive and write a series of tensors at the clock rate at a first end section of the chain of sections, and sequentially propagate the series of tensors through individual sections within the chain of sections at the clock rate. The chain of sections is to output the series of tensors at a second end section of the chain of sections. The chain of sections is to also output the series of tensors at an intermediate section of the chain of sections.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: June 21, 2022
    Assignee: SambaNova Systems, Inc.
    Inventors: Raghu Prabhakar, Nathan Francis Sheeley, Amitabh Menon, Sitanshu Gupta, Sumti Jairath, Matheen Musaddiq
  • Patent number: 11281512
    Abstract: A storage device having an improved operation speed includes a memory device and a memory controller for controlling the memory device. The memory controller includes: a Device-To-Host (DTH) information generator configured to generate DTH information to be transferred to a host, a host memory accessor configured to provide the host with the DTH information received from the DTH information generator and an interrupt signal generator configured to output, to the host, an interrupt signal notifying that the DTH information has been provided to the host, based on a request from the host memory accessor.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: March 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Kwang Ho Choi, Joong Yong Jeon
  • Patent number: 11269629
    Abstract: Many signal processing, machine learning and scientific computing applications require a large number of multiply-accumulate (MAC) operations. This type of operation is demanding in both computation and memory. Process in memory has been proposed as a new technique that computes directly on a large array of data in place, to eliminate expensive data movement overhead. To enable parallel multi-bit MAC operations, both width- and level-modulating memory word lines are applied. To improve performance and provide tolerance against process-voltage-temperature variations, a delay-locked loop is used to generate fine unit pulses for driving memory word lines and a dual-ramp Single-slope ADC is used to convert bit line outputs. The concept is prototyped in a 180 nm CMOS test chip made of four 320×64 compute-SRAMs, each supporting 128× parallel 5 b×5 b MACs with 32 5 b output ADCs and consuming 16.6 mW at 200 MHz.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 8, 2022
    Assignee: The Regents of the University of Michigan
    Inventors: Zhengya Zhang, Thomas Chen, Jacob Christopher Botimer, Shiming Song
  • Patent number: 11269308
    Abstract: Method for creating and managing programmable logic controller (PLC) solution comprises connecting existing PLC solution to a cloud network, and connecting from a user device to a virtualization server. A graphical representation of a pin layout of a PLC is displayed on a GUI on the user device. An input comprising selection of a first pin, a sensor or an actuator configured to be coupled with the PLC via the first pin, and a parameter for the operation of the selected sensor or the selected actuator is received on the GUI. The received input is sent from the user device to the virtualization server. An executable PLC application for execution on the PLC is received on the user device. The PLC application is configured to operate and/or monitor the PLC according to the received input. The PLC application is sent to the PLC for being deployed on the PLC.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: March 8, 2022
    Assignee: Ciambella Ltd.
    Inventor: Trisala Chandaria
  • Patent number: 11263165
    Abstract: Apparatuses relating to periodic Universal Serial Bus (USB) transaction scheduling at fractional bus intervals are described. In one embodiment, an apparatus includes a receptacle to receive a plug of a first device and a second device; a transceiver circuit coupled to the receptacle; and a controller circuit to: switch between a first mode for a first class of data transfers and a second mode for a second class of data transfers, wherein the first class preempts the second class of data transfers, schedule a data transfer with the transceiver circuit for a first endpoint of the first device at a first service interval of a bus interval when in the first mode, and schedule a data transfer with the transceiver circuit for a second, different endpoint of the second device at a second service interval that is smaller than the first service interval when in the first mode.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Karthi R. Vadivelu, Abdul R. Ismail, Nausheen Ansari
  • Patent number: 11232037
    Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 25, 2022
    Assignee: Seagate Technology LLC
    Inventors: Nitin Satishchandra Kabra, Sidheshkumar Ramanlal Patel, Sneha Kishor Wagh
  • Patent number: 11216383
    Abstract: An electronic system includes a host device and a storage device including a first memory device of a volatile type and a second memory device of a nonvolatile type. The first memory device is accessed by the host device through a memory-mapped input-output interface and the second memory device is accessed by the host device through a block accessible interface. The storage device provides a virtual memory region to the host device such that a host-dedicated memory region having a first size included in the first memory device is mapped to the virtual memory region having a second size larger than the first size.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Duck-Ho Bae, Dong-Uk Kim, Hyung-Woo Ryu, Kwang-Hyun La, Joo-Young Hwang, You-Ra Choi
  • Patent number: 11184824
    Abstract: Systems and methods are provided for upgrading wireless network devices, such as access points (APs). When a first AP needs an upgrade, a network controller of the first AP may identify and select a neighbor AP. The radio(s) of the neighbor AP can be split into multiple logical radios, at least one of which includes a backup virtual AP (VAP). The backup VAP can support client devices originally supported by the first AP, allowing those client devices to roam to the neighbor AP while the first AP is upgrading, and without needing to re-associate with the neighbor AP. From the client device perspective, it appears as though they are still being supported by the first AP. Upon upgrading the first AP, the client devices can roam back to the first AP (without needing to re-associate with the first AP). No downtime is experienced, and no RF holes are generated.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 23, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Xuguang Jia, Guangzhi Ran, Qiang Zhou
  • Patent number: 11169828
    Abstract: An electronic control unit includes a first non-volatile memory configured such that a control program is written thereto; a second non-volatile memory configured such that an identifier is written thereto; and a processor. The identifier is for verifying whether the control program is correct. The processor chooses either an identifier contained in advance in the control program or an identifier written in the second non-volatile memory, depending on how and/or whether the identifier is written in the second non-volatile memory. The processor verifies whether the control program is correct based on the chosen identifier.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: November 9, 2021
    Assignee: Hitachi Astemo, Ltd.
    Inventor: Hisao Ito