Abstract: A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.

Abstract: Storage space is reclaimed by cleaning and compacting data objects where data objects are stored by immutable storage. A storage area of which space needs to be reclaimed is identified. Active and stale data objects stored in a storage area are identified, and only active data objects are transferred to a shadow storage area from the storage area when recovering storage space. I/O operations can be fulfilled from the storage area and the shadow storage area. Compaction requests and I/O requests are throttled according to QOS parameters. Recovery of storage space does not cause a failure to meet performance requirements for any storage volume.

Abstract: An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.

Abstract: An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.

Abstract: An electronic device including a communication interface and a command buffer coupled to the communication interface. The communication interface is configured to receive commands from a plurality of initiator devices, and the command buffer is configured to store the commands. The electronic device further includes a command buffer management module coupled to the command buffer. The command buffer management module is configured to generate a message indicating a remaining allowed storage size associated with the command buffer. The communication interface is further configured to enable communication of the message to a particular initiator device of the plurality of initiator devices. The message may enable the particular initiator device to hold off on sending one or more other commands to the command buffer if the remaining allowed storage size fails to satisfy a threshold storage size.

Abstract: A system, method and computer program product for anonymizing data. Datasets anonymized according to the method have a relational part having multiple tables of relational data, and a sequential part having tables of time-ordered data. The sequential part may include data representing a “sequences-of-sequences”. A “sequence-of-sequences” is a sequence which, itself, consists of a number of sequences. Each of these kinds of data may be anonymized using k-anonymization techniques and offers privacy protection to individuals or entities from attackers whose knowledge spans the two (or more) kinds of attribute data.

Abstract: Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.

Abstract: Method and apparatus to efficiently organize data in caches by storing/accessing data of varying sizes in cache lines. A value may be assigned to a field indicating the size of usable data stored in a cache line. If the field indicating the size of the usable data in the cache line indicates a size less than the maximum storage size, a value may be assigned to a field in the cache line indicating which subset of the data in the field to store data is usable data. A cache request may determine whether the size of the usable data in a cache line is equal to the maximum data storage size. If the size of the usable data in the cache line is equal to the maximum data storage size the entire stored data in the cache line may be returned.

Abstract: An invention is provided for filtering cached input/output (I/O) data. The invention includes receiving a current I/O transfer. Embodiments of the present invention evaluate whether to filter ongoing data streams once the data stream reaches are particular size threshold. The current I/O transfer is part of an ongoing sequential data stream and the total data transferred as part of the ongoing sequential data stream is greater than the predetermined threshold. The transfer rate for the ongoing sequential data stream then is calculated and a determination is made as to whether the transfer rate is greater than a throughput associated with a target storage device. The current I/O transfer is cached when the transfer rate is greater than the throughput associated with a target storage device, or is not cached when the transfer rate is not greater than the throughput associated with a target storage device.

Abstract: A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress.

Abstract: In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.

Abstract: The present disclosure includes systems and techniques relating to input/output (I/O) command aggregation for Small Computer System Interface (SCSI) enabled devices.

Abstract: A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical device. The method comprises, at a first control element receiving a data packet transmitted by one of said one or more computing devices, and determining whether said data packet comprises a command including a first logical identifier identifying one of said resources. If it is determined that said data packet comprises a command including a first logical identifier a second logical identifier is obtained, the second logical identifier being associated with said first logical identifier and identifying said one of said resources. A request including said second logical identifier is transmitted to a second control element, the second control element being arranged to identify a physical device associated with said second logical identifier and to forward said request to the identified physical device.

Abstract: An invention is provided for filtering cached input/output (I/O) data. The invention includes receiving a current I/O transfer. Embodiments of the present invention evaluate whether to filter ongoing data streams once the data stream reaches are particular size threshold. The current I/O transfer is part of an ongoing sequential data stream and the total data transferred as part of the ongoing sequential data stream is greater than the predetermined threshold. The transfer rate for the ongoing sequential data stream then is calculated and a determination is made as to whether the transfer rate is greater than a throughput associated with a target storage device. The current I/O transfer is cached when the transfer rate is greater than the throughput associated with a target storage device, or is not cached when the transfer rate is not greater than the throughput associated with a target storage device.

Abstract: A method is disclosed for compressing a sequence of initial digital values into a compressed sequence of compressed values, intending to restore these values into a decompressed sequence of decompressed values. For a first initial value of the sequence, the compressed value of the first initial value is equal to the first initial value and the decompressed value of the compressed value of the first initial value is equal to the first initial value.

Abstract: The present disclosure includes systems and techniques relating to effectively increasing a command queue length for accessing storage, such as by increasing the Queuing Depth (Q-Depth) of Native Command Queuing (NCQ) Commands. In some implementations, a method can comprise receiving a first command to access a first memory location of a storage device; receiving a second command to access a second memory location of a storage device; constructing a consolidated command including a memory address and a data transfer count associated with each of the first command and the second command; constructing an information command having consolidation information about the consolidated command; and communicating the information command and the consolidated command to the storage device for processing by the storage device.

Abstract: An information-processing method performed in an information-processing apparatus, the information-processing apparatus performing wireless communication with a first apparatus and wire communication with a second apparatus, the information-processing method including the steps of: transmitting an interrupt signal to the second apparatus by using the wire communication when data is received from the first apparatus; receiving, by using the wire communication, a clock signal from the second apparatus which receives the interrupt signal; and transmitting and receiving, by using the wire communication, data between the information-processing apparatus and the second apparatus.

Abstract: A print control apparatus includes a print management unit, a storage unit, a print control unit, and a checking unit. The print management unit accepts print instructions for output data, and records an order in which the print instructions have been accepted. The storage unit temporarily stores the output data related to the print instructions accepted by the print management unit. The print control unit sequentially acquires the output data from the storage unit, transmits the output data to an image forming apparatus, and records an order in which the output data have been transmitted. The checking unit compares and checks the order in which the print instructions have been accepted, which has been recorded by the print management unit, and the order in which the output data have been transmitted, which has been recorded by the print control unit.

Abstract: A storage device includes a processing state value calculator that calculates a first processing state value representing a state of data forwarding from the storage device via the connection lines; a notifier that notifies the first processing state value to the second storage device; a receiver that receives a second processing state value representing a state of data forwarding from another storage device (second storage device) via the communication lines and calculated in the second storage device; a multiplicity calculator that calculates, using the first processing state value and the second processing state value, a multiplicity representing the number of data forwarding processes which the storage device is able to simultaneously carry out on the communication lines; and a forwarding controller that forwards data via the communication lines within the calculated multiplicity, so that data may be optimally forwarded via the connection lines.

Abstract: An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link from the controller to each module. Each communication link includes a data out line, a data in line and a clock line, where each clock line is derived from one clock source.

Abstract: A control panel and a serial port communication arbiter for a touch screen with a camera are provided. A serial port communication method for a touch screen with a camera includes: transmitting a channel request message to the serial port communication arbiter, the channel request message being used for requesting for occupying the channel between the control panel of the touch screen with camera and an upper computer; receiving a channel response message transmitted by the serial port communication arbiter, the channel response message containing a state of the channel; transmitting data to the upper computer over the channel if the state of the channel is idle. It can save production cost of the control panel, improve system performance, and facilitate maintenance of the control panel.

Abstract: One embodiment relates to an integrated circuit configured to communicate a low-latency word category over a multi-lane link. A transmitter controller is configured to transmit words belonging to the low-latency word category only over a designated lane of the multi-lane link and to transmit words belonging to non-low-latency word categories over any available lane of the multi-lane link. A receiver controller may be configured to determine a word category of a word received over the designated lane and, if the word category is determined to be the low-latency word category, then read the word from the designated lane before lane-to-lane deskew is completed. Other embodiments, aspects, and features of the invention are also disclosed.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: An apparatus includes first, second, and spare ports, where first data having a data length less than a predetermined value is transmitted from the first port and second data having a data length not less than the predetermined value is transmitted from the second port. The apparatus obtains a first determination result indicating whether input data is the first data or the second data and a second determination result indicating whether a transmission rate of each of the first and second ports is equal to or greater than a threshold. The apparatus sorts the input data to one of the first, second, and spare ports, based on the first and second determination results. The apparatus fragments the second data and transmit the fragmented second data to the spare port when both the first data and the second data are sorted to the spare port.

Abstract: Controlling I/O operations with a storage device includes establishing a quota that corresponds to a maximum amount of data to store on the storage device in a given amount of time, determining if processing an I/O operation would cause the quota to be exceeded, and performing the I/O operation if the quota is not exceeded. The quota may be provided in I/O operations per second or as I/O throughput. Controlling I/O operations with a storage device may also include accumulating credit in response to a rate of I/O operations being less than the quota and performing I/O operations when the quota is exceeded in response to the credit being greater than zero. The credit may be decreased if an I/O operation is performed when the quota is exceeded.

Abstract: In a network protocol processing system in which variables of each of TCP transmission processing and TCP reception processing depend on each other, asynchronous parallel processing is realized between a transmission processing block and a reception processing block for updated protocol processing. Specifically, the system includes a high priority queue for transferring control data to be processed with high priority, a low priority queue for control data other than the above control data, and priority control means for distributing the control data to two kinds of queues. When a request for session establishment and the session disconnection of a new TCP session is issued from an application during transmission of TCP data, data related with the session establishment and the session disconnection is notified preferentially through the high priority queue, and other control data is transferred through the low priority queue.

Abstract: The disclosed embodiments relate to a system for controlling accesses to one or more memory devices. This system includes one or more write queues configured to store entries for write requests, wherein a given entry for a write request includes an address and write data to be written to the address. The system also includes a search mechanism configured to receive a read request which includes an address, and to search the one or more write queues for an entry with a matching address. If a matching address is found in an entry in a write queue, the search mechanism is configured to retrieve the write data from the entry and to cancel the associated write request, whereby the read request can be satisfied without accessing the one or more memory devices.

Abstract: By referring to a receiving connection information table stored in a memory, a receiving assignment CPU assigns packets to parallel processing CPUs in such a manner that the packets received from the same connection are subjected to a receiving process by a corresponding parallel processing CPU. Each parallel processing CPU identifies the input QoS of a packet and notifies a QoS processing CPU, corresponding to that identified input QoS, of the packet. Each QoS processing CPU is arranged so that it corresponds to a QoS processing queue group in the memory and performs a QoS process on this QoS processing queue group.

Abstract: An input/output module for use in an industrial control system and connectable to a programmable logic controller (PLC), the input/output module having an interface configured for an electrical connection to the PLC, a plurality of pins configured for connection to one of a plurality of peripherals, an application specific integrated circuit (ASIC) disposed in the I/O module and electrically coupled to a system controller, the ASIC having a plurality of connection paths, each path being configured for a function, and a switch block configured to reassign a signal from a first connection path of the plurality of connection paths to a second connection path of the plurality of connection paths.

Abstract: When a data request signal is inactivated while a DMA controller is executing DMA data transfer in a burst transfer mode, an address at this time is held and a remaining number of transfer times is counted. After the DMA data transfer in the burst transfer mode is finished, the address and the remaining number of transfer times are re-set in the DMA controller and then the DMA data transfer is executed. This makes it possible to re-transfer data remaining at the timing when the data request signal is inactivated, and the DMA data transfer using the burst transfer mode is executed to or from a module requesting the DMA data transfer by using level of the data request signal.

Abstract: A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit.

Abstract: A channel device equipped with a data buffer unit storing data transferred between a storage device and an input-output device, a transfer controller transferring continuous data between the storage device and the data buffer unit using channel startup information. The storage device transfer controller transfers first data between the storage device and the data buffer unit using first transfer information stored in the address list and transfers the second data using second transfer information and total transfer amount information stored in the address list after the first data is transferred and an input-output device transfer controller transfers the continuous data between the data buffer unit and the input-output device.

Abstract: A data transfer method is provided which includes: sending a stream of data elements from a source to a sink (controlled by a common clock); simultaneously with the sending of the data element stream, sending a first binary signal to the sink, where the first binary signal is low if a data element is to be ignored by the sink, and is otherwise high; simultaneously with the sending of data element stream, sending a second binary signal from the sink to the source, where the second binary signal is low if the data element is not accepted by the sink, and is otherwise high; and simultaneously with the sending of the data element stream, sending a third binary signal to the sink, where the third binary signal marks a beginning and an end of a logical group of data elements within the data element stream.

Abstract: A method for transmitting touch panel data is provided. The method is adapted for transmitting coordinate data of at least a touch point being touched on the touch panel and includes the following procedures. The at least coordinate data is compressed. A serial data transmission interface command and a serial data transmission interface client address are appended in front of the compressed at least coordinate data, such that the compressed at least coordinate data is encapsulated into a serial transmission data packet. In addition, the serial transmission data packet is transmitted through a serial data transmission channel.

Abstract: A data transfer apparatus includes a virtual channel unit configured to time share a serial bus for a first virtual channel and a second virtual channel and include a buffering control unit configured to receive data via the first virtual channel and the second virtual channel, first and second receive buffers being configured to store the data received via the first virtual channel and the second virtual channel, respectively; and a switching unit configured to control storing the data received via the first virtual channel in the second receive buffer when the buffering control unit receives the data from another data transfer apparatus which is configured to use only the first virtual channel and the capacity of the first receive buffer is smaller than that of the second receive buffer.

Abstract: A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.

Abstract: A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.

Abstract: There are provided a waveform observing apparatus and the system thereof in which, when a removable storage medium is inserted into the waveform observing apparatus to capture a copy of measured data, a difference copy is made while including the latest measured data collected by the waveform observing apparatus at the time, sixteenth and seventeenth measured data temporarily stored in a buffer memory are filed and stored in the state of being housed in a fourth measured data file, into a body memory. Copies of a third measured data file including part of the difference copy and a new fourth measured data file are written into the USB memory. When the USB memory is inserted into a personal computer, a hard disk of the personal computer comes into a state where its third measured data file is overwritten and stored and the fourth measured data file is newly stored.

Abstract: Embodiments described in the present disclosure relate to a method for initializing registers of peripherals of a microcontroller, including acts of: accessing initialization data in a non-volatile memory connected by a main bus to a processing unit of the microcontroller and to the peripherals, activating a peripheral including registers to be initialized, and transferring the data read into the registers of the activated peripheral, the initialization data being accessed in the memory by an initialization circuit distinct from the processing unit, the initialization data accessed being sent to the peripherals by an initialization bus distinct from the main bus.

Abstract: A data transfer device includes a storage controller that stores received response data in a buffer with respect to each piece of identification information included in the response data when receiving the response data from a first device, the response data being transferred from the first device in response to a transfer request transferred from a second device, a counting unit that counts a number of pieces of the response data stored in the buffer by the storage controller with respect to each piece of the identification information, and a determination unit that determines whether the number counted by the counting unit reaches a specified value preliminarily set with respect to each piece of the identification information.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: A memory block reclaiming judging apparatus and a memory block managing system are disclosed in the present invention. The memory block reclaiming judging apparatus comprises a peripheral information accessing unit, a data packet information recording unit, a data calculating unit, and a comparing and judging unit, wherein the data calculating unit is configured to calculate remaining scheduling times of a data packet-and write the remaining scheduling times of the data packet into the data packet information recording unit, and meanwhile set a flag for indicating acquirement of information of the required scheduling times as valid; the comparing and judging unit is configured to generate a memory block reclaiming instruction, reset the remaining scheduling times of the data packet in the data packet information recording unit to an initial value, and set the flag for indicating acquirement of information of the required scheduling times as invalid.

Abstract: A signal processor includes a processor that counts the number of input data pieces or a size of each of the input data pieces; a first memory that stores a result of the counting by the processor; and a second memory that records whether the result of the counting exceeds a capacity of the first memory.

Abstract: Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.

Abstract: A system improves bandwidth used by a data stream. The system receives data from the data stream and partitions the data into bursts. At least one of the bursts includes one or more idles. The system selectively removes the idles from the at least one burst and transmits the bursts, including the at least one burst.

Abstract: Method and system for a data transfer operation to a device memory is provided. The method includes setting a counter to an initial value; detecting the data transfer operation; determining if information is written to a first memory location of the device memory; counting in a first direction when a total transfer size (N) is written to the first memory location of the device memory; and counting in a second direction when data is written in memory locations other than the first memory location of the device memory, wherein the data transfer operation is complete when a counter value transitions from a non-initial value to an initial value.

Abstract: A pulsed electrical remote control interface for an equipment item including a plurality of functions to be controlled includes at least a first command input associated with a first command line (TC-Type, TC-Type-plus, TC-Type-minus) for selecting at least one function (RF ON, RF OFF, ALC ON, ALC OFF, FCA UP, FCA DOWN, GCA UP, GCA DOWN, SCA UP, SCA DOWN, INHIBIT) to be performed from the plurality of functions and at least one second command input associated with a second command line (EXE, EXE-UP-ON, EXE-DOWN-OFF) for executing the selected function, each command input being associated with an outbound pulsed command line and a return line, the return line possibly being shared with a number of outbound lines. Applicable to the control of any kind of equipment that includes a large number of functions and requires a large number of pulsed command signals, notably in the field of satellite communication systems.

Abstract: A physical coding sublayer includes a first channel configured to receive a first encoded data stream from a physical media attachment layer and to provide a first decoded data stream to a media access layer. The first channel includes a first circuit configured to detect synchronization headers in the first encoded data stream received from the physical media attachment layer, a decoding circuit configured to decode the encoded data stream and to adjust a width of the received data from a first width to a second width based on a signal identifying the synchronization headers received from the first circuit, and a first single configured to compensate for clock differences between the physical media attachment layer and the media access layer to which the first buffer provides the first decoded data stream.

Abstract: A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical device. The method comprises, at a first control element receiving a data packet transmitted by one of said one or more computing devices, and determining whether said data packet comprises a command including a first logical identifier identifying one of said resources. If it is determined that said data packet comprises a command including a first logical identifier a second logical identifier is obtained, the second logical identifier being associated with said first logical identifier and identifying said one of said resources. A request including said second logical identifier is transmitted to a second control element, the second control element being arranged to identify a physical device associated with said second logical identifier and to forward said request to the identified physical device.

Abstract: A data transmission method is provided, which includes: obtaining a current queue length of a queue corresponding to an output port; when the current queue length meets a back-pressure requirement, determining a back-pressure priority corresponding to the current queue length according to the current queue length and a mapping relationship between a preset queue length and the back-pressure priority, and generating back-pressure information, where the back-pressure information inhibits a line card from sending data with a data priority less than or equal to the back-pressure priority to the output port; and sending the back-pressure information to a line card.