Abstract: A data processing system and method are provided. The data processing system includes: a data acquisition unit, configured to acquire a plurality pieces of data related to a target object; and a data processing unit, configured to receive the plurality pieces of data and set a plurality of adjacent regions in a two-dimensional spatial representation of the plurality pieces of data according to a tolerable compression error. The plurality of regions include an adjacent first region and second region, respectively covering a plurality pieces of data. The data processing unit is configured to forwardly expand the second region to obtain the expanded second region overlapping the first region, calculate a compression error of data covered by the expanded second region, reset the first region and compress the data covered by the reset first region. The data processing system can reduce or minimize the data compression error.

Abstract: Data transfer, synchronizing applications, and low latency networks are disclosed. An example method includes maintaining a first buffer in a first computing device, the first buffer to receive discrete units of data from a second computing device; maintaining a second buffer in the first computing device, the second buffer to store size data identifying a size of respective ones of the discrete units of data received from the second computing device; and reading from the first buffer according to a first value of a first pointer and a corresponding one of the sizes stored in the second buffer.

Abstract: Techniques for polling an input/output (I/O) device are described herein. The techniques include polling a device for data from the I/O device, and receiving the data from the I/O device at the host device as a result of the polling. The techniques include determining whether the data received is the same as data received at a previous polling of the I/O device. Upon determining the data received is the same, the techniques include decreasing the polling rate if the data is the same, and if it is not the same. Upon determining the data is not the same, the techniques include increasing the polling rate if the data is not the same.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.

Abstract: A communication link between a host device and a client device can be suspended based on a suspend request or notification provided by the client device. The suspend request can be transmitted by a client device to a host device if the client device determines that suspension is appropriate, and can be sent in response to receiving a polling request from the host device. After receiving a suspend request, the host device can initiate an operation to suspend the communication link between the devices.

Abstract: An image processing apparatus includes an image forming unit, power supplier, power controller, memory, signal transmission unit and transmission timer. The image forming unit forms an image based on image data from a plurality of host devices. The power supplier supplies power to a power system including the image forming unit. The power controller controls the power from the power supplier to the power system. The memory stores a usage amount of each host device. The signal transmission unit transmits a response request to a host device having at least a predetermined usage amount. The transmission timer counts a first time period from a transmission of the response request. The power controller halts the power from the power supplier to the power system when determining, based on the first time period, that a reply to the response request is not transmitted from the specific host device for a predetermined period.

Abstract: A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can change the execution state of the first thread. Reservation circuitry of the processing device that was executing the first thread monitors the reservation. In the event that the reservation cleared, such as by the second thread modifying data at the predetermined memory address, the first thread is reinstated to its prior execution state. By using a hardware reservation mechanism to monitor for clearing of a set reservation, repeated memory accesses to the memory address by the first thread can be minimized or avoided while in the polling loop and other threads can be allowed to execute at the processing device with reduced interference from the waiting thread.

Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

Abstract: In some embodiments of the present invention, host systems and/or devices are made to be capable of employing asynchronous or synchronous modes. For example, for storage devices capable of finishing I/O requests in a sufficiently small amount of time, e.g., a few microseconds, host system software may perform the storage I/O request synchronously by polling for a completion.

Abstract: A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage device in communication with the storage controller, where that data storage device reservation is held by a first communication path group comprising a first plurality of communication paths configured in the communication link. If the method detects a failed communication path configured in the first communication path group, the method configures a second communication path group by removing the failed communication path from the first communication path group, wherein the second communication path group maintains the data storage device reservation.

Abstract: In a disclosed example of a method, a requested value of a target register may be specified as a precondition to performing a requested read or write operation. The requested read or write operation may be generated by a requesting device, such as a processor, and sent over a bus to a peripheral device containing the target register. The target register may be polled internally to the peripheral device without generating additional bus traffic between the requesting device and the peripheral device. A ring topology may be used to internally poll the target register and to perform the requested read or write operation when the polled value of the target register equals the requested value.

Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.

Abstract: In some embodiments of the present invention, host systems and/or devices are made to be capable of employing asynchronous or synchronous modes. For example, for storage devices capable of finishing I/O requests in a sufficiently small amount of time, e.g., a few microseconds, host system software may perform the storage I/O request synchronously by polling for a completion.

Abstract: A network device may include a line interface to receive and transmit data units, a memory including instructions associated with a user space and a kernel space that are executable by a processor, the user space including a first-in-first-out (FIFO) region for storing the data units and corresponding metadata, where the kernel space writes the data unit and the corresponding metadata to the FIFO region, the metadata including a next pointer that identifies a memory address for storing the next data unit in the FIFO region, a user space process determines whether to transmit or drop the data unit, the user space process being a single process, and the user space transmits the data unit from the FIFO region without involving the kernel space when the user space process issues a command.

Abstract: A software thread is dispatched for causing the system to poll a device for determining whether a condition has occurred. Subsequently, the software thread is undispatched and, in response thereto, an interrupt is enabled on the device, so that the device is enabled to generate the interrupt in response to an occurrence of the condition, and so that the system ceases polling the device for determining whether the condition has occurred. Eventually, the software thread is redispatched and, in response thereto, the interrupt is disabled on the device, so that the system resumes polling the device for determining whether the condition has occurred.

Abstract: A software thread is dispatched for causing the system to poll a device for determining whether a condition has occurred. Subsequently, the software thread is undispatched and, in response thereto, an interrupt is enabled on the device, so that the device is enabled to generate the interrupt in response to an occurrence of the condition, and so that the system ceases polling the device for determining whether the condition has occurred. Eventually, the software thread is redispatched and, in response thereto, the interrupt is disabled on the device, so that the system resumes polling the device for determining whether the condition has occurred.

Abstract: The present invention may be related to a bridge for communications between a first computing device and a second computing device in a data communication system. The bridge may include a first interface, a second interface and a control module. The first interface may be adapted to couple with the first computing device. The second interface may be adapted to couple with the second computing device. The control module may be configured to process a file input/output (I/O) command from the first computing device so as to allow the first computing device to have access to at least one of data or resource of the second computing device via the first and second interfaces. Moreover, the control module may further include a parser, a decoder and a micro processor. The parser may be configured to identify whether the file I/O command includes an encoded controller command and retrieve the encoded controller command from the file I/O command if the file I/O command includes an encoded controller command.

Abstract: An apparatus and a method for processing high speed data using hybrid Direct Memory Access (DMA) are provided. The method includes determining a size of data to be transmitted, determining a memory access method of the data by comparing the determined size of the data with a first threshold, and determining an I/O bus access method of the data by comparing the determined size of the data with a second threshold.

Abstract: According to one example of the present invention, there is provided an electronic device comprising one or more configurable features. The device comprises an interface for receiving configuration data for configuring a feature of the electronic device and a data store or memory for storing feature configuration data associated with a configurable feature. The device further comprises logic for determining whether the received configuration data is compatible with configuration data stored in the data store. If the logic determines that the received configuration data is compatible the device is configured in accordance with the received configuration data.

Abstract: A method and system suitable for grouping a plurality of multifunction devices (MFDs), the system including a storage station for storing information gathered from the plurality of MFDs by selectively polling the plurality of MFDs; wherein the information is selectively processed based on static performance data and dynamic performance data relating to the plurality of MFDs.

Abstract: A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.

Abstract: In some embodiments, an electronic apparatus comprises at least one memory module, and a universal serial bus (USB) host controller coupled to the memory, wherein the USB host controller implements hardware assisted idleness endpoint detection.

Abstract: Herein described are at least a system and a method of reducing or decreasing the rate of interrupts transmitted by a device to a microprocessor. In a representative embodiment, the device comprises a universal asynchronous receiver/transmitter. In a representative embodiment, the rate of interrupts is reduced by receiving and using a first signal as an input to a first counter. The first counter outputs a first count, and compares the first count to a value provided by a memory. Subsequently, a second signal is generated to initiate an interrupt when the first count equals the value. In a representative embodiment, a system for delaying transmission of an interrupt from a universal asynchronous receiver/transmitter (UART) to a microprocessor comprises a counter capable of generating a count, a memory capable of storing a value, and a comparator used for comparing the count to the value.

Abstract: An apparatus, system, and method for controlling access to a network. A device controls communication between a computer and the network. The device includes an integrated circuit receiving signals from one or more peripheral devices and transmitting the received signals to the computer, a first data connection connecting the computer to the device, and a second data connection connecting the apparatus to a network. The device also includes a switch connecting the first and second data connections and permitting the computer to access the network when in a first state and disconnecting the first and second data connections when in a second state. The device further includes a timer determining the time period since the last transmission of signals from the one or more peripheral devices, and when the time period since the last transmission of signals exceeds a predetermined time period the integrated circuit causes the switch to change from the first state to the second state.

Abstract: One embodiment provides a system which uses a temporal ordering policy for allocation of limited processor resources. The system starts by executing instructions for a program during a normal-execution mode. Upon encountering a condition which causes the processor to enter a speculative-execution mode, the processor performs a checkpoint and commences execution of instructions in the speculative-execution mode. Upon encountering an instruction which requires the allocation of an instance of a limited processor resource during the execution of instructions in the speculative-execution mode, the processor checks a speculative-use indicator associated with each instance of the limited processor resource. Upon finding the speculative-use indicators asserted for all instances of the limited processor resource which are available to be allocated for the instruction, the processor aborts the instruction.

Abstract: A system and a method for asynchronously signaling interrupts from a plurality of devices in a computing system, while optimizing the latencies in handling the interrupts. In a particular embodiment, an interrupt is signaled via a plurality of daisy chained devices by handing over the interrupt request from one device to another while retaining information regarding any interrupts handed over (also referred to as passed). In this way, the interrupt source can be readily identified (using a binary search, for example) thereby reducing interrupt latency and memory resources required to retain interrupt history.

Abstract: A system and method for interrupt processing includes a technique for exiting from interrupt mode in multiple processor systems. Those processors that were in a suspended or halt state immediately before entering the interrupt mode are released immediately with reference to the resolution of the interrupt condition. Those processors not responsible for the processing tasks associated with resolving the interrupt condition serially exit from interrupt mode on a time-delayed basis following the resolution of the interrupt condition.

Abstract: Described is a distributed copying technique that may be used in migrating large amounts of data from one or more source devices to one or more destination devices. The data source is divided into partitions. As Fibre Channel adapters (FAs) become available, each of the FAs may copy a partition of the data. In connection with specifying paths used for the distributed copying technique, a preferred path selection (source port-target port mapping) may be made by executing code in a controlling data storage system to perform discovery processing. The preferred path selection is used for the duration of the distributed copying unless the preferred path is unable to transmit data. A target port of the preferred path may be randomly selected from all accessible target ports, and/or in accordance with a specified portion of the target ports. Preferred paths may also be specified using an API (application programming interface).

Abstract: Techniques for reconstructing networks are provided. In one aspect, a method for reconstructing a synthetic network, such as a synthetic biological network, is provided. In another aspect, a method for reconstructing a supply chain network is provided. Exemplary supply chain networks include supply chains for petroleum distribution.

Abstract: A method for communication between first and second computer programs having a shared memory. The first computer program has a first work dispatcher for a first work queue. The second computer program has a second work dispatcher for a second work queue. Without causing an interrupt, a message or data is written for the second program from the first program to the shared memory and the second work queue is updated with a work item indicating a message or data for the second program. In association with the updating step, it is determined if the second program is currently busy. If so, the second program is not interrupted regarding the message or data. When the second program subsequently becomes not busy, the second program receives, without an interrupt, and executes the work item to receive the message or data. If the second program was not currently busy, the second program is interrupted to process the message or data on its work queue. This imposes a minimal burden on the second program.

Abstract: A system and method harvest data from at least one device, by canvassing the devices and tracking which canvassed devices yielded harvested data and then repeating such canvassing and tracking until either data has been obtained from all of the devices, or a certain time has passed since the beginning of the canvassing period. In a further embodiment, when data has been obtained from all the devices or the time has passed, whichever comes first, the harvested data is sent to a central processing center.

Abstract: A method and apparatus for an event handling mechanism are described. Under an embodiment of the invention, a method comprises setting a timer for a plurality of time intervals; calling a polling function at the end of each of the plurality of time intervals, the polling function being performed by a first processor; and if the polling function results in a positive result, processing the results of the polling function with a second processor.

Abstract: A method of generating interrupts and a network interface card, which minimizes the number of times that interrupts are generated, are provided. The method includes receiving data frames; estimating a first and second time delay and counting a number of received data frames; determining whether the first time delay has passed and generating an interrupt if the time reaches the first delay time, counting the number of data frames if the first time delay has not passed and generating the interrupt if the number of data frames is equal to N; determining whether the second time delay has passed if the number of data frames is not equal to N and generating the interrupt if the second time delay has passed; stopping operations of estimating the first and second time delays and counting the number of data frames in response to the interrupt generated, and transmitting the received data frames.

Abstract: A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies between nodes are made known and predictable greatly simplify the task of coordinating quiesce responses within the system. When latencies are not fixed and topologies such as open or closed bus architectures are be used a more dynamic approach is required to ensure system serialization. Adaptive quiesce logic on each node's SCE can dynamically identify the role of the node within the system and automatically configure itself to guarantee that no enabled processor within the entire system receives a quiesce indication before all processors have reached the stopped state. This is also true for systems where nodes are being concurrently added or removed during system operation. Bus states process quiesce requests.

Abstract: A processor control device includes a processor executing an instruction, a module coupled to the processor through a bus and processing independently from the processor, the module is provided in a plural number and a polling processing unit coupled to each module, the polling processing unit stopping an operation of the processor depending on an execution status of the module processing at a time of an access request from the processor.

Abstract: This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card (1) and a host device (2) are connected with each other in accordance with a six-wire-system half-duplex protocol using four-bit parallel signals, a bus state signal, and a clock signal. When the state of the bus state signal is a state of accepting interruption, the memory card (1) sends an interrupt signal (INT) to four-bit parallel buses. Different elements of interruption are allocated to the respective bits of the four-bit parallel signals. That is, the bit at which the INT signal is sent varies depending on the content of interruption.

Abstract: A method for communication between first and second computer programs having a shared memory. The first computer program has a first work dispatcher for a first work queue. The second computer program has a second work dispatcher for a second work queue. Without causing an interrupt, a message or data is written for the second program from the first program to the shared memory and the second work queue is updated with a work item indicating a message or data for the second program. In association with the updating step, it is determined if the second program is currently busy. If so, the second program is not interrupted regarding the message or data. When the second program subsequently becomes not busy, the second program receives, without an interrupt, and executes the work item to receive the message or data. If the second program was not currently busy, the second program is interrupted to process the message or data on its work queue. This imposes a minimal burden on the second program.

Abstract: In one embodiment, a data processing system includes, but is not limited to, a processor, a memory coupled to the processor, and a universal serial bus (USB) controller coupled to the processor and the memory. The USB controller includes a local memory to cache at least one activity descriptor of at least a portion of a periodic schedule having multiple frames stored in the main memory. The USB controller defers to service an active USB device described by one of the activity descriptors until a corresponding frame is scheduled to be serviced subsequently. Other methods and apparatuses are also described.

Abstract: An inquiring apparatus and method thereof is provided for assisting the CPU to inquire the state of the peripheral device. When the CPU needs to perform an inquiring process to wait for a peripheral device to come to an expected state, an inquiring apparatus is activated, instead of the CPU, to perform an inquiring process. The CPU is placed in a power-saving state which stops outputting the clock to the CPU when the inquiring apparatus performs the inquiring process. The inquiring process includes outputting a read cycle to the peripheral device receiving a current state of the peripheral device in response to the read cycle; and comparing the current state with the expected state. If the current state and the expected state are the same, the clock is outputted to the CPU again.

Abstract: In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying I/O into those to be processed at a priority and those not to be processed at a priority. The storage control apparatus comprises an I/O processing controller with a memory that is common for the whole controller. The storage control apparatus manages information for dividing and controlling a plurality of I/O processes as priority and non-priority in that memory and operates while suppressing non-priority I/O processing on the basis of information in the memory.

Abstract: This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card (1) and a host device (2) are connected with each other in accordance with a six-wire-system half-duplex protocol using four-bit parallel signals, a bus state signal, and a clock signal. When the state of the bus state signal is a state of accepting interruption, the memory card (1) sends an interrupt signal (INT) to four-bit parallel buses. Different elements of interruption are allocated to the respective bits of the four-bit parallel signals. That is, the bit at which the INT signal is sent varies depending on the content of interruption.

Abstract: Provided are a method, system, and program implemented by a device driver executing in a computer for handling interrupts from an associated device, wherein the device driver is capable of interfacing with the associated device. The device driver receives a call requesting whether an interrupt received from a device is from the associated device and reads interrupt status information in memory within the computer to determine whether the associated device transmitted the interrupt, wherein the device writes the interrupt status information to the memory. If the associated device transmitted the interrupt, then the device driver requests resources from the operating system to handle the interrupt.

Abstract: A Bus Driver implements an arbitration mechanism to allow both the system management interrupt (SMI) and the Bus Driver to cooperatively use a Bus host controller hardware. This mechanism employs a hardware-based semaphore (status bit) to allow either the SMI or the driver to claim ownership of the Bus host controller for an arbitrary period of time. While either the SMI or the driver may own the status bit, the other party must poll the bit until ownership is achieved. For the SMI, this involves scheduling a periodic SMI interrupt. The driver performs self arbitration of claiming the status bit to provide the periodic SMI interrupt the opportunity to claim the bit. The mechanism allows the SMI access to the Bus host controller in a “timely” manner, while minimizing impact to driver access to the Bus host controller, which could impact driver Bus transaction throughput.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings and literal symbols, whereby bounds checking need not be performed on each symbol. Because literal symbols and small substrings of symbols form the majority of compressed data, the reduced checking significantly speeds up decoding on average. In one implementation, a fast LZ77 decoder that operates without bounds checking is used in a first phase until the end of the output buffer is neared at which time a second phase standard decoder, which performs bounds checks on each to ensure that the buffer does not overflow, is used. Normally the standard decoder decompresses only a small amount of data relative to the amount of data decompressed with the fast decoder, greatly improving decompression speed while not compromising safety.

Abstract: Methods and apparatus control the loading of a memory buffer. The memory buffer may have a watermark with a first watermark value and can receive an advance indication of a memory service interruption. Based at least in part on the received advance indication of the memory service interruption, the watermark can be modified to have a second watermark value different from the first watermark value.

Abstract: A TAP linking module provides for control and access of plural TAPs on an IC through one set of JTAG signal pins. The IC includes plural circuit modules, each with its own TAP, and boundary scan registers connected to an additional TAP. All the TAPs and the linking module have their TDI, TMS and TCK inputs connected to one set of input pins on the integrated circuit. The TDO outputs of all the TAPs and linking module are connected to the TDO pin through a multiplexer. A special instruction scanned into an enabled TAP produces a select signal to the linking module. This disables the enabled TAP and causes the linking module to be the scan path between the TDI and TDO pins. Selection data scanned into the linking module disables the linking module and enables a TAP to be connected between the TDI and TDO pins.

Abstract: An apparatus, method and program product for use with a data processing system having a processor handling an I/O request in an I/O operation, main storage controlled by said processor for storing data, one or more I/O devices for sending data to or receiving data from said main storage in the I/O operation, and a summary register for registering I/O requests by any one or more of said devices. The apparatus includes a dispatcher for polling said summary register to determine if an I/O request is outstanding. A program in the dispatcher calculates a delay value responsive to the workload of the processor in handling I/O requests. An adapter between the device and the processor drives an interrupt of the processor if the calculated time delay is exceeded between completing I/O requests.