Abstract: Systems and methods for managing peripheral device connectivity based on context are described. In an embodiment, an IHS may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: select a first radio to communicate with a peripheral device; determine that at least one of: a distance between the IHS and the peripheral device, a battery level of the IHS, or a battery level of the peripheral device is greater or smaller than a threshold value; and, in response to the determination, select a second radio to communicate with the peripheral device.

Abstract: A configuration to enable a UE to send data to a modem, from an AP, in the absence of an uplink grant from the modem. An apparatus receives data transmissions from a base station. The apparatus stores the data transmissions in a memory of the AP of the apparatus. The apparatus identifies, by the AP, an uplink grant based at least in part on a size of a modem buffer. The apparatus determines, by the application processor, whether to send data to the modem based at least in part on the identified uplink grant. The apparatus sends, by the AP, the data when the identified uplink grant exceeds a threshold.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to operate under at least a first device protocol and a second device protocol, where the first and second device protocols have different endurance and protection requirements. When data is programmed to the memory device using the first device protocol, but is read from the memory device using the second device protocol, the differing endurance and protection requirements may cause issues in reading the data. In order to alleviate the issues, during idle time of the second device protocol, the controller may program the data using the endurance and protection requirements of the second device protocol to a different portion of the memory device so that the data may be read using either or both device protocols with the appropriate recovery information.

Abstract: A game data processing method, a storage medium, and an electronic device are disclosed. The method may include: a mapping relationship is established between a first client and a second client based on a first data transfer request from the first client; first game data of the first client is sent to the second client according to the mapping relationship; second game data from the second client is acquired, wherein the second game data is obtained through updating, by the second client, the first game data; the second game data is verified based on first user identification information of the first client to obtain a verification result; and in response to the verification result indicating that the second game data is approved, the first game data is updated to the second game data.

Abstract: In an embodiment a method for sharing a camera includes separately performing, by an electronic device, in response to an image obtaining request sent by a first application and an image obtaining request sent by a second application, the following operations: creating a first image consumer instance corresponding to the first application and creating a second image consumer instance corresponding to the second application, obtaining a corresponding first image provider instance based on the first camera and the first image parameter set that are requested by the image obtaining requests sent by the first application and the second application and establishing an association between the first image consumer instance and the first image provider instance and an association between the second image consumer instance and the first image provider instance.

Abstract: A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.

Abstract: Techniques are provided for dynamically implementing quality of service policies for a distributed storage system based upon resources saturation. A quality of service policy is defined for throttling I/O operations received by a node of the distributed storage system based upon whether resources of the node have become saturated. The quality of service policy is dynamically implemented based upon ever changing resource utilization and saturation. Dynamically implementing the quality of service policy improves the ability to efficiently utilize resources of the node compared to conventional static polices that cannot adequately react to such changing considerations and resource utilization/saturation. With conventional static policies, an administrator manually defines a minimum amount of guaranteed resources and/or a maximum resource usage cap that could be set to values that result in inefficient operation and resource starvation.

Abstract: Embodiments of the disclosure provide a method for enhancing standard authentication systems to include risk-based decisions. Risk-based decisions can be selectively implemented within existing authentication systems to strategically modify and supplement security if an unacceptable risk is detected. Embodiments capture information pertaining to a user and user device. Information is stored to create a profile for the user and user device. A comparison between the stored information and live data can be performed within authentication systems to optimize security. If the results of the comparison demonstrate the presence of an acceptable risk, then the need for subsequent authentication can be reduced or eliminated, which improves a user experience.

Abstract: Some examples described relate to securing a memory device of a computing system. For instance, a method may comprise comparing a command for the memory device to each command in a list of commands. The command is accepted when the command matches an authorized command in the list of commands. The accepted command is issued to the memory device.

Abstract: Systems and methods for providing workspace configuration recommendations in hoteling environments are described. In an embodiment, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive telemetry data from a plurality of client IHSs, where the telemetry data comprises integrated device data and workspace device data. The program instructions may, upon execution, further cause the IHS to identify, for a client IHS, a workspace configuration recommendation usable in a selected one of a plurality of workspaces based, at least in part, upon the telemetry data, and to transmit an indication of the recommendation to the client IHS.

Abstract: Techniques enabling multiple controllers to share a peripheral's serial interface as well as various systems and devices that may employ such techniques. One illustrative method includes configuring a controller to use an SPI (serial peripheral interface) bus for communication with a peripheral device only if a chain input terminal is asserted; and asserting a chain output terminal after the communication is complete. An illustrative system includes a peripheral device and multiple controller devices. The peripheral device has: a peripheral chip select terminal, a peripheral serial clock terminal, a peripheral controller output peripheral input (COPI) terminal, and a peripheral controller input peripheral output (CIPO) terminal.

Abstract: A storage system performs data replication with a recovery point objective (RPO). The storage system replicates data at intervals through data transfers over a network. The storage system determines bandwidth of the network. The storage system determines the intervals for replicating the data, based on size of data transfers, network bandwidth, and the recovery point objective.

Abstract: Techniques for processing read/write requests involve determining an average response time for read/write requests to a storage device within a predetermined time period, and comparing the average response time with at least one predetermined threshold. Such techniques further involve adjusting a read/write request upper limit of the storage device based on the comparison between the average response time and the at least one predetermined threshold. Here, the read/write request upper limit indicates the maximum number of read/write requests in a read/write request queue for the storage device. In this way, the read/write request upper limit of a storage device may be dynamically adjusted based on a current response time of the storage device for processing read/write requests, and slow read/write processing caused by the accumulation of read/write requests at one storage device can be avoided.

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes a memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Abstract: One or more systems, devices, computer program products, and/or computer-implemented methods provided herein to use a redundant array of disks. A system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components can comprise a control component that directs, for n physical drives of a redundant array of disks (RAID) storing data for at least n logical volumes, log-structured writing of data of each logical volume of the at least n logical volumes vertically across chunks of only a single physical drive of the n physical drives, wherein the control component further directs writing of parity data at each of the physical drives, which parity data at each physical drive of the subset respectively corresponds to other ones of the physical drives of the n physical drives.

Abstract: Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.

Abstract: One or more triggered-instruction processing elements are provided, a given triggered-instruction processing element comprising execution circuitry to execute processing operations in response to instructions according to a triggered instruction architecture. Input channel processing circuitry receives a given tagged data item (comprising a data value and a tag value) for a given input channel, and in response controls enqueuing of the data value of the given tagged data item to a selected buffer structure selected from among at least two buffer structures mapped onto register storage accessible to one or more of the triggered-instruction processing elements in response to a computation instruction for controlling performance of a computation operation. The selected buffer structure is selected based at least on the tag value, so data values of tagged data items specifying different tag values for the given input channel are allocatable to different buffer structures.

Abstract: A communication device receives, using a connectionless protocol, data transmitted by a transmission terminal. The communication device determines, in accordance with a receivable size of the communication device, a data transmission request in order to receive the data from the transmission terminal.

Abstract: Various methods, apparatuses/systems, and media for automating a process of receiving documentation are provided. A first computing device initiates an electronic communication process to request documentation from a second computing device utilized by a user. A processor receives identification information of the user for generating a unique barcode to be provided with the requested documentation in response to the initiation of the electronic communication. One or more processors generate the unique barcode based on the received identification information of the user; create an application programming interface (API) link for the generated barcode; transmit the electronic communication with the API link attached therein to the second computing device; and automatically obtain the unique barcode upon receiving an input to open the API link from the second computing device, the unique barcode to be attached as a cover sheet with the requested documentation for scanning by a multi-functional device.

Abstract: Protection of a kernel from a sniff and code reuse attack. A kernel mode page table in initialized in a kernel. The kernel page entries in the kernel mode page table are set from s-pages to u-pages. Supervisor mode access prevention is enabled in the u-pages. Code contained in the kernel page entries in the u-pages is executed, the kernel page entries in the u-pages are capable of execution but are not capable of being accessed and read directly.

Abstract: A method, system, and apparatus are disclosed herein for bridging a deterministic phase of instructions with a non-deterministic phase of instructions when those instructions are executed by a machine learning accelerator while executing a machine learning network. Specifically, data is transferred from off-chip memory to on-chip memory (non-deterministic phase of instructions). The data transfer involves determining whether certain on-chip memory is already storing data that has not been consumed yet (e.g., certain memory locations on-chip may be storing data for future consumption and should not be overwritten). Based on determining that the certain on-chip memory is not storing data that has not been consumed yet, the data may be transferred from the off-chip memory to the on-chip memory and the target memory locations may be marked as storing data that has not been consumed yet. The deterministic phase of instructions may be started subsequently.

Abstract: An information handling system may include a host processor module comprising a host processor field programmable gate array, a management controller communicatively coupled to the host processor field programmable gate array and configured to provide out-of-band management facilities for management of the information handling system, and an interposer configured to interface between the host processor field programmable gate array and one or more peripheral devices in order to perform power management and control of the one or more peripheral device. The interposer may include a general purpose input/output extender configured to enable and control power delivery to the one or more peripheral devices and a microcontroller unit communicatively coupled to the host processor field programmable gate array and configured to perform monitoring and discovery of the one or more peripheral devices.

Abstract: An apparatus comprising a CPU core configured to execute instructions and consume data. The apparatus includes a memory configured to store the instructions and the data. A memory protection shim is coupled to the CPU core and the memory. The memory protection shim is configured to perform transformations over digital blocks to perform at least one of authentication or decryption of the digital blocks received from the memory. The memory protection shim is coupled to the CPU core in a fashion that prevents egress of the digital blocks or ingress of other external digital blocks between the memory protection shim and the CPU core.

Abstract: A computerized system operating in conjunction with computerized apparatus and with a fabric target service in data communication with the computerized apparatus, the system comprising functionality residing on the computerized apparatus, and functionality residing on the fabric target service, which, when operating in combination, enable the computerized apparatus to coordinate access to data.

Abstract: In accordance with implementations of the subject matter described herein, there provides a solution for multi-path RDMA transmission. In the solution, at least one packet is generated based on an RDMA message to be transmitted from a first device to a second device. The first device has an RDMA connection with the second device via a plurality of paths. A first packet in the at least one packet includes a plurality of fields, which include information for transmitting the first packet over a first path of the plurality of paths. The at least one packet is transmitted to the second device over the plurality of paths via an RDMA protocol. The first packet is transmitted over the first path. The multi-path RDMA transmission solution according to the subject matter described herein can efficiently utilize rich network paths while maintaining a low memory footprint in a network interface card.

Abstract: An example computing device includes a plurality of interfaces to connect to a plurality of audio peripheral devices, a communications interface to establish a network connection, and a processor interconnected with the plurality of interfaces and the communications interface. The processor is to determine a location of the computing device based on the network connection. The processor sets an audio peripheral device from the plurality of the audio peripheral devices as a default audio peripheral device based on the location. The processor communicates an audio signal through the default audio peripheral device.

Abstract: An apparatus comprising a CPU core configured to execute instructions and consume data. The apparatus includes a memory configured to store the instructions and the data. A memory protection shim is coupled to the CPU core and the memory. The memory protection shim is configured to perform transformations over digital blocks to perform at least one of authentication or decryption of the digital blocks received from the memory. The memory protection shim is coupled to the CPU core in a fashion that prevents egress of the digital blocks or ingress of other external digital blocks between the memory protection shim and the CPU core.

Abstract: An adaptor includes non-volatile memory that stores a scan engine. A removable storage device is connected to the adaptor, which in turn is connected to a host computer. Files being copied between the removable storage device and the host computer through the adaptor are scanned for malware using the scan engine.

Abstract: A system is disclosed. The system may include a processor and a memory coupled to the processor. A storage device may also be coupled to the processor. The storage device may include a first interface and a second interface. The storage device may be configured to extend the memory. A mode switch may select a selected interface of the first interface and the second interface for a command issued by the processor.

Abstract: A surgical instrument is disclosed. The surgical instrument includes a first control circuit configured to communicate with an energy module using at least a first protocol over a first communication line and a second control circuit configured to communicate with another surgical instrument coupled to the surgical instrument using at least a second protocol over a second communication line.

Abstract: The present application discloses a pre-reading method and system of a kernel client, and a computer-readable storage medium. The method includes: receiving a reading request for a file and determining whether the reading of the file is continuous; if the reading of the file is discontinuous, generating a head node of a file inode, and constructing a linked list embedded in the head node; determining whether the file includes a reading rule for the file, and if the file includes the reading rule for the file, acquiring, based on the reading rule, the number of reading requests for the file and a reading offset corresponding to each request, generating a map route based on the number of reading requests and corresponding reading offsets, and storing the map route in the linked list; and executing pre-reading based on the linked list.

Abstract: Embodiments of a system and method to track the locality of a file being restored at the time of prefetching; and a mechanism to dynamically adjust the prefetching parallelism, per read batch, optimally based on the locality and other heuristics, such as system load. A process tracks locality of data elements in a batched data stream, as corresponds to a number of different container IDs accessed by the data elements. The prefetch nominally works serially on the data elements, however, if the locality exceeds a threshold separating acceptable versus non-acceptable distribution of data accesses, each batch is divided into a number of smaller sub-batches that are then pre-fetched in parallel with one another.

Abstract: A display device is disclosed that includes a display panel, a data driver, a timing controller, a memory device, and a power voltage generator. The display panel includes pixels. The data driver is configured to apply data voltages to the pixels. The timing controller is configured to control the data driver, to generate a test strobe signal by shifting a phase of a strobe signal, to perform a test write operation and a test read operation with the memory device based on the test strobe signal, and to increase a power voltage when an error bit occurs in the test write operation and the test read operation. The memory device is configured to sample memory data received from the timing controller using the strobe signal and to store sampled memory data. The power voltage generator is configured to apply the power voltage to the memory device.

Abstract: An apparatus includes a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes a plurality of memory blocks and a BGA component controller and firmware adjacent the plurality of memory blocks to manage the plurality of memory blocks. The apparatus further includes a processing device, included in the memory component, to perform memory operations on the BGA components.

Abstract: Method and apparatus for matched buffer decompression. In some examples, a circuit comprising a first data element, a second data element, a first buffer coupled to the first data element, a second buffer coupled to the second data element, compression override logic circuits coupled to the first data element and the second data element, and a parallel register coupled to the compression override logic circuits.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a privilege area and a normal area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a privilege mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: Methods of memory allocation in which registers referenced by different groups of instances of the same task are mapped to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.

Abstract: Techniques that facilitate machine learning optimization are provided. In one example, a system includes a computational resource component, a batch interval component, and a machine learning component. The computational resource component collects computational resource data associated with a group of computing devices that performs a machine learning process. The batch interval component determines, based on the computational resource data, batch interval data indicative of a time interval to collect data for the machine learning process. The machine learning component provides the batch interval data to the group of computing devices to facilitate execution of the machine learning process based on the batch interval data.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a secure area and a non-secure area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a secure mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: A system and method rate limits database access to, for example, prevent or reduce damage from unauthorized or errant access of a database by enforcing a network-level limit to the amount of data that may be accessed from the database. In at least one embodiment, a data transfer rate limiter monitors data transfer and determines whether the data transfer exceeds one or more predetermined thresholds. Based on the determination, the data transfer rate limiter generates a control signal that controls one or more processes that appropriately address any the data rate transfer of concern.

Abstract: Systems and methods of writing data acquired from measurement instrumentation. Embodiments include establishing a direct data connection between the test equipment and a network storage drive, generating test data from a sample under test, and writing the test data to the network storage drive without assistance of a computerized controlling device configured to control the testing device.

Abstract: An integrated circuit (IC) includes an Input/Output (I/O) interface, first-domain circuitry and second-domain circuitry. The I/O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I/O interface with the bit value.

Abstract: A data intake and query system provides interfaces that enable users to configure source type definitions used by the system. A data intake and query system generally refers to a system for collecting and analyzing data including machine-generated data. Such a system may be configured to consume many different types of machine data generated by any number of different data sources including various servers, network devices, applications, etc. At a high level, a source type definition comprises one or more properties that define how various components of a data intake and query system collect, index, store, search and otherwise interact with particular types of data consumed by the system. The interfaces provided by the system generally comprise one or more interface components for configuring various attributes of a source type definition.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may fetch a first command from the host into a command queue, suspend execution of the first command when receiving a lock request for the first command from the host, and resume the execution of the first command when receiving an unlock request for the first command or after the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request.

Abstract: Examples provide a method and apparatus for a multi-domain computing device providing physical separation of computing domains and network isolation. The multi-domain computing device includes a user facing panel with a shared display device and a keyboard, video mouse (KVM) switch. A set of domain-specific devices which are not shared between domains may include one or more processors, card readers, network devices, headset jacks, and power switches. The devices shared by the different domains include a display screen, power supply, the KVM switch and/or touchscreen. Each domain is configured to power up, boot and operate independently within a single physical unit.

Abstract: In response to a detected presence of an intended target appliance within a logical topography of controllable appliances identity information associated with the intended target appliance is used to automatically add to a graphical user interface of a controlling device an icon representative of the intended target appliance and to create at a Universal Control Engine a listing of communication methods for use in controlling corresponding functional operations of the intended target appliance. When the icon is later activated, the controlling device is placed into an operating state appropriate for controlling functional operations of the intended target appliance while the Universal Control Engine uses at least one of the communication methods to transmit at least one command to place the intended target appliance into a predetermined operating state.

Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for precisely tracking memory usage in a multi-process computing environment. One of the methods includes implementing an instance of a memory usage tracker (MUT) in each process running in a node of a computer system. A MUT can maintain an account of memory usage for each of multiple logical owners running on a process on which the MUT is running. The MUT can determine an actual memory quota for each owner, and enforce the actual memory quota of the owner. Enforcing the actual memory quota of the owner can include receiving each memory allocation request, checking each allocation request and a current state of the account against the actual quota, approving or rejecting each allocation request, communicating the approval or rejection to an underlying memory manager, and updating the owner account for each approved allocation request.

Abstract: An apparatus may be communicatively coupled to other nodes in a network. The apparatus may include a control circuit configured to repeatedly issue transmission cycles to the other nodes. A given transmission cycle may include a least one send slot for each of the other nodes to send data. The control circuit may be configured to initiate transmission cycles by issuing beacon signals to the other nodes. The control circuit may be configured to determine when to issue a beacon signal in a given transmission cycle by determining that all of the other nodes have completed all associated send slots in an immediately previous transmission cycle and based upon a determination of the completion of the other nodes' transmission, delaying transmission of the beacon signal for the given transmission cycle.