Abstract: A printer includes a printing unit powered from a battery which is charged by a charge IC, and a processor. The processor sets a mode of the printer to a print mode, and sets the mode to a low-power mode in which total power consumption of the printer is lower than that in the print mode, in a state that the printing unit stops printing. In a case where the processor sets the mode to the low-power mode, the processor sets the mode to a first low-power mode, in which the charge IC is driven at a first SW frequency, when the charge IC works to charge the battery, and sets the mode to a second low-power mode, in which the charge IC is driven at a second SW frequency lower than the first SW frequency, when the charge IC stops the charge of the battery.

Abstract: In accordance with one disclosed method, a client device may be caused to present a user interface for an application, the user interface enabling selective access to a plurality of resources via the client device. A state of a peripheral device that is connectable to the client device may be determined and, based at least in part on the state of the peripheral device, at least a first resource, from among the plurality of resources, may be identified with which the peripheral device can interact. Based at least in part on the identifying of the first resource, the user interface may be caused to include at least a first selectable user interface element that, when selected, causes the client device to access to the first resource so as to enable the peripheral device to interact with the first resource.

Abstract: Technologies for memory management with memory protection extension include a computing device having a processor with one or more protection extensions. The processor may load a logical address including a segment base, effective limit, and effective address and generate a linear address as a function of the logical address with the effective limit as a mask. The processor may switch to a new task described by a task state segment extension. The task state extension may specify a low-latency segmentation mode. The processor may prohibit access to a descriptor in a local descriptor table with a descriptor privilege level lower than the current privilege level of the processor. The computing device may load a secure enclave using secure enclave support of the processor. The secure enclave may load an unsandbox and a sandboxed application in a user privilege level of the processor. Other embodiments are described and claimed.

Abstract: A storage device includes a non-volatile memory; a volatile memory; and a memory controller configured to control the non-volatile memory and the volatile memory. The memory controller is configured to, in response to a determination that a progressive defect has occurred in at least one memory of the non-volatile memory or the volatile memory during an operation of the storage device, such that the at least one memory is determined to be a defective memory, perform a repair operation on the defective memory based on executing a memory revival firmware.

Abstract: A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.

Abstract: A computer uses an active cable architecture to control communications. The computer sends a first set of instructions for completion of an activity to a first micro-controller of an active communication cable. The computer determines that at least one transceiver of an active cable is to receive a set of signals from the first micro-controller. The computer forms a communication connection between the first micro-controller and the at least one transceiver. The computer sends a second set of instructions to the at least one transceiver, wherein the second set of instructions instruct the at least one transceiver to complete at least a portion of the activity.

Abstract: The technology disclosed herein enables segregation of network traffic on an application basis. In a particular embodiment, a method is performed in a virtual network interface for a first guest Operating System (OS) executing on a host and includes receiving guest data packets from the first guest OS. The method further includes associating the guest data packets with respective ones of a plurality of applications executing within the first guest OS and separating the guest data packets into respective ones of a plurality of application port interfaces each corresponding to at least one of the plurality of applications. The method also includes passing the guest data packets to a host network interface using the plurality of application port interfaces.

Abstract: A data processing system may include a plurality of memory systems and a host configured to provide commands for the memory systems. A first memory system among the memory systems may receive the commands from the host, check each of the memory systems where a plurality of command operations corresponding to the commands are to be performed, transmit respective commands among the commands to respective remaining memory systems except for the first memory system among the memory systems through a plurality of dedicated channels, and perform a first command operation corresponding to the first memory system in at least one of the remaining memory systems.

Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

Abstract: An input device includes a first body and a second body. When the first body is connected to the second body and the first body and the second body is disposed at a notebook computer, the first body and the second body are jointly used as a touchpad. When the first body is connected to the second body and both the first body and the second body are separated from the notebook computer, the first body and the second body are jointly used as a mouse. When the first body is separated from the second body and both the first body and the second body are separated from the notebook computer, the first body and the second body are respectively used as two independent remote controls. In addition, a notebook computer including the foregoing input device is also provided.

Abstract: The head-wearable display device according to the present invention is provided with one communication interface via which the head-wearable display device is connected with a portable terminal, to obtain audio and video data from the portable terminal, exchange data with the portable terminal and obtain working power supply from the portable terminal. As compared with current externally-connected type head-wearable display device which has to employ a plurality of cables, the head-wearable display device according to the present invention may operate normally in a way of connecting with the portable terminal via only one cable, without occupying too many communication interfaces of the portable terminal, avoids the problem that the head-wearable display device and portable terminal cannot establish connection because types and number of communication interfaces on the portable terminal cannot meet the needs of the head-wearable device.

Abstract: A semiconductor package includes: memory devices that are stacked one on another; and an inter-layer channel for communication between the memory devices, wherein each memory device includes: a data pad; a memory core; a data input/output circuit that inputs/outputs data through the data pad; an inter-layer channel transfer circuit that transfers a read data transferred from the memory core to the inter-layer channel or transfers a data inputted through the data input/output circuit to the inter-layer channel; an inter-layer channel reception circuit receiving the data of the inter-layer channel; a read error correction circuit correcting an error of the data transferred from the inter-layer channel reception circuit to produce an error-corrected data and transfers the error-corrected data to the data input/output circuit; and a write error correction circuit generating a parity data to be stored in the memory core based on the data transferred from the inter-layer channel reception circuit.

Abstract: A storage device utilizing read look ahead (RLA) may utilize auxiliary or spare latches as a RLA cache for storing pre-fetch data. The RLA may predict the next commands and do a speculative read to the flash using the latches for RLA storage. The auxiliary/spare latches may be present on a plane or die of non-volatile memory and may be different from the transfer data latch (XDL) that transfers data from the memory and the host. When the XDL is backed up, sense commands may still be performed and the data is stored in the auxiliary latches before being transferred with the XDL.

Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.

Abstract: A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in each switch box. The switch boxes are arranged into serial loading sets such that the switch boxes in each serial loading set are configured to form a multi-bit shift register chain for serial shifting the corresponding configuration words.

Abstract: Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.

Abstract: A method and an apparatus for transmitting content in a portable terminal are provided.

Abstract: A configurable interface includes a transmitter module and a receiver module, each configured to operate according to at least three different interface standards. The configurable interface further includes an interface module configured to determine a physical medium attachment (PMA) standard of a PMA coupled to the configurable interface and activate at least one component of the configurable interface based on the PMA standard. In an arrangement, the device interface supports a CAUI-4 standard.

Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).

Abstract: A device and method for writing/reading a piece of data in/from a memory register shared by a plurality of peripherals, each peripheral having a peripheral clock signal, when two or more of the plurality of peripherals need to write/read such piece of data at the same time, the digital device including a central unit having the memory register and a bank of SL modules in signal communication with the central unit, the bank of SL modules being designed to write/read the piece of data.

Abstract: Methods and apparatus relating to observing an internal link via an existing port for System On Chip (SOC) devices are described. In one embodiment, a logic within an SOC device may allow an external logic analyzer to observe communication between a first and second component of the SOC through an existing (e.g., shared and/or non-dedicated) interface. Other embodiments are also disclosed.

Abstract: A semiconductor device includes a data storage suitable for storing a training data for a training operation, a data bus inversion (DBI) calculator suitable for calculating DBI information for the training data input from the data storage through global transmission lines, generating a DBI flag signal based on the DBI information and outputting a DBI data, which is the training data inverted according to the DBI flag signal, in response to a DBI signal, a first multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the DBI data to a first channel in response to a training signal and the DBI signal and a second multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the DBI flag signal to a second channel.

Abstract: A method auto-switches interfaces between a client computer and subsystems in a device under management. A first output bus from a first subsystem is coupled to a client computer via a multiplexer, wherein the first subsystem is a subsystem from multiple system subsystems in the device under management. A hardware subsystem bus monitor monitors all output busses from the multiple system subsystems for a predetermined event on a bus. In response to the predetermined event being detected on a second output bus from a second subsystem in the device under management, the multiplexor decouples the first output bus from the client computer and couples the second output bus to the client computer.

Abstract: Operating a demultiplexer on an I2C bus, the demultiplexer including a set of input signal lines from an I2C master and a plurality of sets of output signal lines, the demultiplexer configured to couple the inputs among the output in dependence upon a demultiplexer select signal line that couples the demultiplexer to a rise time detection circuit, where the rise time detection circuit is also coupled to the input signal lines and the rise time detection circuit: monitors a voltage of at least one of the input signal lines, including: receiving, from the I2C master, a signal on one of the lines; and detecting rise time of the signal; and if the rise time of the signal is less than a predefined threshold, configuring the demultiplexer to vary the coupling of the input signal lines from a first set of outputs to a second set.

Abstract: A method of enabling a wireless communication between a master unit and at least one sensor unit is executed within a frame, the sensor unit having an internal data sampling frequency and being adapted to store samples with corresponding sample sequence numbers. The sensor unit transmits an integrated value to the master unit. The master unit transmits, during a master unit portion of the frame, a data update request message comprising an initial sample sequence number from which integration by the at least one sensor unit has to be carried out. The sensor unit integrates the sample values from the initial sample sequence number to a current sample sequence number and then transmits the integrated sample value and the current sample sequence number. The master unit receives the integrated sample value and current sample sequence number and stores at least the current sample sequence number.

Abstract: Disclosed herein is a data reception circuit including a clock generation block configured to divide a first clock based on clock information, the first clock being the clock of a transmission stream targeted to transmit video data between apparatuses, the clock information indicating a cyclical relationship between the first clock and a second clock serving as the clock of predetermined data, the clock generation block further outputting the divided clock as the second clock.

Abstract: A multi-protocol multiplexer provides signals according to different protocols for accessing a storage subsystem to a connector, where the signals according to a first protocol are to be routed over a first subset of channels of an interconnect to the storage subsystem, and the signals according to a second protocol are routed over a second subset of channels of the interconnect.

Abstract: Described is an integrated circuit (IC) that allows for communication between any input/output (I/O) pin and onboard peripherals. Accordingly, the resultant IC can be easily documented and connections between I/O pins and peripherals can be managed for each peripheral independently. The IC may include one or more sets of hardwired connections that provide a connection between of any I/O pin and any onboard peripheral. The hardwired connections may include the use of one or more crossbars. This increases the overall functionality and potential applications for an IC as the only limitation on peripheral connectivity is the number of I/O pins.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: The invention provides a bidirectional level shifter which includes: a first signal terminal; a second signal terminal; a first switch, coupled between the first signal terminal and ground; an inverter receiving a signal from the first signal terminal; a Schottky diode including an anode and a cathode, the anode receiving a signal from the second signal terminal; a second switch, coupled between the cathode of the Schottky diode and the ground; a comparing circuit, comparing a reference voltage and a voltage at the second signal terminal to control the first switch, wherein the reference voltage is lower than a forward bias voltage of the Schottky diode; a first voltage source coupled to the first common node; and a second voltage source coupled to the second common node.

Abstract: A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that are configured to receive a plurality of input channels from neighboring switch boxes in the array. Within a switch box, one of the I/O ports conditionally selects from the input channels received by the remaining I/O ports in the switch box to form a plurality of output channels to be driven to a neighboring switch box in the array.

Abstract: A method auto-switches interfaces between a client computer and subsystems in a device under management. A first output bus from a first subsystem is coupled to a client computer via a multiplexer, wherein the first subsystem is a subsystem from multiple system subsystems in the device under management. A hardware subsystem bus monitor monitors all output busses from the multiple system subsystems for a predetermined event on a bus. In response to the predetermined event being detected on a second output bus from a second subsystem in the device under management, the multiplexor decouples the first output bus from the client computer and couples the second output bus to the client computer.

Abstract: One switch-state aggregation technique uses a digital-to-analog converter in combination with an analog-to-digital converter to aggregate the state of a plurality of switches. Another switch-state aggregation technique uses input/output lines of a processor to aggregate the state of a plurality of switches and to communicate data other than the state of the switches. These techniques can be used to aggregate information about whether a plug or other connector is inserted into the ports of a patch panel or other telecommunication or communication assembly, system, or device.

Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).

Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.

Abstract: A processor has a central processing unit (CPU), a first CPU register set, a second CPU register set, a multiplexer logic for either coupling the first or the second CPU register set with the CPU, and control logic for controlling the multiplexer logic to switch from the first CPU register set to the second CPU register set upon receipt of at least one of a plurality of interrupt signals, wherein the at least one of a plurality of interrupt signals must meet a condition that is programmable within the control logic.

Abstract: A system and corresponding method for selectively communicating data between a first device and a second device is provided. An indication of a configuration of the second device is received by the first device. A selection signal is generated based on the configuration. Universal Serial Bus (USB) protocol data, uncompressed high definition media data, or a combination thereof may be caused to be selectively supplied to the second device by the first device based on the selection signal. The first device may be configured to transmit, on a DisplayPort link to the second device, a data flow comprising both USB protocol data and uncompressed high definition media data signals. The devices may be configured such that the USB protocol data is transferred from the second device to the first device during a video blanking period associated with the uncompressed high definition media data signals.

Abstract: A system and method to reduce and/or eliminate crosstalk between various data paths of a data bus within integrated circuits (i.e., chips). The system and method can transmit both delayed and non-delayed data in respective transmission paths, store the delayed and non-delayed data upon receipt, and delay the reading of the delayed and non-delayed data from the storage unit to compensate for the delay implemented on the transmission of the delayed data.

Abstract: A multiplexer receives multiple differential signals, selects one differential signal, and outputs, via an output port, the differential signal thus selected. The multiple differential signals are respectively input to multiple differential input ports. Multiple buffers are respectively provided to the multiple differential input ports. Each buffer includes a differential input terminal connected to a corresponding differential input port, and a differential output terminal connected to an output port. Each buffer is configured to be capable of switching states, according to the control signal, between an enable state in which a differential signal that corresponds to a differential signal input to the differential input terminal is output, and a disable state in which current consumed by the buffer becomes substantially zero, and the differential output terminal thereof is set to a high-impedance state.

Abstract: There is a need to alleviate or reduce crosstalk between bonding wires or wires in a device substrate. One selection configuration divides a multiplexed terminal group into three groups according to functions differently from another selection configuration that divides the multiplexed terminal group into two groups. A first multi-pin semiconductor device is configured such that the groups are successively arranged along one edge of the chip. The first semiconductor device connects with a second semiconductor device via a multiplexed terminal group. The multiplexed terminal group includes first through third interface terminal groups that differ from each other in signal input/output configurations.

Abstract: A device and method for writing/reading a piece of data in/from a memory register shared by a plurality of peripherals, each peripheral having a peripheral clock signal, when two or more of the plurality of peripherals need to write/read such piece of data at the same time, the digital device including a central unit having the memory register and a bank of SL modules in signal communication with the central unit, the bank of SL modules being designed to write/read the piece of data.

Abstract: A method for sharing data contained on a peripheral device amongst a plurality of blade servers is disclosed. The method includes storing a copy of data from a peripheral device to a memory device. The memory device is partitioned into at least ‘n’ memory areas, each memory area storing one copy of the data. The method also includes assigning one of the at least ‘n’ memory areas to each of a plurality ‘n’ of servers. The method also includes establishing communication between the plurality of servers and the plurality of assigned memory areas via a switch controller. The switch controller is configured to access the plurality of assigned memory areas via a processor.

Abstract: One embodiment of the invention comprises a non-transitory, tangible computer readable storage medium encoded with processor readable instructions to perform a method of transferring SDIO data. One method comprises buffering multiple IP packets to transfer from one of a SDCC host and a SDIO client to the other of the SDCC host and the SDIO client. A multiplexing header is attached to each of the multiple IP packets and one of at least one SDIO read command and at least one SDIO write command issued. The multiple IP packets are then transferred in a single SDIO transfer between the one of a SDCC host and a SDIO client to the other of the SDCC host and the SDIO client.

Abstract: Systems, devices, and methods for multiplexing one or more services are disclosed. Such systems and devices may have an architecture that includes communication interfaces, processors, storage devices, and software applications that generate virtual machines. Each of the virtual machines may receive a first set of service data for a service of the one or more services; process the first set of service data using the one or more software applications to generate a second set of service data and data instructions associated with the second set of service data; provides a service security function for the service; provide a service operating system; mine the first set of service data, including analytical information; and transmit the second set of service data and data instructions associated with the second set of service data to a display interface that may be a communication interface.

Abstract: An integrated circuit comprises a predefined logic area including a microprocessor coupled to a plurality of peripheral devices including an external bus interface over a system bus. A customizable logic area is accessible by the microprocessor over the system bus. A first I/O bus sends data to an external device. A second I/O bus receives data from an external device. A first set of multiplexers in the predefined logic area have first inputs coupled to an output of the external bus interface, second inputs coupled to the customizable logic area, and an output coupled to a first I/O bus. A second set of multiplexers in the predefined logic area have first inputs coupled to the customizable logic area, second inputs coupled to the second I/O bus, and an output coupled to an input of the external bus interface.

Abstract: The invention provides hardware based techniques for switching processing tasks of software programs for execution on a multi-core processor. Invented techniques involve a hardware logic based controller for assigning, adaptive to program processing loads, tasks for processing by cores of a multi-core fabric as well as configuring a set of multiplexers to appropriately interconnect cores of the fabric and program task specific segments at fabric memories, to arrange efficient inter-task communication as well as transferring of activating and de-activating task memory images among the multi-core fabric. The invention thereby provides an efficient, hardware-automated runtime operating system for multi-core processors, minimizing any need to use processing capacity of the cores for traditional operating system software functions.

Abstract: An output input (I/O) control apparatus and a control method thereof are provided. The I/O control apparatus includes an interface control unit, a read-only memory, a random access memory, a multiplexer and a micro-process unit. The interface control unit is coupled to a memory apparatus through a bus, and the memory apparatus is external to the I/O control apparatus. The read-only memory stores judgment codes. The multiplexer is controlled by the micro-process unit to switch to the interface control unit, the read-only memory or the random access memory. When the bus is not busy, the micro-process unit can read data from the memory apparatus. When the bus is occupied and busy, the micro-process unit can read and execute codes from the read-only memory or the random access memory so as to avoid computer system instability or thermal damage.

Abstract: A router has multiple channel inputs and multiple channel outputs and a switch core for selectively connecting at least two of the channel outputs to respective channel inputs. Each channel output is connected to an output signal path containing a FIFO register and the router is configured so that first and second channel outputs are connected to a pair of channel inputs respectively. The router configuration is changed so that the first and second channel outputs are connected to first and second channel inputs respectively. The FIFO registers in the output signal paths of the first and second channel outputs are forced to equal fullness.

Abstract: An apparatus for forming a color image has at least a first, a second, and a third illumination source, each illumination source energizable to provide continuous illumination of a first, a second, or a third wavelength band, respectively, to an optical multiplexer. The optical multiplexer is actuable to cyclically switch received light from each one of the illumination sources, in turn, to each one of at least a first, a second, and a third projector channel in a repeated sequence. The first projector channel connects to a first projector apparatus, the second projector channel connects to a second projector apparatus, and the third projector channel connects to a third projector apparatus. Each projector apparatus has a light modulator that is energizable to form an image from the light of the first, second, or third wavelength band that is cyclically switched onto its projector channel from the optical multiplexer.