Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: Direct memory access controller (DMAC) (54) adapted to directly execute C language style FOR tasks assigned by a processor (70), where the FOR task includes a movement of a data element from a first location to a second location in memory. The DMAC includes multiple execution units (EUs) (88, 90, 92), each to perform an arithmetic or logical operation, and a FOR task controller (80, 82, 86) to perform the data movement. The FOR task controller selects the operation to be performed by the EU. In one embodiment, the FOR task is made up of C language type FOR loops, where descriptors identify the control and body of the loop. The descriptors identify the source of operands for an EU, and the source may be changed within a FOR task. A descriptor specifies a function code for an EU and may specify multiple sets of operands for the EU.

Abstract: An apparatus and method for disk mapping and data retrieval includes a data storage medium on which has been stored a plurality of data records. Each record includes at least a record identification portion, for uniquely identifying each record from among the plurality of data records. The apparatus builds a record locator table in high speed semiconductor memory which comprises the unique record identifiers for the records on the storage medium as well as a record locator index generated by the apparatus, which indicates the address of the data record on the storage medium. Data retrieval is facilitated by first searching the record locator table in high speed semiconductor memory for a requested data record. Utilizing the record locator index associated with the requested data record, the system directly H: accesses the requested data record on the storage medium thereby minimizing storage medium search time.

Abstract: An apparatus for storing and reproducing data includes a detector to detect available space in a storage medium in which target data is configured to be stored, an estimator to estimate a compressed quantity of the target data if the target data is compressed at an initial bit rate, a comparator to compare the detected available space with the estimated quantity and provide a comparison result, and a DSP to determine a bit rate according to the comparison result, compress the target data at the determined bit rate, and configured to store the compressed data in the storage medium.

Abstract: The present invention generally relates to a loopback direct memory access control system for a digital scanner for processing images. More specifically, the present invention is directed to a method and apparatus for quickly reading digital data from memory, processing the digital data and writing the processed digital data to memory.

Abstract: The present invention provides for the compression of digital and analog data for storage and transmission. Analog data in the form of an analog signal is converted into a digital signal by an analog-to-digital converter. The digital signal is then converted into an analog signal having an alternating frequency by a first converter processor and an alternating frequency generator according to a predetermined conversion table. To reproduce the original analog signal, the analog signal having an alternating frequency is first converted back into a digital signal by an alternating frequency measurement means connected to a second converter processor, also in accordance with the predetermined conversion table. The digital signal is then converted to the original analog signal by a digital-to-analog converter.

Abstract: A method for reducing radio frequency interference from a high frequency serial bus by scrambling data signals and reducing the repetition of control signals. Beginning and ending control signals are provided with meaningless signals provided therebetween.

Abstract: The present invention provides a system and method for reducing memory requirements in a low resource computer system. Although examples herein are described in terms of embedded systems, the present invention is equally applicable to other low resource computer systems, such as palmtops, and laptops. Memory requirements, such as RAM requirements, can be reduced by combining virtual memory with a secondary memory with statically compressed contents. According to embodiments of the present invention, executable image of memory, such as the image of RAM, is compressed at image production time. The compressed image is then stored in a non-volatile memory, such as FLASH memory. At run-time, when a request identifying a virtual address is received, it is determined whether a physical address in the physical memory, such as RAM, is associated with that virtual address. If there is no physical memory associated with that virtual address, then a physical address is obtained to be associated with that virtual address.

Abstract: A processing system retrieves selected compressed audio data from a compact disc and produces sound based on the retrieved data. In this regard, the processing system utilizes a disc storage mechanism, a processing element, a system manager, and an audio output device. A compact disc is inserted into the disc storage mechanism. The system manager receives inputs from a user and, in response to the user inputs, reads organizational structure information stored on the compact disc. Based on the inputs and the organizational structure information, the system manager identifies a set of compressed data stored on the compact disc. The system manager retrieves instructions of a decompression application from the compact disc and transmits these instructions to the processing element. The processing element executes the received instructions, thereby decompressing the set of compressed data into uncompressed data.

Abstract: An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high speed system peripheral bus such as the PCI bus and couples to system memory. The IMC preferably uses a lossless data compression and decompression scheme. Data transfers to and from the integrated memory controller of the present invention can thus be in either two formats, these being compressed or normal (non-compressed). The IMC also preferably includes microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data from system I/O peripherals such as the hard drive, floppy drive, or local area network (LAN) are decompressed in the IMC and stored into system memory or saved in the system memory in compressed format.

Abstract: A Control B protocol for PostScript™ devices allows data to be compressed and transmitted to the PostScript™ device without the need of having bi-directional communications between the sending and receiving device to check for Control B capability or activation. The Control B protocol allows data to be transmitted in binary format, while control functions are represented by quoted character codes, thereby resulting in an efficient use of bandwidth between the devices.

Abstract: A disk control apparatus includes a host interface unit for inputting and outputting data from and to a host, a cache memory for temporarily storing the input data, a compression/decompression unit for compressing or restoring the input data and outputting the data, a buffer memory for temporarily storing the compressed data outputted from the compression/decompression unit, a disk access control unit for controlling an access to a disk and a disk data management unit for making a management as to which position of a disk storage device to write the data stored in the cache memory.

Abstract: In a wireless and/or wireline communications system (100), a method (400-536) and apparatus (200) for minimizing an amount of data (300) communicated between a source device (107, 108, 112 or 114) and a destination device (107, 108, 112 or 114) in order to modify an electronic document stored at said destination device. Said method and/or apparatus employs method steps and apparatus structure for editing a version of the electronic document stored at the source device via a set of input commands to create an edited version of the document. Thereafter, the set of input commands are transmitted to the destination device in order to modify the version of the electronic document stored at the destination device when the set of input commands are smaller in size than edited version of the document.

Abstract: The present invention provides an apparatus and method for transmitting serial data bits in a computer system having both an IEEE 1394 bus and a universal serial bus. The arrangement comprises a networked entertainment system comprising a host computer system and a remote peripheral consumer electronics device. The host system includes a processor, a bus, a memory, and a graphics card. A host interface circuit is coupled to the host system to provide an interface with a remote peripheral device. A remote interface circuit is coupled to the remote peripheral device to provide an interface with the host system. The host interface circuit and the remote interface circuit are connected to each other by an IEEE 1394 bus cable. The host interface circuit provides a USB port for connecting a USB device to the host system. The remote interface circuit provides USB ports for connecting USB devices.

Abstract: System and method for reducing data access latency for cache miss operations in a computer system implementing main memory compression in which the unit of compression is a memory segment. The method includes steps of providing common memory area in main memory for storing compressed and uncompressed data segments; accessing directory structure formed in the main memory having entries for locating both uncompressed data segments and compressed data segments for cache miss operations, each directory entry including index for locating data segments in the main memory and further indicating status of the data segment; and, checking a status indication of a data segment to be accessed for a cache miss operation, and processing either a compressed or uncompressed data segment from the common memory area according to the status.

Abstract: An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high speed system peripheral bus such as the PCI bus and couples to system memory. The IMC preferably uses a lossless data compression and decompression scheme. Data transfers to and from the integrated memory controller of the present invention can thus be in either two formats, these being compressed or normal (non-compressed). The IMC also preferably includes microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data from system I/O peripherals such as the hard drive, floppy drive, or local area network (LAN) are decompressed in the IMC and stored into system memory or saved in the system memory in compressed format.

Abstract: A digital information reproduction apparatus for compressing frames of data so as to intermittently reproduce the data in fast-forward speed. A data re-write device retrieves a reproduction-target frame for the fast-forward reproduction and a parameter-calculation-target frame exclusively for calculation of the frame data parameters. The frames then are transferred to a RAM. A decoder determines the frame data in the RAM, calculates the parameter-calculation frame data, and decodes the reproduction frame data by use of the parameter obtained as above. The described operation prevents expending the reproduction frame data with an incorrect parameter so as to normally fast-forward reproduce the compressed data. Furthermore, the present can select a frame used in the fast forward reproduction according to a feature index so that a section subjected to the fast-forward reproduction can be easily grasped by the user.

Abstract: The present invention provides a system and method for reducing memory requirements in a low resource computer system. Although examples herein are described in terms of embedded systems, the present invention is equally applicable to other low resource computer systems, such as palmtops, and laptops. Memory requirements, such as RAM requirements, can be reduced by combining virtual memory with a secondary memory with statically compressed contents. According to embodiments of the present invention, executable image of memory, such as the image of RAM, is compressed at image production time. The compressed image is then stored in a non-volatile memory, such as FLASH memory. At run-time, when a request identifying a virtual address is received, it is determined whether a physical address in the physical memory, such as RAM, is associated with that virtual address. If there is no physical memory associated with that virtual address, then a physical address is obtained to be associated with that virtual address.

Abstract: Data storage controllers employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. In one aspect, a data storage controller comprises a digital signal processor (DSP) comprising a data compression engine (DCE) for compressing data stored to the data storage device and for decompressing data retrieved from the data storage device; a programmable logic device, wherein the programmable logic device is programmed by the digital signal processor to instantiate a first interface for operatively interfacing the data storage controller to the data storage device and to instantiate a second interface for operatively interfacing the data storage controller to a host; and a non-volatile memory device, for storing logic code associated with the DSP, the first interface and the second interface.

Abstract: A mask ROM is employed for a semiconductor memory. The mask ROM records information in the stage of manufacturing so that the information cannot be thereafter rewritten. However, the manufacturing cost therefor can be reduced as compared with a nonvolatile memory such as an EEPROM, and it is optimal for recording contents requiring no rewriting. Thus, a card-type recording medium employing a semiconductor memory recording contents requiring no rewriting, which is at a lower manufacturing cost as compared with a nonvolatile memory such as an EEPROM, is provided.

Abstract: A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number.

Abstract: A physical layer interface for a serial bus includes a controller for producing parallel data representing a near-end line state of the serial bus. A line transmitter is connected to the controller for converting the parallel data therefrom into serial data and transmitting the serial data to the serial bus. A line receiver is connected to the serial bus for receiving therefrom serial dtaa and converting the received serial data into parallel data representing a far-end line state of the serial bus. A differential line state of the serial bus is detected from the parallel data of the controller and the parallel data of the line receiver. The detected differential line state is the input to the controller. In a modified embodiment, a far-end line state of the serial bus is detected from the near-end line state of the serial bus and a far-end differential signal received by the line receiver and directly supplied to the controller.

Abstract: Aspects for caching storage data include partitioning a storage cache to include a compressed data partition and an uncompressed data partition, and adjusting a size of the compressed data partition and the uncompressed data partition for chosen performance characteristics. A data caching system aspect in a data processing system having a host system in communication with a storage system includes at least one storage device and at least one partially compressed cache. The at least one partially compressed cache further includes an uncompressed partition and a compressed partition, where the compressed partition stores at least a victim data unit from the uncompressed partition.

Abstract: An advanced input/output interface is provided for an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol. The advanced input/output interface includes a bit compression circuit for receiving a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory. The bit compression circuit converts the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol. A bit decompression circuit receives a second signal formatted in the multi-level protocol. The bit decompression circuit converts the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol. In one embodiment, the advanced input/output interface allows for high speed/bandwidth memory accesses while reducing the pin count and operating frequency required for operation.

Abstract: In an optical data storage device for storing data on a removable optical disk in a continuous sequence of sectors or blocks, the input data buffer may be subject to under-run. An under-run detector is disclosed which is responsive to the buffered data comprising less than a sector of data for indicating an under-run, and a padding provider is disclosed which is responsive to the under-run indication for providing padding characters for formatting into sectors. The sectors may be provided with headers indicating the sectors as padding. A reading device for reading the data sectors and providing the data to a host detects padding and prevents the padding data from transmission to the host.

Abstract: System control of compression and decompression of data based upon system aging parameters, such that compressed data becomes a system managed resource with a distinct place in the system storage hierarchy. Processor registers are backed by cache, which is backed by main storage, which is backed by decompressed disk storage, which is backed by compressed disk storage then tape, and so forth. Data is moved from decompressed to compressed form and migrated through the storage hierarchy under system control according to a data life cycle based on system aging parameters or, optionally, on demand: data is initially created and stored; the data is compressed at a later time under system control; when the data is accessed, it is decompressed on demand by segment; at some later time, the data is again compressed under system control until next reference. Large data objects are segmented and compression is applied to more infrequently used data.

Abstract: An image operation processing apparatus is connected to a memory. The apparatus processes, by accessing the memory, a data packet including instruction information and an address of a prescribed address space. The apparatus realizes an address translation process for translating the address included in an incoming data packet to an address of a partial address space smaller than the prescribed address space. It further realizes a memory access process for accessing the memory in accordance with the address translated by the address translation process. Finally, it performs a process in accordance with the instruction information included in the data packet.

Abstract: A method and system for compressing bitmap data in a system for sharing an application running on a host computer with a remote computer, wherein the shared application's screen output is simultaneously displayed on both computers. Simultaneous display of screen output is achieved by efficiently transmitting display data between the host computer and the remote computer. When a font used by the host computer for displaying text is not available on the remote computer, the host computer sends a bitmap representation of the text for display, rather than the text itself. Bitmap representations are cached by the remote computer, so that the same bitmap representation need not be repeatedly transmitted from the host computer to the remote computer. Bitmap representations are compressed by the host computer prior to transmission, transmitted, then decompressed by the remote computer.

Abstract: A reference value is set for recording quantity of information, and a plurality of compression factors is provided for compressing information to be recorded. The compression factors are arranged in order. The information is sequentially recorded on a first memory at a first compression factor of the arrangement of the compression factors. It is determined whether the recording quantity of a first information group reaches the reference value. The first information group is compressed at a larger second compression factor when the recording quantities reaches the reference value, and the compressed first information group is recorded on the first memory at a first area. A second information group following the first information group is compressed at the second compression factor, and the compressed second information group is recorded on the first memory at a second area next to the first area. It is determined whether the sum of the recorded first and second information groups reaches the reference value.

Abstract: A system and method for silent Automatic Call Distributor (ACD) call monitoring in a telephony-over-LAN environment includes an ACD agent terminal for handling incoming calls from customers. A first call between the agent terminal and a customer terminal includes agent voice data and customer voice data. After the agent terminal has set up the first call with the customer terminal, the agent terminal receives a monitoring call setup request from a supervisor terminal. In response to the call setup request, the agent terminal cooperates with the supervisor terminal to establish a monitoring call over which the agent terminal transmits the agent voice data and the customer voice data to the supervisor terminal. The agent terminal monitors the first call for simultaneously transmitted agent voice data and customer voice data.

Abstract: A digital data recording method is provided where the efficiency of use of the recording medium storage area for recording data in a sequence is increased and a desired data can be retrieved at a higher speed. When a record n in an entity is terminated at the trailing end of a group N, a record n+1 following the record n is recorded in a group N+1. When a record n extends up to the group N+1, a header H2′ attributed to the group N and a front part of the record n as well as the preceding records 1 to n−1 are designated as another entity E2′. The remaining or rear part of the record n is designated as an entity E3′ and recorded in the group N+1 as added with a header H3′. Then, the record n+1 is designated as an entity E4 and recorded in the group N+1 as added with a header H4.

Abstract: A digital information reproducing apparatus in accordance with a prior art that uses a semiconductor memory to realize a memory means cannot reproduce digital data which has been encoded according to a compression coding form different from the one adopted by an incorporated decoding circuit. According to the present invention, a decoding program stored in a second semiconductor memory is selected according to a compression coding form adopted for digital data stored in a first semiconductor memory. The selected decoding program is used to decode the digital data by means of an arithmetic circuit. Thus, digital information can be reproduced irrespective of a compression coding form adopted for provided digital information.

Abstract: In accordance with the present invention, a method and apparatus are provided for efficiently transmitting data between stages of a decompression pipeline by implementing a control store register for minimizing the amount of data that is transferred among decompression units. The control store register is a register having memory locations that are associated with decompressed coefficients. As the coefficients are decompressed, a determination is made as to whether they contain zero or non-zero values. The result of that determination is stored in the control store register such that the processor performing the inverse quantization and inverse discrete cosine operations only retrieves non-zero coefficients. Therefore, data transmission is performed in an efficient manner.

Abstract: A reference value is set for recording quantity of information, and a plurality of compression factors is provided for compressing information to be recorded. The compression factors are arranged in order. The information is sequentially recorded on a first memory at a first compression factor of the arrangement of the compression factors. It is determined whether the recording quantity of a first information group reaches the reference value. The first information group is compressed at a larger second compression factor when the recording quantities reaches the reference value, and the compressed first information group is recorded on the first memory at a first area. A second information group following the first information group is compressed at the second compression factor, and the compressed second information group is recorded on the first memory at a second area next to the first area. It is determined whether the sum of the recorded first and second information groups reaches the reference value.

Abstract: An isochronous data pipe provides a bidirectional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any number of isochronous channels. The isochronous data pipe is a programmable sequencer that operates on the stream of isochronous data as it passes through the isochronous data pipe. The isochronous data pipe is programmed by an application to perform specific operations on the stream of data before the data is either transmitted across the bus structure or sent to the application, thereby pre-processing and manipulating the data before it is delivered to its destination. The operations are performed on both the packet header and the data field of the data packet. The isochronous data pipe can be stopped and started on the occurrence of specific events.

Abstract: A preferred coding network uses an architecture called a Base-Filter-Resource (BFR) system. This approach integrates the advantages of format-specific compression into a general-purpose compression tool serving a wide range of data formats. Source data is parsed into blocks of similar data and each parsed blocks are compressed using a respectively selected compression algorithm. The algorithm can be chosen from a static model of the data or can be adaptive to the data in the parsed block. The parsed blocks are then combined into an encoded data file. For decoding, the process is reversed.

Abstract: An automated telecommunication switch type and protocol detection routine transmits an interrogation message to a telecommunication switch. The contents of the interrogation message are such as to cause the switch to transmit a response message that uniquely identifies only one switch protocol and switch type. Once switch type and protocol have been automatically determined, this information may be coupled with an automated service profile identifier (SPID) detection mechanism to facilitate generation of the requisite SPID(s).

Abstract: The invention provides a method and apparatus for incorporating an appliance into a computer system. One embodiment of the invention has a computer with a first digital wireless transceiver, and an appliance unit with a second digital wireless transceiver for communicatively coupling to the first wireless transceiver. This appliance unit also has (1) an output device, communicatively coupled to the second wireless transceiver, for presenting an output presentation based on signals received from the computer via the wireless transceivers, and (2) an input device, communicatively coupled to the second wireless transceiver, for receiving input signals from a operator of the appliance unit.

Abstract: Relocation table entries in a executable object code file are interpreted as relocation instructions rather than as individual specifications for a particular respective relocatable information item. An abstract machine is provided for interpreting the relocation instructions and performing various relocation operations and various control functions for the abstract machine, in response to the relocation instructions. Certain variables contain information which is referenced and updated in response to certain types of the relocation instructions, thereby obviating the need to include such information as part of each relocation instruction. Certain of the relocation instruction types can also specify a particular relocation operation to be performed on a run of n consecutive relocatable information items, where n is specified as part of the relocation instruction.

Abstract: A system for compressing data and transferring the compressed data between a plurality of apparatus within a short period of time includes a dividing unit for dividing data into a plurality of divided strings of byte data, a compressing unit for concurrently compressing the strings of byte data which have been divided by the dividing unit, an expanding unit for concurrently expanding the compressed strings of byte data which have been transferred, a mixing unit for mixing the divided groups of byte data which have been compressed by the compressing unit, a distributing unit for distributing the groups of byte data which have been mixed by the mixing unit and transferred, and a combining unit for combining the groups of byte data which have been expanded by the expanding unit.

Abstract: A system and method for performing parallel data compression which processes stream data at more than a single byte or symbol (character) at one time. The parallel compression engine modifies a single stream dictionary based (or history table based) data compression method, such as that described by Lempel and Ziv, to provide a scalable, high bandwidth compression. The parallel compression method examines a plurality of symbols in parallel, thus providing greatly increased compression performance. The method first involves receiving uncompressed data, wherein the uncompressed data comprises a plurality of symbols. The method maintains a history table comprising entries, wherein each entry comprises at least one symbol. The method operates to compare a plurality of symbols with entries in the history table in a parallel fashion, wherein this comparison produces compare results. The method then determines match information for each of the plurality of symbols based on the compare results.

Abstract: An encoder for compressing video data to allow for its transmission over a narrow bandwidth. The encoder comprises a multiformat video codec for real-time compression digital data and a dynamic random access memory which operates as a temporary storage device storing compressed data while the codec is compressing data. A digital signal processor adjust the data compression ratio for the codec while the codec is compressing video data. An EPROM, which is connected to the digital signal processor contains the software to run the digital signal processor. A programmable gate array operates as an interface between the codec and an external processor. The array includes a read write controller which provides a read signal to the codec to allow compressed video data to be read from the codec to a parallel to serial shift register within the array. The write control signals which allow data to be written into and shifted through the register are also generated by the read write controller.

Abstract: An apparatus and method for transparent on-the-fly decompression of the program instruction stream of a processor. Connected between a processor and a memory storing compressed information is a decompression device. The decompression device, receives a request from the processor for information, retrieves compressed information from the memory, decompresses the retrieved compressed information to form uncompressed information, and transmits the uncompressed information to the processor. The compressed information may include both program instructions and data. When the decompression device receives a request for information, which includes an unmodified address, from the processor, it generates an index offset from the received unmodified address. An indexed address corresponding to the generated index offset is retrieved from an index table. Compressed information corresponding to the selected indexed address is retrieved from the memory and transmitted to the processor.

Abstract: An improved compressed file system is provided. In a preferred embodiment of the present invention, a memory cache is used for storing uncompressed data that is sent to or received from a compressed logical drive. When writing data to the compressed logical drive, the preferred embodiment of the present invention determines whether to use write-behind caching or write-through caching.

Abstract: An apparatus and method for disk mapping and data retrieval includes a data storage medium on which has been stored a plurality of data records. Each record includes at least a record identification portion, for uniquely identifying each record from among the plurality of data records. The apparatus builds a record locator table in high speed semiconductor memory which comprises the unique record identifiers for the records on the storage medium as well as a record locator index generated by the apparatus, which indicates the address of the data record on the storage medium. Data retrieval is facilitated by first searching the record locator table in high speed semiconductor memory for a requested data record. Utilizing the record locator index associated with the requested data record, the system directly accesses the requested data record on the storage medium thereby minimizing storage medium search time.

Abstract: A method and apparatus for managing update writing in place in linear address space mapped memories. This is attained by partitioning the memory into compressed and uncompressed areas, estimating the percent of compressible images of fixed-length symbol strings recordable into the image locations, revising the estimate upward or downward as a function of the persistency of runs of writes to one area or the other, and adjusting the relative number of locations in the areas proportionally to the revised estimate.

Abstract: A microprocessor includes a cache memory, a bus interface unit, and an execution engine. The bus interface unit is connected to the cache memory and adapted to receive compressed data from a main memory. The execution engine is connected to the bus interface unit and adapted to receive the compressed data from the bus interface unit. The execution engine decompresses the compressed data into uncompressed data and transmits the uncompressed data to the bus interface unit. The bus interface unit is further adapted to transmit the uncompressed data to the cache memory. The microprocessor may be used in a microprocessor system having a main memory capable of storing compressed data, where the bus interface unit transfers compressed data from the main memory to the cache memory in the microprocessor. A method is also provided for increasing memory bandwidth in a microprocessor system including a microprocessor having a cache memory.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract: An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high speed system peripheral bus such as the PCI bus and couples to system memory. The IMC preferably uses a lossless data compression and decompression scheme. Data transfers to and from the integrated memory controller of the present invention can thus be in either two formats, these being compressed or normal (non-compressed). The IMC also preferably includes microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data from system I/O peripherals such as the hard drive, floppy drive, or local area network (LAN) are decompressed in the IMC and stored into system memory or saved in the system memory in compressed format.

Abstract: A unique combination of software and hardware provides any computer with a system for high speed digital data communications using the computer's standard parallel printer port. The disclosed embodiment of the invention allows any computer with a standard parallel printer port to play or record digital audio sound allowing the computer to serve as a platform for multimedia presentations.