Abstract: An identification number inserting portion 26 in a multiplexing portion 33 in an audio transmission system 10 inserts a connection identification number for own connection into an audio band signal cell which is to be transmitted via an up line 60. An identification number detecting portion 30B detects that the connection identification number is transmitted again from a switching system 1 to the audio transmission system 10 via a down line 70.

Abstract: A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the shuffled result in a selected destination register (610). A shuffled result is formed by interleaving bits from a first source operand portion with bits from a second operand portion. A de-interleave and pack (DEAL) instruction is provided for de-interleaving a source operand. The shuffle instruction and the DEAL instruction have an exactly inverse effect. The DSP includes swizzle circuitry that performs interleaving or de-interleaving in a single execution phase.

Abstract: A method for storing lines of data in a data array of a cache memory mapped to a main memory of a processing system. The data array includes data storage lines having equal lengths. The method includes compressing at least one of the lines of data, fitting the compressed line of data within a subsection of one of the data storage lines, and pointing to the subsection using a tag array. When lines of data are stored in compressed form, more lines can fit into the cache, and a probability of a cache hit is increased.

Abstract: The present invention relates generally to a method and system for processing data. In a particular embodiment, the method includes receiving data to be processed from a network communication channel, storing the received data to be processed in memory based files at a computer memory that is local to and directly coupled to a processor via a high-speed memory bus, processing the received and stored data at the processor to produce processed data, compressing the processed data using a data compression software routine resident at the computer memory to produced processed and compressed data, and storing the processed and compressed data at a computer disk storage unit.

Abstract: Systems and methods for providing accelerated data storage and retrieval utilizing lossless data compression and decompression. A data storage accelerator includes one or a plurality of high speed data compression encoders that are configured to simultaneously or sequentially losslessly compress data at a rate equivalent to or faster than the transmission rate of an input data stream. The compressed data is subsequently stored in a target memory or other storage device whose input data storage bandwidth is lower than the original input data stream bandwidth. Similarly, a data retrieval accelerator includes one or a plurality of high speed data decompression decoders that are configured to simultaneously or sequentially losslessly decompress data at a rate equivalent to or faster than the input data stream from the target memory or storage device. The decompressed data is then output at rate data that is greater than the output rate from the target memory or data storage device.

Abstract: A system and method for compressing a data set. The method comprises the steps of: (i) requesting a data set from a server to be sent to a user, (ii) determining the size of the data set to be sent, (iii) compressing the data set, (iv) assigning a compression flag to the compressed data set, (v) sending the compression flag and compressed data set to the user, (vi) inspecting the data set for compression, (vii) uncompressing the data set; and (viii) processing the data set. Alternatively, upon determining the size of the data set to be sent, assigning an uncompressed flag to the data set, sending the uncompressed flag and data set to the user, inspecting the data set for compression, and processing the data set. In another alternative embodiment, upon determining the size of the data set to be sent, sending the uncompressed data set to the user, inspecting the data set for compression, and processing the data set.

Abstract: A computer workstation runs an application 10 to participate in a video conference. The workstation contains a video adapter card 18 which converts a video signal produced by a camera 20 into a hardware specific format. Likewise, the video adapter card can also be used to display incoming video signals that are in the same hardware specific format. The workstation also contains software support modules (SSM). On the capture side, the SSM 16 provides a video signal in bit map form for transmission to terminals in the conference which do not have compatible video hardware. Correspondingly, on the display side the SSM 34 receives and displays incoming video signals in bit map form from other workstations which likewise do not have compatible hardware.

Abstract: A program file or other type of information file for use in an embedded system is partially compressed in a host device and subsequently transferred to a non-volatile memory of the embedded system. The compressed portion of the file may include non-relocation data such as data sections, text sections, symbol tables, etc. The uncompressed portion includes relocation data such as section headers or a file header which identify one or more destination locations for corresponding parts of the file in a random access memory of the embedded system. A loading program running on a processor of the embedded system determines a destination location for at least part of the file within the embedded system without decompressing the compressed portion of the file. The invention advantageously eliminates the need for multiple file copy operations in transferring data between non-volatile memory and random access memory in an embedded system.

Abstract: A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a CPU, instruction cache, data cache, main memory, data buses and address bus. The method includes extracting compressible instruction and data portions from executable code, creating a mathematical model of the extracted code portions, class the individual instructions in the extracted portions based upon their operation codes and compressing the instructions. The compressed instructions are further compressed when extracted from memory by using bus compaction. The method is also embodied in a computer system with a processor and a memory adapted to perform the steps of the method to compress the extracted instruction portions. Additionally, the method is embodied on a computer program product bearing software instructions adapted to perform the steps of the method to compress the extracted instruction portions.

Abstract: A system and method for extracting data from a protected region of memory loads at least a first part of extraction code into physical memory and, thereafter, activates a memory mapping facility that maps a real memory onto the physical memory and prevents programs from accessing a protected memory region of the physical memory. At least a second part of the extraction code is then loaded into the virtual memory utilizing the memory mapping facility. The extraction code is then executed to deactivate the memory mapping facility and to copy data from the protected memory region to a second physical memory region, such that reactivating the memory mapping facility will cause a real memory region to be mapped onto the second physical memory region.

Abstract: A method for adding compressed page tables to an operating system is disclosed. An embodiment provides for a method in which a single entity, for example, an operating system has control of the compression and decompression of data and where the data is stored. When a data access is desired, the method accesses a table specifying the physical memory location of uncompressed data to determine if specified data is in uncompressed memory. The method of this embodiment accesses a table specifying the physical memory location of data in compressed memory to determine if the data is in the compressed memory. The method also access a page directory table to determine the location of the data in virtual memory in the event of a page fault. Then, this embodiment accesses the data based on the table look-up results.

Abstract: An expansion module for a Handspring Visor includes a multi-master AMBA Advanced System Bus (ASB). The Springboard bus of the visor is coupled to the ASB bus via Springboard-to-ASB-bus bridge. This bridge includes a protocol translator and a second Arm7 to ASB interface. The protocol translator translates bi-directionally between the Springboard bus protocol and the Arm7TDMI protocol. The translator includes an interface to the Springboard bus and a state machine. The state machine coordinates data transfers between the buses. The state machine also monitors signals indicating when each of the buses begins to treat a data transfer as complete so that the data transfer can be validated or flagged as an error condition. A programmable counter adjusts maximum counts to compensate for different clock frequencies in measuring a write-wait state duration to ensure valid writes from the Visor to the ASB bus.

Abstract: A method and system for parallel fetch and decompression of compressed data blocks is disclosed. A method first accesses a table of pointers specifying the location of compressed data to obtain a pointer. Using the pointer, the method reads a pointer in the first block of data, the pointer specifying the location of the next block of compressed data in a chain of compressed data blocks. The method also transfers the rest of the first compressed data block to be decompressed. The method then fetches the next compressed data block using the second pointer while decompressing the first compressed data block. Using a pointer in each successive compressed data block in the chain, the method pre-fetches the next compressed data block while the previous compressed data block is being decompressed.

Abstract: If a recording medium having a medium ID is used, a secure manager manages enciphering/decoding of a content with use of the medium ID for each recording medium. If a HDD having no medium ID is used, the secure manager obtains a device ID specific to a computer system through a BIOS and manages enciphering/decoding of a content to be recorded into the HDD, with use of the device ID. The device ID is stored in a safe area in the computer system. As a result, even if a content is recorded into an open recording medium such as a hard disk drive, the content can be protected from improper use so that utility and protection of digital contents can be improved.

Abstract: A portable memory device is provided that is capable of easy connection to a personal computer via a universal serial bus (USB) port, IEEE 1394 (i.e., firewire) or similar port. Included in the portable memory device is a compression/decompression engine capable of compressing and decompressing data. Data residing on a personal computer or other host platform is compressed by the engine and saved to the memory of the portable memory device. Compressed data is retrieved and decompressed by the engine and transmitted to the personal computer for use by the user. Embodiments of the present invention thus provide a highly convenient system and apparatus for users to access and save larger quantities of data to a relatively small device.

Abstract: An apparatus and a method for providing decoded information, the apparatus comprising: a memory module for storing encoded information; a decoder, coupled to the memory module, for fetching and decoding encoded information and for providing decoded information; and a cache, coupled to the memory module and to the decoder and to a recipient of decoded information, the cache is adapted to store at least one set of decoded information, to be provided to the recipient of information after a cache check condition is fulfilled and a cache hit occurs. A cache check condition is fulfilled when a change of flow occurs.

Abstract: The present invention provides for the compression of digital and analog data for storage and transmission. Analog data in the form of an analog signal is converted into a digital signal by an analog-to-digital converter. The digital signal is then converted into an analog signal having an alternating frequency by a first converter processor and an alternating frequency generator according to a predetermined conversion table. To reproduce the original analog signal, the analog signal having an alternating frequency is first converted back into a digital signal by an alternating frequency measurement means connected to a second converter processor, also in accordance with the predetermined conversion table. The digital signal is then converted to the original analog signal by a digital-to-analog converter.

Abstract: A coding device and method in which m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than ½. The coding device and method are also employed to record information on a recording medium and to transmit information. In the decoding method and apparatus, n-bit code words are decoded into m-bit information words. The decoding involves determining the state of a next n-bit code word, and based on the state determination, the current n-bit code word is converted into an m-bit information word. The decoding device and method are employed to reproduce information from a recording medium, and to receive information transmitted over a medium.

Abstract: Data storage controllers and data storage devices employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. In one embodiment of the invention, a composite disk controller provides data storage and retrieval acceleration using multiple caches for data pipelining and increased throughput. In another embodiment of the invention, the disk controller with acceleration is embedded in the storage device and utilized for data storage and retrieval acceleration.

Abstract: Systems and methods for providing fast and efficient data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises the steps of: analyzing a data block of an input data stream to identify a data type of the data block, the input data stream comprising a plurality of disparate data types; performing content dependent data compression on the data block, if the data type of the data block is identified; performing content independent data compression on the data block, if the data type of the data block is not identified.

Abstract: A method and apparatus is presented providing high-performance lossless data compression implemented in hardware for improving network communications. A compression module useful in a switching platform is also presented capable of compressing data stored in buffer memory. Instructions for a compression task are assigned to the compression module by a microprocessor writing a control block to a queue in stored local memory. The control block informs the compression module of the size and location of the unprocessed data, as well as a location in the buffer memory for storing the processed data and the maximum allowed size for the compressed data. Using this technique, the microprocessor can limit the compression of data to those data streams allowing compression, to those segments that are susceptible to compression, and to those segments that are large enough to show a transmission speed improvement via compression.

Abstract: The present invention provides a method in a computer system of integrating a compression system with an operating system. The computer system preferably comprises at least a memory device and one storage device. A user-supplied device driver is provided for storage devices that are not supported by the computer system to enable the computer system to communicate with the storage devices. In response to initialization of the computer system, the operating/compression system is loaded into the memory device and begins executing before any user-supplied device drivers are loaded into the memory device. Any compressed volume files located on the computer system are assigned drive letters at this time. When the user-supplied device drivers are loaded into the memory device, drive letters are assigned to the various storage devices. A drive letter conflict resolution scheme is provided to resolve conflicts that occur when the operating system attempts to assign a drive letter.

Abstract: An input device may operate with a variety of different host processor-based systems running a variety of different applications by providing a translation module which translates input commands in one format to a format compatible with one or more applications that may run on a given processor-based system. A table may be provided, for example, in software, which enables a variety of different input device formats to be converted into a variety of formats utilized by an application. In this way, contention between an application and an input device may be resolved.

Abstract: A method for storing data in a solid state device, comprising the steps of (A) retrieving data from a source device, (B) storing said data in a compressed format to said solid state device and (C) accessing and uncompressing portions of said data from said solid state device, wherein said portions represent data to be executed in response to an address.

Abstract: Systems and methods for providing accelerated data storage and retrieval utilizing lossless and/or lossy data compression and decompression. A data storage accelerator includes one or a plurality of high speed data compression encoders that are configured to simultaneously or sequentially losslessly or lossy compress data at a rate equivalent to or faster than the transmission rate of an input data stream. The compressed data is subsequently stored in a target memory or other storage device whose input data storage bandwidth is lower than the original input data stream bandwidth. Similarly, a data retrieval accelerator includes one or a plurality of high speed data decompression decoders that are configured to simultaneously or sequentially losslessly or lossy decompress data at a rate equivalent to or faster than the input data stream from the target memory or storage device. The decompressed data is then output at rate data that is greater than the output rate from the target memory or data storage device.

Abstract: There is provided an AV server system with high operationality for a simple use. A file system is not provided in an AV server, and AV data are continuously recorded or reproduced from a place (sector) of a random-accessible HD where a magnetic head is positioned.

Abstract: A system for, and method of, generating an alias source address for an electronic mail (“e-mail”) message having a real source address and a destination address and a computer network, such as the Internet, including the system or the method. In one embodiment, the system includes an alias source address generator that employs the destination address to generate the alias source address. The system further includes an alias source address substitutor that substitutes the alias source address for the real source address. This removes the real source address from the e-mail message and thereby renders the sender, located at the real source address, anonymous. Further-described are systems and methods for forwarding reply e-mail and filtering reply e-mail based on alias source address.

Abstract: A system and corresponding method for communicating non-I/O data between components of an industrial control system (ICS) including control or automation devices and a programmable logic controller. The method includes the steps of: having one of the components, such as a control or automation device, transmit the non-I/O data formatted as a message frame in the same way as a I/O data is formatted as a message frame, including having a message type identifier to identify that the message frame bears non-I/O data; and having another of the components, such as the programmable logic controller, receive the encapsulated non-I/O data as a message frame, wherein the receiving component identifies the non-I/O data based on the message type identifier conveyed with the message frame and extracts the non-I/O data from the message frame. The transmitting component transmits the non-I/O data over a field bus such as a PROFIBUS, INTERBUS, DEVICENET, CAN, or CAN OPEN types of field bus.

Abstract: A data storage system includes data storage and a record locator data structure in random access memory. The record locator data structure includes entries having different lengths. For locating variable-length data records in the data storage, for example, at least some but not all of the entries have a data-length portion indicating data length of a respective data record of the entry when the data length of the respective data record fails to match an expected data length. Each entry, for example, has a fixed length portion including an indication of whether or not the entry has a data-length portion, the fixed length portions are stored sequentially in a first region of address locations of the random access memory, and the data-length portions are stored sequentially in a second region of address locations of the random access memory.

Abstract: In a typical storage medium, such as a magnetic hard disk, there is a file allocation table (FAT) stored thereon which is referenced each time the medium is accessed. Many data processing mechanisms rely on the existence of this FAT for accessing the medium. However, some storage media, such as CD-ROM's, do not have FAT's stored thereon. In order to properly interface FAT reliant data processing mechanisms with storage media having no FAT, file storage information is first obtained from the storage medium. Then, using this file storage information, a FAT having a format compatible with the data processing mechanisms is generated. Information from the FAT is provided to the mechanisms and, using this FAT information, the mechanisms can access information on the storage medium. Thus, even though the storage medium has no FAT, it is still accessible by FAT reliant data processing mechanisms.

Abstract: A method and apparatus for efficient cache mapping of compressed Very Long Instruction Word (VLIW) instructions. In the present invention, efficient cache mapping of compressed variable length cache lines is performed by decompressing a sequence of compressed instructions to obtain decompressed cache lines and storing the decompressed cache lines in the same sequence in the cache memory. The present invention decouples the program counter based cache mapping from the memory address. In this way, a fixed increment cache pointer and variable size compressed cache line can be achieved, and, in doing so, decompressed cache lines fit nicely within the cache, in sequential order, while variable length compressed cache lines can be directly accessed without the use of a translation table.

Abstract: An information processing system has first and second information processing apparatuses. The first information processing apparatus has an internal auxiliary storage device. The second information processing apparatus does not include an internal auxiliary storage device. Both information processing apparatuses have a main storage device, communication unit and auxiliary-storage-device control unit. The second information processing apparatus has an emulation mechanism for carrying out CKD-FBA format conversion to a series of CCW commands. Specifically, a command is set to access the internal auxiliary storage device and the emulation mechanism transmits the command set to the first information processing apparatus having the internal auxiliary storage device by way of the communication unit of the second information processing apparatus and a communication path.

Abstract: A disk control apparatus includes a host interface unit for inputting and outputting data from and to a host, a cache memory for temporarily storing the input data, a compression/decompression unit for compressing or restoring the input data and outputting the data, a buffer memory for temporarily storing the compressed data outputted from the compression/decompression unit, a disk access control unit for controlling an access to a disk and a disk data management unit for making a management as to which position of a disk storage device to write the data stored in the cache memory.

Abstract: In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies and, wherein information stored within the main memory is indirectly accessible by a processor through a compression and decompression mechanisms, an improved memory architecture that accommodates the necessary compressed information data structures, together with a memory region and mapping method for storing information that bypasses the compression and decompression mechanisms to provide low latency processor access to certain address spaces.

Abstract: A computing system includes a storage server having a memory organization that includes a compressed memory device for storing sectors, each sector having a sector data portion and associated header and trailers, either attached by the hosts or by components of the computing system. The compressed memory device comprises a memory directory and a plurality of fixed-size blocks. The system implements a methodology for detaching headers and trailers from sectors before storing the sectors in the memory, and storing the headers and trailers in the memory disk cache, separate from the sector data portion; and, reattaching headers and trailers to sector data portions when the sectors are sent from the memory to a host or to a mass storage device. The header and trailer data are managed through the same memory directory used to manage the compressed main memory.

Abstract: A method and apparatus are provided for reducing the number of cache line data transfers among components of a computer system, thus reducing the amount of traffic on a bus and increasing overall system performance. A sideband communication line is provided to transfer information from a source cache agent pertaining to redundant data strings occurring in a cache line to a destination cache agent. If redundant data strings occur in a cache line, the transfer of one or more portions of a cache line from the source to the destination can be canceled. Redundancy logic is provided to detect occurrences of redundant data strings located in a given cache line, generate and transfer redundancy bits when predetermined redundant data strings occur and decode redundancy bits at a destination cache agent to determine whether redundant data strings occur in subsequent cache lines to be transferred.

Abstract: A compression system stores meta-data in the compressed record to allow better access and manage merging data. Markers are added to the compression stream to indicate various things. Each compressed record has a marker to indicate the start of the compressed data. These markers have sector number as well as the relocation block numbers embedded in their data. A second marker is used to indicate free space. When compressed data is stored on the disk drive, free space is reserved so that future compression of the same, or modified, data has the ability to expand slightly without causing the data to be written to a different location. Also the compressed data can shrink and the remaining space can be filled in with this free space marker. A third type of marker is the format pattern marker. Compression algorithms generally compress the format pattern very tightly. However, the expectation is that the host will write useful data to the storage device.

Abstract: A system for interconnecting a plurality of interdependent fiber channel loops or fabrics. The system preferably comprises a first server which includes a PCI bus and a fibre channel to PCI bus adapter for each one of the plurality of the independent fibre channels. Each fibre channel to PCI bus adapter is configured to connect one of the plurality fibre channels to the PCI bus at the first server. The plurality of independent fibre channels then communicate with each other across the PCI bus of the first server utilizing the intelligent I/O (I2O) routing of the fibre channel to PCI bus adapters. The plurality of fibre channels are configured to communicate with the other fibre channels, as well as the first server via the PCI bus. This system can be configured such that any one of the plurality of fibre channels can include one or more devices connected thereto in addition to the first server.

Abstract: The present invention provides a system and method for reducing memory requirements in a low resource computer system. Although examples herein are described in terms of embedded systems, the present invention is equally applicable to other low resource computer systems, such as palmtops, and laptops. Memory requirements, such as RAM requirements, can be reduced by combining virtual memory with a secondary memory with statically compressed contents. According to embodiments of the present invention, executable image of memory, such as the image of RAM, is compressed at image production time. The compressed image is then stored in a non-volatile memory, such as FLASH memory. At run-time, when a request identifying a virtual address is received, it is determined whether a physical address in the physical memory, such as RAM, is associated with that virtual address. If there is no physical memory associated with that virtual address, then a physical address is obtained to be associated with that virtual address.

Abstract: The present invention provides for the compression of digital and analog data for storage and transmission. Analog data in the form of an analog signal is converted into a digital signal by an analog-to-digital converter. The digital signal is then converted into an analog signal having an alternating frequency by a first converter processor and an alternating frequency generator according to a predetermined conversion table. To reproduce the original analog signal, the analog signal having an alternating frequency is first converted back into a digital signal by an alternating frequency measurement means connected to a second converter processor, also in accordance with the predetermined conversion table. The digital signal is then converted to the original analog signal by a digital-to-analog converter.

Abstract: A data system comprising a store (10), a memory (12), a user interface (32) and a memory controller (24) where the memory is used to buffer all data transferred between the user interface and the store, the system being characterized in that the memory controller copies data directly between the store and the memory, whereas the memory controller re-organizes data when the data is transferred between the memory and the user interface.

Abstract: A method and apparatus are provided for reducing the number of cache line data transfers among components of a computer system, thus reducing the amount of traffic on a bus and increasing overall system performance. A sideband communication line is provided to transfer information from a source cache agent pertaining to redundant data strings occurring in a cache line to a destination cache agent. If redundant data strings occur in a cache line, the transfer of one or more portions of a cache line from the source to the destination can be canceled. Redundancy logic is provided to detect occurrences of redundant data strings located in a given cache line, generate and transfer redundancy bits when predetermined redundant data strings occur and decode redundancy bits at a destination cache agent to determine whether redundant data strings occur in subsequent cache lines to be transferred.

Abstract: A control means 24A reads an unrecorded area of a recording medium 25 in advance, and stores the read unrecorded area in a stack of a RAM 11. The unrecorded area is stored in the stack of the RAM 11 by being pushed onto the bottom of a stack pointer. When new data is recorded on the recording medium 25, recording is executed in order from the top of the stack pointer. Accordingly, information which continuously progresses in a time series manner can be recorded on the recording medium 25 without lack of the information which continuously progresses, and it is possible to reduce the time required to calculate and display the remaining recording time.

Abstract: A data compressor uses data known to exist on a destination computer for compressing an input data stream by encoding portions of the input data stream as references to matching portions of the known data. The known data is preprocessed to better correlate with the input data stream. The preprocessing includes identifying and modifying internal references in the known data, such as relative offsets and addresses of jump and call instructions in executable code or cross references and hyperlinks in documents. The preprocessing is driven by generating a set of data that describes specific individual modifications or alternatively indicates relationships between the known data and the input data stream, such as code or data block motion, from which individual modifications can be deterministically made.

Abstract: The present invention generally relates to a digital scanner for scanning images. More specifically, the present invention is directed to a method and apparatus for quickly processing and storing digital data in memory.

Abstract: There is provided an address decoding circuit including (a) a first address decoder for practical use for decoding an address which is particular to an individual object, (b) a second address decoder for test use for decoding a constant address regardless of objects, and (c) a logic circuit receiving a selection signal and switching from decoding result transmitted thereto from the first address decoder to decoding result transmitted thereto from the second address decoder, and vice versa in accordance with the selection signal. The address decoding circuit selects decoding result of an address used for a test, which is particular to peripheral macros, in a test mode in accordance with the selection signal. Hence, when peripheral macros are mounted on different chips, it would be possible to use a common vector, even if an address for practical use is changed. This ensures reduction in steps of re-constructing test vector.

Abstract: A data transfer apparatus and a data transfer system intended to transfer data continuously input or output to/from a main memory without any interruption and to transfer continuous data on a general-purpose bus such as a PCI bus, and a recording medium storing a program that commands a computer to execute all or some of functions of each component of the data transfer apparatus or the data transfer system.

Abstract: In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies, a method and apparatus for enabling termination of a pending compression operation for the purpose of writing the data directly to the main memory, bypassing the compressor hardware during stall conditions. Memory space (compressibility) is sacrificed for higher system performance during these temporary write back stall events. A background memory scrub later detects and recovers the “lost” compressibility by recycling the uncompressed data back through the compressor during idle periods.

Abstract: Compression-decompression functions provided in the recording device are easily replaceable so that they conform with the compression-decompression function provided in the host computer. A recording device 10 connected with a host computer 20 for operation based on commands from the host computer 20 comprises a interface card 12 mounted in the recording device 10 replaceably with respect to the control board 11 for exchanging data with the host computer 20. A first data decompressor 30 is included in the interface card 12 for decompressing compressed data to be exchanged between the host computer 20 and recording device 10. This allows selection and replacement of decompression function in the recording device in conformance with the compression algorithm in the host computer without replacing the recording device as a whole.

Abstract: A method of operating a processor (30). The method comprises a first step of fetching an instruction (20). The instruction includes an instruction opcode, a first data operand bit group corresponding to a first data operand (D1′), and a second data operand bit group corresponding to a second data operand (D2′). At least one of the first data operand and the second data operand consists of an integer number N bits (e.g., N=32). The instruction also comprises at least one immediate bit manipulation operand consisting of an integer number M bits, wherein 2M is less than the integer number N. The method further includes a second step of executing the instruction, comprising the step of manipulating a number of bits of one of the first data operand and the second data operand. Finally, the number of manipulated bits is in response to the at least one immediate bit manipulation operand, and the manipulating step is further in response to the instruction opcode.