Abstract: A Universal Serial Bus to parallel bus bridge includes a Universal Serial Bus port that receives a serial bit stream of data and commands in a Universal Serial Bus protocol from a USB host computer. A parallel bus port on the bridge includes parallel port registers and state machines coupled to a peripheral device. A USB controller core is coupled between the Universal Serial Bus port and the parallel bus port and converts data and commands between the Universal Serial Bus protocol and the parallel bus protocol. A sequencer is coupled between the USB controller core and the parallel bus port. A sequence of sequencer commands is loaded into memory in the USB bridge and used by the sequencer to perform a sequence of parallel port operations. The sequencer performs the commands autonomously without intervention from the USB host computer.

Abstract: The communications interface enables a processor unit to dialog with an IC card having an elementary time unit (ETU) for transmitting one bit that is equal to (K/Fs). The IC card includes a microprocessor, a clock pin for application of an external clock signal enabling the microprocessor of the IC card to be clocked, and an I/O pin. The microprocessor receives external data or transmits data via the I/O pin. The communications interface includes a serial communications line for interchanging data with the IC card via the I/O pin. The communications interface also includes a transmitting module, which is written-addressable by the processor unit and includes a serialization module for serializing and transmitting, over the serial communications line, data received from the processor unit. The communications interface also includes a receiving module, which is read-addressable by the processor unit and includes a serialization module for serializing data received over the serial communications line.

Abstract: An encoder for compressing video data to allow for its transmission over a narrow bandwidth. The encoder comprises a multiformat video codec for real-time compression digital data and a dynamic random access memory which operates as a temporary storage device storing compressed data while the codec is compressing data. A digital signal processor adjust the data compression ratio for the codec while the codec is compressing video data. An EPROM, which is connected to the digital signal processor contains the software to run the digital signal processor. A programmable gate array operates as an interface between the codec and an external processor. The array includes a read write controller which provides a read signal to the codec to allow compressed video data to be read from the codec to a parallel to serial shift register within the array. The write control signals which allow data to be written into and shifted through the register are also generated by the read write controller.

Abstract: Disclosed is a device for the conversion of a series signal received in the form of a low-amplitude, high-frequency differential signal into n parallel signals. The device uses a scheme derived from that of a static memory cell as a sample-and-hold unit and amplifier. The device continues to perform well when the differential signal comprises noise in common mode.

Abstract: A method and associated circuitry are described for interfacing a software-based modem in a computer system. Memory/modem interface circuitry is integrated within a system controller coupling a main memory with a microprocessor. A dedicated region of the main memory is configured as separate transmit data and received data buffer regions. Buffer address registers included within the system controller store values pointing to address locations within the buffer regions of the memory for next data in and next data out. The values programmed in these registers are incremented responsive to associated data transfers in/out of the buffer regions, and the transmit data and received data buffer regions function as FIFOs. The frequency and duration of processor utilization imposed by software-based modems is significantly reduced, due to FIFO operations functioning at main memory access speed.

Abstract: A serial to parallel interface for coupling multiple channels of audio input data to a digital audio workstation (DAW) having at least one processor capable of performing digital signal processing functions is formed from a programmable ASIC. The serial to parallel interface includes configuration registers which may be programmed to allow the interface to communicate with external audio devices that are operating in any audio format and bit width format. The serial to parallel interface includes a double buffered input and output serial datapath. The double buffered input and output datapath eases timing constraints between the interface and the DSP, thus allowing the DSP the flexibility of being able to read data at almost any point during an audio data transmission period. In addition, the double buffering mechanism within the serial to parallel interface allows for sample receipt errors to be isolated from the DSP, thereby ensuring the integrity of the audio data before it is propagated to the DAW.

Abstract: A single chip integrated circuit device includes a bus system for effecting communication of parallel data on chip, functional circuitry connected to the bus system for executing an operation in response to parallel data received from the bus system, an external port, and a serial to parallel data packet converter interconnecting the parallel bus system and the external port. The external port includes a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device. The serial data packets each include a packet identifier indicating the length of the data packet and information defining an operation to be executed by the functional circuitry.

Abstract: A serial/parallel interface for interfacing the serial port of a microcontroller with parallel bus devices, and a protocol for communicating with the same. The interface operates to maximize through-put with minimum handshaking by incorporating logic within the interface itself to control data flow. A row/column count state machine in the interface accumulates serial clock pulses from the microcontroller and controls the latching of parallel output data. A read/write state machine accumulates addresses and controls the read/write operation in response to a command sent by the microcontroller in the serial data stream. The read/write state machine accumulates addresses in response to an interface clock derived from the serial clock from the microcontroller.

Abstract: The present invention is a method and apparatus for virtualizing a serial bus information source/sink point of a serial bus device into an address space of a processor. A register unit is coupled to a parallel port device to support a serial bus transaction between the processor and the serial bus device. The register unit has a plurality of registers which are mapped into the address space of the processor via the parallel port device. One of the plurality of registers corresponding to the serial bus information source/sink point. A control circuit is coupled to the register unit to allow the processor to access the information source/sink point via the parallel port device.

Abstract: A bus arbitration interface comprises first and second serial/parallel converting units connecting a DMA device to an LSI with a DMA controller built therein for exchanging a request signal sent from the DMA device to the DMA controller and an acknowledge signal sent from the DMA controller to the DMA device as serial signals, a DMA arbitration bus interface, that is an outside interface of the LSI, provided with signal I/O pins; and a DMA device arbitration interface that is an outside interface of the DMA device.

Abstract: Circuitry is described for interfacing a software-based modem in a computer system. Memory/modem interface circuitry is integrated within a system controller coupling a main memory with a microprocessor. A dedicated region of the main memory is configured as separate transmit data and received data buffer regions. Buffer address registers included within the system controller store values pointing to address locations within the buffer regions of the memory for next data in and next data out. The values programmed in these registers are incremented responsive to associated data transfers in/out of the buffer regions, and the transmit data and received data buffer regions function as FIFOs. The frequency and duration of processor utilization imposed by software-based modems is significantly reduced, due to FIFO operations functioning at main memory access speed.

Abstract: A system is provided for packing and unpacking data being transferred between a serial network connection and a parallel system bus of a computer system. In the receive direction, this is achieved by unpacking fixed length serial data packets into a receive payload buffer. Data is then incrementally fetched from the receive payload buffer and stored in a first latch. The contents of the first latch are then transferred to a second latch, while additional fixed length serial data packets are store in the first latch. The data stored in the first and the second latch is then aligned in an aligner module depending on an address offset in a host computer memory and stored in an unpacker module. Variable length data is then retrieved from the unpacker module and stored in the host computer memory. In the send direction, this is achieved by aligning and packing variable length data transferred into a send payload buffer. Variable length data is first stored in a first latch.

Abstract: Apparatus, and an associated method, converts a conventional computer peripheral device, such as an I/O (input/output) subsystem into an I.sub.2 O-aware device. An IOP mounted upon a connector card is connected to a computer bus to which the conventional computer peripheral device is connected. Once connected, the IOP, together with the conventional computer peripheral device form an I.sub.2 O-aware device.

Abstract: An I/O interface for an integrated circuit (IC) is described that has a reduced number of I/O pins dedicated to providing control signals to or status information from the IC. In one embodiment, the IC comprises a plurality of input pins connected to logic for receiving and processing input data. The input pins have an input bandwidth greater than the logic's processing rate. If data and control signals are multiplexed onto the same input pin, the excess input pin bandwidth may used to transfer control signals into a plurality of latches within the IC. The I/O interface outputs a select signal that designates when an external device should drive the input pins with either data or control signals. In a specific embodiment, the logic comprises a parallel to serial converter and the control signal select conversion speed or encoding options. In another embodiment, the IC comprises a plurality of output pins connected to the output of a selector.

Abstract: The communication control device allows a plurality of data items to be transferred to and from external devices, such as a CPU and a memory, via an external bus having a different data bus width in DMA (direct memory access) transfer mode. DMA transfer is controlled by the DMA controller provided in the communication control device. The DMA controller produces a signal indicating that a plurality of data items are continual.

Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.

Abstract: There is disclosed a single chip integrated circuit device having a bus system, functional circuitry, and external port, and a parallel/serial data packet converter interconnecting the bus system and the external port. The parallel/serial data packet converter is operable to convert parallel data from the bus system into bit serial packets for output through the port, and allocate a packet identifier to the bit serial packets in dependence on the information received from the bus system in accordance with a predetermined protocol. A method of effecting communication between a single chip integrated circuit device and an external device using such a parallel/serial data packet converter is also disclosed.

Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.