Abstract: A serial transceiver transmits at least one package of a data link layer and includes at least one channel including at least one transmitting module and at least one receiving module, a generating module and a controlling module. The channel is for transmitting the corresponding package. The transmitting module transmits the corresponding package and generates a transmitting time signal. The receiving module receives the package transmitted from the corresponding transmitting module and generates a receiving time signal. The generating module generates a target delay time signal. The controlling module receives the target delay time signal, transmitting time signals and receiving time signals, and generates a delay time signal for the corresponding receiving module according to the target delay time signal, the transmitting time signal and the receiving time signal.

Abstract: A data transfer control device includes: a link controller which analyzes a packet received through a serial bus; an interface circuit which generates interface signals and outputs the interface signals to an interface bus; and a reset signal output circuit which outputs a reset signal to the interface circuit. The link controller analyzes a packet to determine whether or not the received packet includes synchronization signal generation direction information (synchronization signal code). The reset signal output circuit outputs the reset signal to the interface circuit when the link controller has determined that the received packet includes the synchronization signal generation direction information.

Abstract: A bus device is used with a computer system. In the bus device, a bus-interfaced host performs data transmission in a first mode in response to a first command resulting from certain software execution of the computer system. A bridge device is coupled to and communicable with the bus-interfaced host via a first interface according to a first transmission protocol, and coupled to and communicable with the bus-interfaced device via a second interface according to a second transmission protocol. A bus-interfaced device performs data transmission in a second mode different from the first mode in response to a second command resulting from certain modification of the first command.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first serial protocol, and then transferred to the first port. Translations may be performed in response to information included in the headers of the received packets, including source ID values, destination ID values and/or case number values.

Abstract: Input-output circuitry for integrated circuits such as programmable logic device integrated circuits is provided. The input-output circuitry can be configured to operate in a single-ended data mode or a serializer-deserializer mode using programmable routing circuitry such as programmable multiplexers. In single-ended data mode, data registers in the single-ended input-output circuitry may be used to handle transmitted and received single-ended data. In serializer-deserializer mode, the data registers may be configured to form a shift register. The shift register may be used in a serializer-deserializer circuit. Parallel-to-serial and serial-to-parallel data conversion operations may be performed using the shift register. The serializer-deserializer circuit may be connected to differential input-output circuitry such as a differential transmitter circuit or a differential receiver circuit. The data registers may be configured to operate as positive-edge-triggered or negative-edge-triggered devices.

Abstract: A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.

Abstract: A universal cable interface and associated system and method are provided for coupling a transmission medium to a processing device. The universal cable interface can selectively operate in a first (input) mode and a second (output) mode. The universal cable interface can also handle different types of data, such as standard definition video data and high definition video data. When operating in the first mode, the universal cable interface may receive serial data over the transmission medium and convert the serial data into a parallel format for transmission to the processing device. When operating in the second mode, the universal cable interface may receive parallel data from the processing device and convert the parallel data into a serial format for transmission over the transmission medium.

Abstract: A single-wire communication bus couples a transmitting device to a UART in a receiving device. Flow control circuitry in the UART fills a transmit memory buffer with remote data. The UART supplies a remote start bit onto the single-wire bus for each byte of remote data written into the transmit memory buffer. After detecting a remote start bit on the single-wire bus, the transmitting device supplies initial data bits and a stop bit, which together form an RS232 character. Data flow is controlled when the UART supplies a subsequent remote start bit only after data has been read out of the UART freeing up bytes in a receive memory buffer. After the transmitting device detects the subsequent remote start bit, the transmitting device supplies subsequent data bits onto the single-wire bus. In another embodiment, flow control circuitry functionality is performed by flow control code in the receiving device operating system.

Abstract: A serial memory interface is described, including a memory array, a plurality of serial ports in data communication with the memory array, transferring data between the memory array and at least one of the plurality of serial ports, and a logic block that is configured to control access to the memory array by the plurality of serial ports, the logic block using the serial ports to transfer data between the memory array and at least one of the plurality of serial ports.

Abstract: Core clock alignment circuits include a serial-in parallel-out (SIPO) data processing circuit, which is configured to generate a plurality of lanes of deserialized data in response to a corresponding plurality of lanes of serialized data. The SIPO data processing circuit is further configured to generate a plurality of recovered clock signals from corresponding ones of the plurality of lanes of serialized data. These recovered clock signals may be out-of-phase relative to each other. The devices also include a plurality of lane FIFOs, which are configured to receive respective ones of the plurality of lanes of deserialized data and respective ones of the plurality of recovered clock signals at write ports thereof. A core clock alignment circuit is provided, which may be electrically coupled to the plurality of lane FIFOs.

Abstract: An information recording apparatus is disclosed, in which a HDD is connected to an ATA bus as a master device, an optical disk drive is connected as a slave device to a connector by an eSATA interface, and a system control unit asserts a PDAIG signal at the time of activating the information recording apparatus.

Abstract: Disclosed are a high speed serializing-deserializing system and a method thereof. The high speed serializing-deserializing system includes: a serializing unit including a plurality of serializers, generating a strobe signal, and multiplexing and converting N bits of parallel data into serial data; a transmission link transmitting the converted serial data and the strobe signal from the serializing unit; and a deserializing unit including a plurality of deserializers, and converting the serial data from the transmission link into the N bits of parallel data with the strobe signal from the transmission link. When serializing N bits of externally supplied parallel data with a rate of N:1, the N may be set to one of various integers. Although the N is extend to a large number such as 16, 32, and the like, the performance is not deteriorated and serialization-deserialization is possible.

Abstract: An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.

Abstract: The present invention provides a programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof. In an embodiment, the programmable modular circuit comprises a plurality of serial-to-parallel interface registers coupled together by a data line, a clock line, and an enable line. Each of the plurality of serial-to-parallel interface registers is coupled to a module of the system-on-a-chip. The data line and the clock line are used to serially clock data into the plurality of serial-to-parallel interface registers. Applying a first logical value to the enable line provides the data serially clocked into the plurality of serial-to-parallel interface registers to modules of the system-on-a-chip. Applying a second logical value to the enable line provides default values to modules of the system-on-a-chip.

Abstract: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Abstract: A system, method and apparatus for aligning data sequentially received on multiple single-byte data paths are provided. A sufficient number of bytes received in each channel may be stored (e.g., buffered) and examined to properly match data from each single-byte path. Once matched, the data may be output in a proper order on the multi-byte interface, for example, via some type of multiplexor arrangement. Furthermore, alignment operations may be performed in such a way so as to reduce the latencies involved in aligning data.

Abstract: The configuration of a system including a lot of receiving side devices can be simplified. The system includes a driver 10 and receivers 21 to 2N. The driver 10 and each of the receivers 21 to 2N are configured to be daisy chain connected, thereby performing data communication. The data communication is herein performed by serial communication. The driver 10 includes a PS/SP conversion 12, and transmits serial data obtained by conversion by the PS/SP conversion unit 12. Each of the receivers 21 to 2N includes a PS/SP conversion unit 33, and converts the received serial data to parallel data by the PS/SP conversion unit 33.

Abstract: A relay device and the like are provided which are capable of easily transmitting/receiving information among information processors connected on buses whose information transmission standards are different from each other. A bridge B1 for connecting buses BS1 and BS2 whose information transmission standards are different from each other includes: an operation unit (11) for performing an operation of instructing an operation of an apparatus connected to any of the buses BS; a message generator 5 for generating a control message corresponding to the instructed operation; and a packet transmitter/receiver (7, 8) for transmitting the generated control message to a target apparatus via the bus BS to which the target apparatus is connected.

Abstract: Methods, systems, and articles of manufacture for transferring control commands to a memory device. In one embodiment, the memory device comprises at least one serial command terminal with a downstream serial command decoder for receiving and decoding external command code as a serial bit sequence. Embodiments of the invention also disclose a memory controller comprising both a multiplicity of parallel command outputs and at least one serial command output for transmitting command code to the memory device as a serial bit sequence.

Abstract: An optical storage system for coupling to at least a plurality of peripheral devices. The optical storage system includes a data read subsystem to read out data stored in an optical storage medium, a data process subsystem to generate address information and data information according to the read out data, and an interface controller to generate output data according to the address information and the data information and to transfer the output data to one of the peripheral devices. A number of bits of the output data being transferred in parallel is configurable according to a parallel bit number. The data information and the address information are transferred via the same pins.

Abstract: A switch is coupled between a plurality of host units and a device for routing frame information therebetween. The switch includes a first serial advanced technology attachment (ATA) port including a first host task file that is responsive to a non-data frame information structure (FIS) from a first host unit. The switch further includes a second serial ATA port including a second host task file that is responsive to a non-data FIS from a second host unit. The switch further includes a third serial ATA port that is responsive to a non-data FIS from a device and further includes an arbitration and control circuit for selecting one of the first host or second host units to concurrently access the device, through the switch, by accepting non-data FIS, from either of the first or second host units, at any given time, including when the device is not in an idle state.

Abstract: A configuration of an electronic device (400) is managed by obtaining (1005) stakeholder attributes of a component resident in the electronic device from stakeholder requirements (FIGS. 7, 8) of one or more stakeholders and correlating (1020) the respective stakeholder attributes as well as available sets of values of attributes of the component to determine (1025) a set of selected values of the attributes, and establishing (1030) at least a portion of a new configuration of the electronic device using the set of selected values of the attributes of the component. When the stakeholder requirements cannot be met with an existing application in the electronic device, the application may be formed (1200) from components of existing applications.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: A system and method performs speed and connection handshaking between Beta signal ports and/or Bilingual ports in a serial data interface system. A tone pattern generator (e.g., a flip-flop) can be used to generate a tone pattern signal representing approximately 49 MHz to approximately 62 MHz. A selecting system (e.g., a multiplexer, a digital multiplexer, or the like) selectively transmits either the tone pattern signal or a data input signal. These signals include a driver control signal. A serializer serializes either the tone pattern signal or the data input signal. A clock device (e.g., a clock divider) drives the tone pattern generator and the serializer. A driver receives and differentially transmits, along a twister-wire pair, either the serialized tone pattern signal or the serialized data input signal.

Abstract: A signal converter includes an interconnect interface, a FIFO set, which comprises a transmitter FIFO and a receiver FIFO respectively connected to the interconnect interface through a data bus, a parallel/serial converter connected to the transmitter FIFO and the receiver FIFO by two data buses respectively and kept apart from the FIFO set, and a serial I/O interface connected to the parallel/serial converter.

Abstract: A hard disk drive is coupled to a plurality of host units for communication. The first host unit includes a serial advanced technology attachment (SATA) port, including a first host task file coupled for access to the device and responsive to commands sent by the first host unit. The second host unit includes a SATA port, including a second task file, coupled for access to the device and responsive to commands sent by the second host unit. An arbitration and control circuit is coupled to the first host task file and second task file. The arbitration and control circuit selects commands from one or the other host units when either host units sends a command for execution for concurrently accessing the device, and accepts commands from both, at any given time, including when the device is not idle.

Abstract: In accordance with the teachings described herein, systems and methods are provided for inserting 2-bit codes into the least significant bit positions of timing reference signal code words, to prevent long runs of zeros from entering the scrambling polynomial. By preventing the long runs of ones and zeros in the scrambled data stream, the receive-end DC-restoration circuits can be simplified, reducing complexity and increasing system performance. A serial digital interface prevents long runs of ones and zeros by replacing the values of the two least significant bits of the data stream prior to the scrambler. The two least significant bits are changed from 11b or 00b to 01b or 10b.

Abstract: A switch is coupled between a plurality of host units and a device, for communicating therebetween. A first serial advanced technology attachment (SATA) port includes a first host task file, and is coupled to a first host unit. A second SATA port includes a second host task file, and is coupled to a second host unit. The task files are responsive to commands sent by the respective host units, and cause access to the device by the host respective host units. A third parallel ATA port includes a device task file, and is coupled to a device, for access to the device by the first or second host units. An arbitration and control circuit is coupled to the task files, for selecting one of the first or second host units to concurrently access the device through the switch at any given time, including when the device is not idle.

Abstract: A switch is coupled between a plurality of host units and a device for communicating therebetween. Included is a first serial advanced technology attachment (SATA) port, a second SATA port, and a third SATA port. The first SATA port includes a first host task file coupled to a first host unit, and the first host task file is responsive to commands sent by the first host unit to the device. The second SATA port includes a second host task file coupled to a second host unit, and the second host task file is responsive to commands sent by the second host unit to the device. An arbitration control circuit is coupled to the SATA ports, and selects from the first and second hosts to concurrently access the device, through the switch, accepting commands from either host units at any time, including when the device is not idle.

Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Abstract: A switching control circuit includes a serial-to-parallel converter, a rewritable storage device, and a decoder. The serial-to-parallel converter performs serial-to-parallel conversion for converting an inputted first control signal into a first parallel signal, and outputs the first parallel signal. The rewritable storage device has a write mode and a read mode selectively switched over in response to a storage mode switching signal, stores therein data of the first parallel signal in the write mode, and outputs the stored data as a second parallel signal in the read mode. In the read mode, the decoder decodes the first control signal and the second parallel signal to generate and output a plurality of element control signals to a plurality of elements, respectively. In the write mode, the decoder holds the plurality of element control signals generated in the read mode.

Abstract: A system and method performs speed and connection handshaking between Beta signal ports and/or a Bilingual ports in a serial data interface system. A tone pattern generator (e.g., a flip-flop) can be used to generate a tone pattern signal representing approximately 49 MHz to approximately 62 MHz. A selecting system (e.g., a multiplexer, a digital multiplexer, or the like) selectively transmits either the tone pattern signal or a data input signal. These signals include a driver control signal. A serializer serializes either the tone pattern signal or the data input signal. A clock device (e.g., a clock divider) drives the tone pattern generator and the serializer. A driver receives and differentially transmits, along a twister-wire pair, either the serialized tone pattern signal or the serialized data input signal.

Abstract: A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.

Abstract: An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed.

Abstract: A data transfer control device including: a link controller which analyzes a packet received through a serial bus; a packet detection circuit which detects completion or start of packet reception based on analysis result of the received packet; first and second packet buffers into which the packet received through the serial bus is written; and a switch circuit which switches a write destination of the received packet. When a Kth packet has been written into one of the first and second packet buffers and completion of reception of the Kth packet or start of reception of a (K+1)th packet subsequent to the Kth packet has been detected, the switch circuit switching the write destination of the (K+1)th packet to the other of the first and second packet buffers.

Abstract: A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.

Abstract: Data transfer bus charging/discharging current is reduced in a semiconductor memory device. In a data transfer device that sequentially transfers bit sequences in parallel through a plurality of buses from a transmit unit 10 to a receive unit 20, the transmit circuit 10 includes a flag generation circuit 11 and an encoding circuit 12. The flag generation circuit 11 generates a flag indicating whether bit inversion has occurred in consecutive bits in each of the bit sequences to be transferred through the buses and transmits the generated flag to the receive unit 20. The encoding circuit 12 encodes the bit sequences based on the flag, for transmission to the receive unit 20. The receive unit includes a decoding circuit 21 that decodes the bit sequences based on the bit sequences and the flag.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: The present inventions relate to portable communication interface devices for communication and testing between a computer and electronic devices The portable communication interface device of one embodiment includes at least one specialized port, a standard port and a controller. Each specialized port is adapted to selectively communicate with an associated electronic device wherein each associated electronic device communicates by a unique device format. The standard port is adapted to selectively communicate with a computer wherein the computer is communicating by a computer format. The controller is coupled between the one or more specialized ports and the standard port. The controller is adapted to provide an interface between each unique device format and the computer format. The controller includes a data processor that is adapted to perform logic conversions.

Abstract: Methods, apparatus, and computer program products are described for resetting a HyperTransport link in a blade server, including reassigning, by a blade management module, a gate signal from enabling a transceiver to signaling a HyperTransport link reset; sending, by the blade management module to a reset sync module on an out-of-band bus, the gate signal; and in response to the gate signal, sending, by the reset sync module to the blade processor, HyperTransport reset signals. The HyperTransport link includes a bidirectional, serial/parallel, high-bandwidth, low-latency, point to point data communications link. The blade server includes the blade processor, the reset sync module, and the baseboard management controller. The blade server is installed in the blade center. The blade center includes the blade management module. The blade management module is coupled to the baseboard management controller by the blade communication bus.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received data item and for serializing the data item which is to be sent, having a second data interface for writing the parallelized data item to a memory arrangement via a memory data bus and for receiving the data item read from the memory arrangement via the memory data bus; having a write buffer storage for buffer-storing the data item which is to be written, having a control unit in order, after reception of a data item which is to be written via the first data interface in line with a write command, to interrupt the data from being written from the write buffer storage via the second data interface upon a subsequent read command.

Abstract: A flash-memory-card reader reads and writes multiple types of flash-memory cards, including CompactFlash, and the smaller SmartMedia, MultiMediaCard, Secure Digital, and Memory Stick. A converter chip converts the different card signals for transfer to a host personal computer (PC). Serial-to-parallel data conversion is performed for the smaller card formats with serial data interfaces, but not for CompactFlash with a parallel-data interface. A single slot has a 50-pin connector for CompactFlash cards or passive adapters. The passive adapters have the CompactFlash form factor and a smaller connector fitting smaller flash cards. Passive adapters have no components but simply wire the smaller connector to the CompactFlash connector. A pin mapping allows card-type detection by sensing the LSB address pins of the CompactFlash interface. A larger CompactFlash reader has multiple slots for each card type. The reader is connected to the PC by a cable, or located within the PC chassis in a drive bay.

Abstract: A serial buffer is provided having a parallel port configured to couple the serial buffer to a first system via a parallel interface protocol. The serial buffer also includes a serial port configured to couple the serial buffer to a second system via a serial interface protocol and control logic that enables data to be transferred between the parallel port and the serial port in an efficient manner. In one embodiment, the parallel interface protocol is substantially identical to a quad-data rate burst of two (QDRII-B2) interface protocol.

Abstract: A fibre channel switch element with an integrated fabric controller on a single chip is provided. The fabric controller including a processor module that can control various switch element functions; a serlizer/de-serializer for converting parallel data to serial data for transmission; an on-chip peripheral bus that allows communication between plural components and the processor module; a processor local bus and an interrupt controller that provides interrupts to the processor module. The integrated fabric controller also includes a flash controller and an external memory controller; an Ethernet controller; a Universal Asynchronous Receiver Transmitter (“UART”) module that performs serial to parallel conversion and vice-versa; an I2C module that performs serial to parallel and parallel to serial conversion; a general-purpose input/output interface; a real time clock module; an interrupt controller that can receive interrupts inputs from both internal and external sources; and a bridge to an internal PCI bus.

Abstract: A method and system for a programmable input/output transceiver is disclosed. A circuit in accordance with the invention includes a programmable transceiver. The programmable transceiver is configured and/or controlled to support an interface standard. A system according to the present invention includes a programmable transceiver and a field-programmable gate array (FPGA) core coupled to program the programmable transceiver.

Abstract: A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.

Abstract: A system and method to test a host bus adapter's (“HBAs”) ability to handle stream of invalid characters is provided. A data presenter module presents data to a HBA without being aware of a data format. A data producer module that is aware of the data format and schedules special characters so that the HBA can perform alignment operations. A bit offset change module changes a bit offset that is used by the data presenter module and causes to send random serial data to the HBA, which results in loss of alignment in the HBA and causes the HBA to decode invalid characters.