For Data Storage Device Patents (Class 710/74)
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Patent number: 9287022Abstract: A cable for providing electric power from a power source to a mobile device, the cable having a first connector at a first end of the cable for connecting the cable to a mobile device and with a second connector at a second end for connecting the cable to the power source, wherein the cable comprises a memory module for backup and bidirectional transfer of data to and from the mobile device.Type: GrantFiled: September 27, 2013Date of Patent: March 15, 2016Assignee: MEEM SL LimitedInventor: Anil Goel
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Patent number: 9251454Abstract: A storage medium including a first transmittal module and a control module. The first transmittal module includes a plurality of first transmittal pads. The control module determines whether a level state of the first transmittal module is equal to a pre-determined state. When the level state is equal to the pre-determined state, the control module operates in a secure digital (SD) mode. When the level state is not equal to the pre-determined state, the control module operates in an embedded multimedia card (eMMC) mode.Type: GrantFiled: October 24, 2012Date of Patent: February 2, 2016Assignee: Silicon Motion, Inc.Inventors: Hsu-Ping Ou, Chih-Yu Chen
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Patent number: 9244517Abstract: A dataset is identified as a heat-intensive dataset based, at least in part, on the dataset being related to heat generation at a source storage device exceeding a heat rise limit. The source storage device hosts the heat-intensive dataset and the heat-intensive dataset comprises non-executable data. A first cooling area of a plurality of cooling areas is selected to accommodate the heat generation based, at least in part, on cooling characteristics of a plurality of cooling appliances of the plurality of cooling areas. The source storage device is associated with a second cooling area. A target storage device associated with the first cooling area is determined. The heat-intensive dataset is moved from the source storage device to the target storage device.Type: GrantFiled: September 19, 2013Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Jay A. Athalye, Abhinay R. Nagpal, Sandeep R. Patil, Yan W. Stein
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Patent number: 9244877Abstract: A SATA-compatible storage controller that can be configured to allow computers assigned to multiple different computer domains connected by at least one switch fabric to share resources of a common set of storage devices. The storage controller includes a plurality of virtual storage controllers, each providing an interface to a respective computer domain connected to the switch fabric, a virtualization mechanism configured to implement link layer virtualization for the common set of storage devices, and a split serial advanced technology attachment (SATA) protocol stack, the processing of which is partitioned between the respective virtual storage controllers and the virtualization mechanism.Type: GrantFiled: March 14, 2013Date of Patent: January 26, 2016Assignee: Intel CorporationInventors: Chengda Yang, Bradley A. Burres, Amit Kumar, Matthew J. Adiletta
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Patent number: 9189383Abstract: A solid-state disk device exchanging data with a host includes a nonvolatile memory device, a buffer memory configured to temporarily store data exchanged between the host and the nonvolatile memory, and a buffer manager configured to control transfer of data to/from the buffer memory, wherein the transfer of data between the nonvolatile memory device and the host during a streaming mode of operation begins immediately when a defined unit data is input to the buffer memory.Type: GrantFiled: September 14, 2009Date of Patent: November 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Kwangseok Im, Bumseok Yu, Yeon Ju Jeong
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Patent number: 9158459Abstract: Methods, apparatuses, and computer program products for managing a storage device using a hybrid controller are provided where the storage device comprises an internal peripheral component interconnect express (PCIe) interface to control solid state memory within the storage device. In particular embodiments, the storage device includes a first external interface configured to establish an external PCIe link and a second external interface configured to establish at least one of an external serial attached small computer system interface (SAS) link and an external serial advanced technology attachment (SATA) link. Embodiments include receiving from an external source, by the hybrid controller, a first command at the first external interface and a second command at the second external interface; and concurrently implementing, by the hybrid controller, the first command using a PCIe protocol and the second command using one of a SAS protocol and a SATA protocol.Type: GrantFiled: March 5, 2012Date of Patent: October 13, 2015Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Gary D. Cudak, Christopher J. Hardee, Randall C. Humes, Adam Roberts
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Patent number: 9134781Abstract: The present invention discloses an inquiry system having a database and a first testing module as well as a memory unit, a second testing module and a maximum power efficiency control unit built in a power bank. In addition to the information exchange performed by the first testing module through an external computer, the built-in second testing can perform information exchange with a device to be charged (such as a handheld electronic device) directly. Meanwhile, the charging time of the power back can be reduced through the maximum power efficiency control unit.Type: GrantFiled: March 15, 2013Date of Patent: September 15, 2015Assignee: TENNRICH INTERNATIONAL CORP.Inventors: Shih-Hui Chen, Chin-Tien Lin
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Patent number: 9122806Abstract: A method and apparatus for providing a SATA host with access to multiple SATA drives is disclosed. The apparatus may include: an emulated port multiplier for presenting at least one logical drive to the SATA host; a mapping module for maintaining a mapping between the at least one logical drive and a plurality of physical SATA drives, wherein the plurality of physical SATA drives reside in a SAS topology; and a SATA/STP bridge for providing an interface between the SATA host and the SAS topology, the SATA/STP bridge configured to function as a SATA target to communicate with the SATA host and to function as a STP initiator to communicate with the plurality of physical SATA drives in the SAS topology.Type: GrantFiled: November 28, 2012Date of Patent: September 1, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: Vidyadhar C. Pinglikar
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Patent number: 9116624Abstract: Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof.Type: GrantFiled: March 4, 2014Date of Patent: August 25, 2015Assignee: Seagate Technology LLCInventors: Timothy Lawrence Canepa, Carlton Gene Amdahl
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Patent number: 9110592Abstract: A method of operating a computing device includes dynamically managing at least two types of memory based on workloads, or requests from different types of applications. A first type of memory may be high performance memory that may have a higher bandwidth, lower memory latency and/or lower power consumption than a second type of memory in the computing device. In an embodiment, the computing device includes a system on a chip (SoC) that includes Wide I/O DRAM positioned with one or more processor cores. A Low Power Double Data Rate 3 dynamic random access memory (LPDDR3 DRAM) memory is externally connected to the SoC or is an embedded part of the SoC. In embodiments, the computing device may be included in at least a cell phone, mobile device, embedded system, video game, media console, laptop computer, desktop computer, server and/or datacenter.Type: GrantFiled: February 4, 2013Date of Patent: August 18, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Brian Lee, Marc Tremblay, Barry Bond, Vlad Sadovsky, Mark John Ramberg
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Patent number: 9106674Abstract: The number of domain identifiers is incrementally increased for use by a switch in an established fiber channel switched fabric. In other words, the number of domains assigned to a switch by the Principal Switch of the fiber channel switched fabric is increased without triggering the reconfiguration of the established fiber channel switched fabric. In one implementation, incrementally adding one or more additional domain identifiers includes requesting said one or more additional domain identifiers from a Principal Switch of the fiber channel switched fabric using a different World Wide Name (WWN) than used to acquire the original one or more domain identifiers used by the switch.Type: GrantFiled: February 18, 2010Date of Patent: August 11, 2015Assignee: Cisco Technology, Inc.Inventors: Christian Sasso, Siddharth Kasat, Hari Balasubramanian, Ronak Desai
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Patent number: 9104338Abstract: A network storage includes at least one host device, a plurality of disk array devices, an address map that is stored in one of the plurality of disk array devices and indicates a correspondence relation between a logical address to view the plurality of disk array devices as one storage device and a physical address of each of the plurality of disk array devices, a management master that is included in the host device or one of the plurality of disk array devices, an address map storing location information that is stored in the management master and indicates the disk array device that stores the address map and an address on which the address map is stored in the disk array device, and a command management unit that is included in the management master and transmits the address map storing location information to the host device.Type: GrantFiled: October 8, 2009Date of Patent: August 11, 2015Assignee: NEC CorporationInventor: Masahiro Tamagawa
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Patent number: 9087210Abstract: A hijack-protected, secure storage device requires proof that the user has actual physical access to the device before protected commands are executed. Examples of protected commands include attempts to change storage device security credentials of the device, erasure of protected portions of the device, and attempts to format, sanitize, and trim the device. Various techniques for proving the actual physical possession include manipulating a magnet to control a magnetic reed switch located within the device, operating a momentary switch located within the device, altering light reaching a light sensor located within the device (such as by opening or shutting a laptop cover to change ambient light reaching the sensor), and manipulating a radio-transmitting device (such as a cell phone) near the storage device for detection of the manipulation by a compatible radio receiver located within the device.Type: GrantFiled: July 26, 2012Date of Patent: July 21, 2015Assignee: Seagate Technology LLCInventors: Leonid Baryudin, Timothy Joseph Markey, Dmitry Obukhov
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Patent number: 9081910Abstract: Methods and structure for enabling Fast Context Switching (FCS) among a plurality of FCS enhanced Serial Attached SCSI (SAS) expanders of a SAS domain. The FCS enhanced SAS expander is further adapted to detect completion of utilization of the first connection that utilizes an upstream PHY and a downstream PHY of the expander. The expander is further adapted, responsive to detecting completion, to determine whether a second connection between the initiator device and a second target device could be established utilizing the existing coupling between the upstream PHY and the downstream PHY. The expander de-couples the upstream PHY from the downstream PHY within the expander in response to determining that the second connection does not utilize the existing coupling and maintains the existing coupling in response to determining that the second connection utilizes the coupling between the upstream PHY and the downstream PHY.Type: GrantFiled: February 12, 2013Date of Patent: July 14, 2015Assignee: Avago Technologies General IP (Singapore) Pte LtdInventors: Nishant Kumar Yadav, Ankit Goel, Anjali Yadav
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Patent number: 9047188Abstract: In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO buffers data coming from the L1 FIFO, reducing the polling time for received data. Status is always checked for errors before processing the data and updating the state variables. Implementing a state machine to perform some of the checks results in a PRU utilization that is not a function of the bytes that need to be processed.Type: GrantFiled: October 4, 2013Date of Patent: June 2, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Pratheesh Gangadhar Thalakkal Kottilaveedu, Kanad D. Kanhere
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Publication number: 20150149669Abstract: The present disclosure relates to a method for enhancement of media experience that comprises transmitting, by a first computing device, a data stream stored in a first storage region of the first computing device to an output device connected to the first computing device, providing, by a trigger module, a trigger that is linked to the data stream, detecting, by a detection module, the trigger while the data stream is being transmitted, and providing, by a content module, additional data in response to detecting the trigger. Furthermore, a system for enhancement of media experience is described.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Inventor: Cevat Yerli
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Patent number: 9043518Abstract: Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.Type: GrantFiled: January 27, 2014Date of Patent: May 26, 2015Assignee: Micron Technology, Inc.Inventor: Terry M. Grunzke
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Publication number: 20150143001Abstract: An Enterprise Service Bus (ESB) system includes a shared storage that stores data corresponding to files, a file system, and ESB infrastructure functions. The ESB system includes a metadata registry storing metadata associated with the ESB infrastructure functions, separate from the ESB infrastructure functions, and includes storage location information of the ESB infrastructure functions. The ESB system includes a processor configured to receive a request for access to the file system. The processor sends a portion of the metadata registry to a client device, the portion including a portion of the metadata and a directory structure identifying a set of the ESB infrastructure functions that the client device is authorized to access, the portion of the metadata allowing the client device to access a first infrastructure function of the set based on the storage location information. The processor further provides the first infrastructure function to the client device.Type: ApplicationFiled: January 5, 2015Publication date: May 21, 2015Inventors: Dennis L. Kuehn, David D. Bettger, Kevin A. Stone, Marc A. Peters
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Publication number: 20150143002Abstract: A computer system includes a first storage control module and at least one server module. The first storage control module includes plural storage processors. Each server module includes a server processor and a server I/F connected to the server processor and at least two of the plurality of storage processors. The sever I/F of an issuance server which is any one of the at least one server module specifies the storage processor by referring to sorting information in which identification information of the issuance server of an I/O request issued by the server processor of the issuance server, identification information of a destination storage area of the I/O request, and identification information of the storage processor in charge of the destination storage area are correlated with each other, and sends a command based on the I/O request to the specified storage processor.Type: ApplicationFiled: January 29, 2015Publication date: May 21, 2015Inventors: Nobuhiro YOKOI, Mutsumi HOSOYA, Kazushi NAKAGAWA
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Publication number: 20150143000Abstract: A storage control method is characterized by receiving a write signal from an external transmission source, transmitting write data included in the write signal to a transmission destination, storing the write data temporarily, monitoring a temporary stored data amount that is an amount of the write data temporarily stored, transmitting a control signal, based on a result of the monitoring, to the transmission source which performs execution of the first processing, selecting second processing, based on the control signal, which is subject to be suppression of the execution from among the first processing according to a predetermined condition, outputting a suppression signal which suppresses the second processing, and suppressing execution of the second processing based on the suppression signal.Type: ApplicationFiled: November 10, 2014Publication date: May 21, 2015Inventor: Masumi TAKIYANAGI
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Publication number: 20150142999Abstract: The present invention relates to migrating volumes among computers in a computer system. According to the migration method of the present invention, a setting of a storage apparatus is changed so that the volume having been used by the migration source host is accessible by the migration destination host, and then a volume recognition process is performed in the migration destination host. As a result of the volume recognition process, if it is detected in the migration destination host that multiple device files are created in a duplicated manner with respect to a single volume provided by the storage apparatus, the migration destination host deletes the device files created in a duplicated manner leaving one device file.Type: ApplicationFiled: November 5, 2013Publication date: May 21, 2015Applicant: HITACHI, LTD.Inventors: Kenji Ozoe, Taro Ishizaki, Takeshi Nishikawa
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Patent number: 9037764Abstract: A controller and a method for interfacing between a host and storage medium. A storage medium interface includes CH0 circuitry for performing a CH0 process to access a buffer memory on behalf of the storage medium. A host interface includes CH1 circuitry for performing a CH1 process to access the buffer memory on behalf of the host. Access to the buffer memory is arbitrated in sequential tenures to each channel of the multi-channel bus within a maximum arbitration round trip time defined by the time taken by the storage medium to move a distance corresponding to N sectors in which N is greater than one. In the CH0 tenure, the CH0 process transfers data corresponding to N sectors of the storage medium in a multi-sector burst. The length of the tenure of the CH0 channel is pre-designated so that the multi-sector burst is completed within the CH0 tenure.Type: GrantFiled: October 21, 2013Date of Patent: May 19, 2015Assignee: Marvell International Ltd.Inventors: Theodore C. White, Stanley K. Cheong, Lim Hudiono, William W. Dennin, III, Chau Tran
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Publication number: 20150134861Abstract: Disclosed herein are a personal cloud storage chain service system and method which are capable of solving the shortage problem of personal cloud storage by connecting surplus storages, used by each person, to a Digital Media Player (DMP) (e.g., a SetTopBox (STB)) and storing and managing content. A personal cloud storage chain service system according to an embodiment of the present disclosure includes one or more storages configured to include a surplus storage space and be detachable and a DMP configured to issue and store respective signatures for identifying the respective storages when the one or more storages are connected and to store and manage basic information about contents stored in the one or more storages.Type: ApplicationFiled: October 3, 2014Publication date: May 14, 2015Inventor: Ki Yong PARK
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Patent number: 9026690Abstract: A display device as in one aspect of the present disclosure includes a display panel, a case, a connection receiving portion, a connection determination portion, and a display processing portion. The display panel displays an image. The case supports a display surface of the display panel so as to be viewable from the exterior. The connection receiving portion is provided to a side surface of the case, and electrically connects to an external storage device. The connection determination portion determines whether or not the external storage device has been connected to the connection receiving portion. The display processing portion displays, on the display panel, a connection portion image indicative of a connection portion of the connected external storage device in a case where the external storage device has been determined by the connection determination portion to have been connected.Type: GrantFiled: April 18, 2013Date of Patent: May 5, 2015Assignee: KYOCERA Document Solutions Inc.Inventor: Dai Shigenobu
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Publication number: 20150120969Abstract: Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory.Type: ApplicationFiled: December 11, 2014Publication date: April 30, 2015Inventors: Jian HE, Guangyu SHI, Xiaoke NI, Norbert EGI, Xiancai LI, Yu LIU, Huawei LIU
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Publication number: 20150120968Abstract: A control method for an information processing system including a first computer, a second computer, and a plurality of storage devices coupled to the first computer and the second computer through a switch, a processing performance of the second computer being higher than a processing performance of the first computer, the control method includes setting, by the switch, the first computer as a target for connection of the plurality of storage devices; transmitting, by the first computer, data to be processed from the first computer to the plurality of storage devices and thereby storing the data in the plurality of storage devices; switching, by the switch, the target from the first computer to the second computer when the storing is completed; and executing, by the second computer, processing of the data stored in the plurality of storage devices.Type: ApplicationFiled: September 5, 2014Publication date: April 30, 2015Applicant: Fujitsu LimitedInventor: Takatsugu Ono
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Patent number: 9021166Abstract: A system and method for servers to belong to a cascaded cluster of nodes (or servers) is disclosed. Servers share storage in common without the need of an external element such as a switch and or external storage device. SAS technology is used with direct attached drives in each node, and connections between each node, to emulate a SAN environment through a cascaded SAS topology. SAS HBAs each containing an SAS expander, connect elements internal to each server with elements external to each. This cascaded DAS clustering enables bi-directional traffic from each server in the cluster to all other servers and their attached drives.Type: GrantFiled: July 17, 2012Date of Patent: April 28, 2015Assignee: LSI CorporationInventors: Luiz D. Varchavtchik, Reid A. Kaufmann, Jason A. Unrein
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Publication number: 20150113183Abstract: Host port information is pulled directly from the switch before zoning is performed and is organized by chassis as an assist for mapping and masking an entire chassis. A graphical user interface allows a user to select storage by chassis to map and to select servers by chassis to map. The user then applies that mapping such that all servers selected are mapped to all storage selected. The user may repeat this mapping for another set of storage and servers. In a mixed environment, an icon may be shown in the graphical user interface to represent the mix. When the LUN mapping/masking is done, the LUN mapping/masking may be provided to the SAN manager to perform zoning. The LUN mapping/masking defines which host ports see which storage ports.Type: ApplicationFiled: December 23, 2014Publication date: April 23, 2015Inventors: Robert B. Basham, Deanna L.Q. Brown, Kelly L. Hicks, Andrew G. Hourselt, Rezaul S.M. Islam, Ashaki A. Ricketts, Teresa S. Swingler, Theodore B. Vojnovich
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Publication number: 20150113176Abstract: An adapter device is provided that is configured to interface with a host device according to a first communication standard via a first connector and with a transceiver module according to a second communication standard via a second connector. The adapter device detects that the transceiver module has connected to the adapter device. The adapter device retrieves transceiver module identifier information from the transceiver module and converts the transceiver module identifier information to the first communication standard. The converted transceiver module identifier information and adapter device identifier information are sent to the host device.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: Cisco Technology, Inc.Inventors: Norman Tang, Jose Carlos Raygoza Echeagaray, Liang Ping Peng, David Lai, Anthony Nguyen
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Publication number: 20150113182Abstract: Systems and methods for providing accelerated data storage and retrieval utilizing lossless and/or lossy data compression and decompression. A data storage accelerator includes one or a plurality of high speed data compression encoders that are configured to simultaneously or sequentially losslessly or lossy compress data at a rate equivalent to or faster than the transmission rate of an input data stream. The compressed data is subsequently stored in a target memory or other storage device whose input data storage bandwidth is lower than the original input data stream bandwidth. Similarly, a data retrieval accelerator includes one or a plurality of high speed data decompression decoders that are configured to simultaneously or sequentially losslessly or lossy decompress data at a rate equivalent to or faster than the input data stream from the target memory or storage device. The decompressed data is then output at rate data that is greater than the output rate from the target memory or data storage device.Type: ApplicationFiled: June 16, 2014Publication date: April 23, 2015Applicant: Realtime Data LLC dba IXOInventor: James J. FALLON
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Patent number: 9015373Abstract: A storage apparatus capable of achieving both an improvement in efficiency of data transfer processing and an improvement in availability and a method of controlling the storage apparatus are provided.Type: GrantFiled: May 17, 2012Date of Patent: April 21, 2015Assignee: Hitachi, Ltd.Inventor: Makoto Deguchi
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Patent number: 9015391Abstract: A method for dispatching of service requests in a redundant storage virtualization subsystem including a plurality of storage virtualization controllers is disclosed. The method comprises the steps of the host entity issuing a first service request to a first one of the SVCs; the first SVC handling the first service request, acquiring a first result of servicing the first service request, and returning the first result to the host entity the result; and, the host entity issuing a second service request to a second one of the SVCs; and, the second SVC handling the second service request, acquiring a second result of servicing the second service request, and returning the second result to the host entity the result. A storage virtualization subsystem implementing the method, a computer system comprising such storage virtualization subsystem, and a storage media having machine-executable codes stored therein for performing the method are also disclosed.Type: GrantFiled: March 29, 2005Date of Patent: April 21, 2015Assignee: Infortrend Technology, Inc.Inventors: Michael Gordon Schnapp, Chih-Chung Chan
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Publication number: 20150106538Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.Type: ApplicationFiled: October 16, 2013Publication date: April 16, 2015Applicant: QUALCOMM IncorporatedInventors: Narasimhan Vasudevan, Li Pan, Michael Thomas Fertsch, Nan Chen
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Patent number: 9009376Abstract: A BIOS storage unit of an electronic device is connected to a USB 3.0 extension unit of a USB 3.0 host connector. A microcomputer of a USB compatible device is connected to a USB 3.0 extension unit of a USB 3.0 device connector. The microcomputer of the USB compatible device can write and read the BIOS data to/from the BIOS storage unit of the electronic device through the USB 3.0 extension units. Moreover, the microcomputer of the USB compatible device compares the BIOS data read from the BIOS storage unit of the electronic device with the BIOS data stored in its own storage unit, and notifies a result of the comparison.Type: GrantFiled: July 27, 2012Date of Patent: April 14, 2015Assignee: Sharp Kabushiki KaishaInventor: Tatsuaki Amemura
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Patent number: 9009375Abstract: A first I/O transaction request is sent to a storage controller for processing by firmware running on the storage controller. A second I/O transaction request is sent to storage hardware without further processing by the firmware running on the storage controller. Since the firmware did not process the second I/O transaction request, information associated with the second I/O transaction is stored in in a circular buffer accessible to the firmware running on the storage controller. The firmware running on the storage controller reads, from the circular buffer, the information associated with the second I/O transaction that was stored in the circular buffer.Type: GrantFiled: June 26, 2013Date of Patent: April 14, 2015Assignee: LSI CorporationInventors: Gerald E. Smith, James A. Rizzo, Robert L. Sheffield, Anant Baderdinni
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Publication number: 20150100710Abstract: An example of an information processing system includes first storage means for storing saved data of an application and a second storage means. The information processing system, every time saved data is updated, stores, in the first storage means and the second storage means, identification information indicating the updated saved data. Further, the information processing system, every time saved data is updated, stores, in at least one of the first storage means and the second storage means, the identification information corresponding to the saved data before being updated. Use of the saved data stored in the first storage means is allowed at least under the condition that the identification information indicating the same saved data is stored in the first storage means and the second storage means.Type: ApplicationFiled: September 16, 2014Publication date: April 9, 2015Inventors: Akira KINASHI, Hironori ICHIBAYASHI
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Patent number: 9003087Abstract: A shared device unit, which comprises a storage device, is coupled to a plurality of storage systems. The shared device unit provides a plurality of storage areas, which are based on the storage device, to the plurality of storage systems. Each storage system stores allocation management information which comprises an ID of a storage area provided to thereof among the plurality of storage areas, and provides the storage area corresponded to the ID included in the allocation management information to the host computer coupled thereto among the plurality of host computers.Type: GrantFiled: March 18, 2013Date of Patent: April 7, 2015Assignee: Hitachi, Ltd.Inventors: Miho Imazaki, Shigeo Homma, Hiroaki Akutsu, Yoshiaki Eguchi, Akira Yamamoto, Junji Ogawa
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Publication number: 20150095520Abstract: A semiconductor memory apparatus includes an input data bus inversion unit, a data input line, a termination unit, a data recovery unit and a memory bank. The input data bus inversion unit determines whether or not to invert a plurality of input data based on an operation mode signal and the plurality of input data and generates a plurality of conversion data. The data input line transmits the plurality of conversion data. The termination unit terminates the data input line in response to the operation mode signal. The data recovery unit receives the plurality of conversion data and generates a plurality of storage data. The memory bank configured to store the plurality of storage data.Type: ApplicationFiled: January 6, 2014Publication date: April 2, 2015Applicant: SK hynix Inc.Inventor: Seung Wook KWACK
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Publication number: 20150095529Abstract: A method, device and machine-readable storage device for transferring data between identity modules is disclosed. Data is stored in one of a first removable storage module coupled to a donor communication device and a memory of the donor communication device, or both. A first portion of the data is provided to a server. The server provides the first portion of the data to a second removable storage module coupled to a recipient communication device responsive to a determination that a recipient communication device has a right to the data. Additional embodiments are disclosed.Type: ApplicationFiled: December 11, 2014Publication date: April 2, 2015Inventors: Kelley Casimere, Gail A. Churillo, Susanne M. Crockett, Liaqat Ali, Patricia M. Thatcher
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Publication number: 20150095528Abstract: An allocation instruction is received that includes a target data operand and a storage medium operand indicating a storage medium for storing the target data. A data dependency is identified that specifies peripheral data on which the target data depends. In response to determining that the allocation instruction will cause the target data and the peripheral data to locate to different storage mediums having different data IO rates, the execution of the allocation instruction is prevented. In another embodiment, in response to determining that the allocation instruction allocates the target data from a first storage medium to a second storage medium having a faster data IO rate, the allocation instruction is modified to also allocate the peripheral data specified in the data dependency to the second storage medium.Type: ApplicationFiled: September 17, 2014Publication date: April 2, 2015Inventors: Meng Gao, Yang Liu, Mei Mei, Jie Ping Wu
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Patent number: 8996768Abstract: A method and storage device for assessing execution of trim commands are provided. In one embodiment, a trace of trim and write commands sent to a storage device are obtained. For each trim command in the trace, a subsequent write command to a same logical block address (LBA) as the trim command is identified, and an elapsed time between the trim and write commands is calculated. This information can be used to display a histogram and/or to optimize when the storage device executes trim commands and/or when the host device issues trim commands.Type: GrantFiled: June 15, 2012Date of Patent: March 31, 2015Assignee: SanDisk Technologies Inc.Inventors: Oren Cohen, Eyal Sobol, Omer Gilad, Judah G. Hahn
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Patent number: 8996769Abstract: Technology is provided for selecting a master node of a node group in a storage system. The technology can gather data regarding visibility of one or more storage devices of the storage system to one or more active nodes of the node group, determine a maximum visibility value for the node group and selecting an active node with associated visibility value equal to the maximum visibility value as the master node of the node group.Type: GrantFiled: August 6, 2013Date of Patent: March 31, 2015Assignee: NetApp, Inc.Inventors: Radek Aster, Mayank Saxena
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Patent number: 8990463Abstract: Transferring storage device functionality includes providing a device coupled to the storage device, where the device is separate from the storage device, having the device handle I/O requests between an application and the storage device, and, in response to the application issuing an I/O request, having the device determine if the request corresponds to functionality being transferred and, if so, having the device provide the functionality. The device may be a host computer. The application may run on the host computer. A driver on the host computer may provide the functionality. The functionality may include read only functionality, data compression, data encryption, mirroring, and/or status reporting.Type: GrantFiled: December 24, 2013Date of Patent: March 24, 2015Assignee: EMC CorporationInventors: Douglas E. LeCrone, Paul A. Linstead, Denis J. Burt
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Patent number: 8990461Abstract: The present invention generally relates to the management of a configuration of a first device. The first device includes a control unit and an interface unit managing a communication interface. The communication interface comprises at least one resistive line having a resistance value. The resistance value allows the interface unit to identify a configuration for at least one second device adapted to be linked to the first device via the communication interface. The interface unit: /a/ detects a change of the resistance value on the resistive line corresponding to a configuration of said second device; /b/ processes said change of the resistance value to adapt the configuration of the first device according to the configuration of said second device.Type: GrantFiled: August 25, 2010Date of Patent: March 24, 2015Assignee: St-Ericsson SAInventors: Nathalie Ballot, Nicholas Florenchie
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Patent number: 8984172Abstract: An apparent load is determined based on assigning weightings to commands based on various factors including, but not limited to, the limitations of the underlying storage media device(s), where the command queue fullness is viewed from that perspective rather than simply the number of commands outstanding in a storage media device. Also disclosed is the use of a positive bias and a negative bias to artificially influence the apparent load based on fill percentages of storage media devices.Type: GrantFiled: December 6, 2013Date of Patent: March 17, 2015Assignee: Concurrent Ventures, LLCInventors: Jesse D. Beeson, Jesse B. Yates
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Patent number: 8984185Abstract: The present invention relates to a computing arrangement (10), said computing arrangement (10) comprising a computer device (11), multiple input- and/or output-devices (14, 15, 17, 19, 21, 22) attached to said computer device (11). In order to allow the parallel usage of multiple input- and/or output-devices which are attached to a computer device as peripheral devices, the computing arrangement (10) is characterized by a control device (20) for associating said multiple input- and/or output devices (14, 15, 17, 19, 21, 22) to at least two different GUI (Graphical User Interface) instances.Type: GrantFiled: August 30, 2010Date of Patent: March 17, 2015Assignee: Vodafone GmbHInventors: Thomas Lang, Martin Orehek
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Patent number: 8984189Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.Type: GrantFiled: May 1, 2012Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
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Patent number: 8984190Abstract: A data storage device may comprise data storage comprising a first logical unit configured to store user data and a second logical unit configured to store an operating system. A first interface may be configured to couple to a host and a second interface may be configured to couple to a network. In a first mode, the data storage device may be configured to expose the first logical unit to the host and render the second logical unit inaccessible and, in a second mode, the data storage device may be configured to allow access to both the first and the second logical units. The first mode may comprise a direct attached storage (DAS) mode and the second mode may comprise a network attached storage (NAS) mode.Type: GrantFiled: June 29, 2013Date of Patent: March 17, 2015Assignee: Western Digital Technologies, Inc.Inventor: James S. Lin
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Patent number: 8984176Abstract: In one embodiment, a computer system comprises one or more processors, a circuit board assembly having at least one SATA port, a general purpose input/output port proximate the SATA port, signal generating logic to generate a signal when the general purpose input/output port is coupled to a connector, and a memory module communicatively connected to the one or more processors and comprising logic instructions stored in a computer readable medium which, when executed on the one or more processors, configure the one or more processors to configure the SATA port according to the signal generated by the signal generating circuitry.Type: GrantFiled: October 31, 2008Date of Patent: March 17, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christopher Rijken, Juan Martinez, Shan Chen, Peter W. Austin, Chi W. So
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Publication number: 20150074299Abstract: Computer system providing to a host computer a virtual logical volume that is associated with a logical pool configured from storage areas respectively provided by first and second storage apparatuses, and dynamically assigns a storage area from the logical volume to the virtual logical volume, a host computer and the first storage apparatus are connected via a first path configuring an access path, and, when a ratio of an access volume used by a second path connecting the first and second storage apparatuses exceeds a predetermined ratio, it is determined that a problem with the access path from the host computer to virtual logical volume, a third path connecting the host computer and the second storage apparatus is identified as a change destination of the access path, and the identified third path is changed to a part of the access path from the host computer to the virtual logical volume.Type: ApplicationFiled: September 26, 2012Publication date: March 12, 2015Applicant: Hitachi, Ltd.Inventors: Naoshi Maniwa, Takato Kusama