Abstract: Methods, systems, and devices for reconfigurable channel interfaces for memory devices are described. A memory device may be split into multiple logical channels, where each logical channel is associated with a memory array and a command/address (CA) interface. In some cases, the memory device may configure a first CA interface associated with a first channel to forward commands to a first memory array associated with the first channel and a second memory array associated with a second channel. The configuring may include isolating a second CA interface associated with the second channel from the second array and coupling the first CA interface with the second memory array.

Abstract: A power management circuit includes at least one energy storage device and a power controller coupled to the at least one energy storage device. The power controller is configured to enable temporary power to be provided from the at least one energy storage device to a plurality of data storage devices upon a system power loss event. The power controller is further configured to receive a power loss indication signal associated with any individual one of the plurality of data storage devices and responsively enable power loss protection for the data storage device.

Abstract: There are provided a memory controller, a memory system having the memory controller, and an operating method of the memory controller. The memory controller includes a status check command determining section for checking a status check command supported by a memory device among a plurality of status check commands, and a status check performing section for performing a status check operation on the memory device by using the checked status check command.

Abstract: An apparatus has magnetic logic units a logic circuit configured to receive a serial input bit stream at an input node. Individual bits of data from the serial input bit stream are serially written into individual magnetic logic units without buffering the serial input bit stream between the input node and the individual magnetic logic units. Individual bits of data from individual magnetic logic units are serially read to produce a serial output bit stream on an output node without buffering the serial output bit stream between the individual magnetic logic units and the output node.

Abstract: A method for managing a data item includes a hub receiving a first access request from a first engine executing on a computing device operated by a first host and sending the first access request to a second engine executing on a first computing device of a second host. The second host owns the data item. The hub receives, from the second engine, the data item and an access rule set by the second host for the first host, and sends the first access rule and the data item to the first engine for storage. The first engine grants the first host access to the data item according to the first access rule.

Abstract: An information processing apparatus has a task area unit as an area that executes a predetermined process, a power control unit that reads a task area to execute the process from the process and supplies power from a power source to the read task area, and a control unit that executes the process in the task area unit to which the power is supplied by the power control unit.

Abstract: A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

Abstract: An apparatus includes a first Universal Serial Bus (USB) connector and a card holder associated with the first USB connector. A controller including a USB host interface is coupled to the first USB connector. A housing enclosing the controller and at least partially enclosing the card holder has an opening that is dimensioned to enable insertion of a memory card into the card holder. The first USB connector is configured to connect to a second USB connector of the memory card when the memory card is inserted into the card holder.

Abstract: A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

Abstract: A method for data management in a flash memory medium is provided in the present invention, The method comprises the following steps: dividing a plurality of blocks of the flash memory medium into two or more sections; generating a section-address-mapping table by scanning logic addresses in the blocks in each section; storing the section-address-mapping table into a backup block in each section; and performing an operation of writing/reading by reading the section-address-mapping table, storing the section-address-mapping table to a RAM, and performing a conversion between a physical address and a logic address based on the section-address-mapping table stored in the RAM.

Abstract: To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used. The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

Abstract: A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.

Abstract: According to an embodiment, the present invention provides a computer-readable storage medium comprising processor executable codes. The computer-readable storage medium includes code for receiving information from a client entity at a server entity over a network. The computer-readable storage medium includes code for providing a server process at the service, the server process including one or more process threads. The computer-readable storage medium includes code for providing a first context associated the one or more process threads. The computer-readable storage medium includes code for receiving a user request from the client entity for a user thread, the user thread being associated with the service process. The computer-readable storage medium includes code for generating the user thread at the server entity.

Abstract: A memory device includes a memory unit that is nonvolatile and is made up of a plurality of memory areas; first retaining units each of which is provided in correspondence with a different one of the memory areas and each of which retains first setting information that defines whether a corresponding one of the memory areas is in an active state or a stop state; and an electric power-source controlling unit that supplies electric power to one or more of the memory areas that correspond to the first setting information defining the memory areas to be in the active state, and stops electric power supply to one or more of the memory areas that correspond to the first setting information defining the memory areas to be in the stop state.

Abstract: A computer system with an addressable medium is disclosed. The computer system comprises an addressable medium subsystem, a microprocessor and at least one input/output device. The addressable medium subsystem includes: a control logic which has a control circuit with an address table for storing a plurality of addresses, and an access logic with a storage medium layer and an electromagnetic induction circuit. The electromagnetic induction circuit includes a plurality of coils and a plurality of rods. Each rod is surrounded by one of the coils and corresponds to one of a plurality of regions on the storage medium layer. The access logic controls the coils to access the data stored on the regions for the control logic. Each region corresponds to one of the addresses on the address table. The microprocessor and the input/output device electrically couple with the control logic. Both the microprocessor accesses instructions for executing and the input/output device accesses data via the control logic.

Abstract: A memory system of the present invention includes a memory device having a nonvolatile memory and an access device which accesses the memory device. The memory device has a detection unit to detect a temperature of the memory device, a determination unit to determine an operating condition in accordance with the detected temperature and a notification unit to notify the access device of the determined operating condition. The access device has an interface unit to connect to the memory device and a controlling unit to control the interface unit in accordance with the notified operating condition from the memory device.

Abstract: An architecture for an improved non-volatile memory device supporting multiple memory interface options is disclosed herein. In one embodiment, the improved memory device includes a magnetic random access memory (MRAM) array and at least one memory interface block, which is configured for accessing a different type of memory array other than the MRAM array. A smart MRAM interface block is also included and coupled between the plurality of memory interface blocks and the MRAM array. The smart MRAM array is configured for accessing the MRAM array using commands intended for the MRAM array, as well as commands intended for the different type of memory array. A method for operating the improved non-volatile memory device is also disclosed herein.

Abstract: A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient time available to perform the requested operation. If there is sufficient time available and the device manager is in an exclusive mode, the state of the memory device is checked to determine if it is currently executing an operation. If so, this operation is suspended and the requested operation is issued to the memory device. The device manager polls the memory device to determine when the requested operation has been completed. Upon completion, the interrupts are re-enabled and control of the memory device is returned to the system.

Abstract: A nonvolatile memory may include a plurality of blocks as a unit for performing writing and erasing of data which is stored in the respective blocks. The block may include a write data area in which data is written and stored, a correlative code area in which a correlative code indicating a correlation between the data which are written in the respective write data areas of the respective blocks is stored, and an inspection data area in which inspection data required in inspection is stored in the respective blocks for inspecting the validity of the data.

Abstract: A destructive-read memory is one that the process of reading the memory causes the contents of the memory to be destroyed. Such a memory may be used in devices that are intended to acquire data that may have associated usage restrictions, such as an expiration date, usage count limit, or data access fee for the acquired data. Typically, to enforce usage restrictions, and protect against theft, complex and often costly security techniques are applied to acquired data. With destructive-read memory, complex and costly security is not required for stored data. In one embodiment, a write-back mechanism, which may employ security, is responsible for enforcing usage restrictions. If the write-back mechanism determines continued access to acquired data is allowed, then it writes back the data as it is destructively read from the memory.

Abstract: A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient time available to perform the requested operation. If there is sufficient time available and the device manager is in an exclusive mode, the state of the memory device is checked to determine if it is currently executing an operation. If so, this operation is suspended and the requested operation is issued to the memory device. The device manager polls the memory device to determine when the requested operation has been completed. Upon completion, the interrupts are re-enabled and control of the memory device is returned to the system.

Abstract: A configuration and a method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory utilize the imprint effect for increasing the remanent polarization or remanent magnetization of a material having a hysteresis property. The remanent polarization or magnetization is increased by writing a memory content a number of times to the same memory cells.

Abstract: Load balancing of activities on physical disk storage devices is accomplished by monitoring reading and writing operations to blocks of contiguous storage locations on the physical disk storage devices. A list of exchangeable pairs of blocks is developed based on size and function. Statistics accumulated over an interval are then used to obtain access activity values for each block and each physical disk drive. These activities are represented as disk seek, latency and data transfer times. A statistical analysis leads to a selection of one block pair. After testing to determine any adverse effect of making that change, the exchange is made to more evenly distribute the loading on individual physical disk storage devices.

Abstract: A computer system using non-volatile main memory in lieu of random access memory (RAM). The non-volatile main memory stores operating system software and application software used by the central processing unit (CPU) when the computer system is operating after bootup. The operating system and application software used by the computer after bootup are retained in an initialized and executable state within the non-volatile main memory when the computer is powered off. As a result, the time to bootup the computer is reduced because the operating system and application software do not need to be copied into a memory element (e.g., RAM) and initialized into an executable state. Also, applications can be opened more quickly during normal operation, and the computer can be shut down more quickly. Performance of the computer can also be improved by using non-volatile memory for the secondary level memory cache and/or the CPU registers.

Abstract: Load balancing of activities on physical disk storage devices is accomplished by monitoring reading and writing operations to blocks of contiguous storage locations on the physical disk storage devices. A list of exchangeable pairs of blocks is developed based on size and function. Statistics accumulated over an interval are then used to obtain access activity values for each block and each physical disk drive. These activities are represented as disk seek, latency and data transfer times. A statistical analysis leads to a selection of one block pair. After testing to determine any adverse effect of making that change, the exchange is made to more evenly distribute the loading on individual physical disk storage devices.

Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

Abstract: A system and method for determining the disk drive parameters of any disk drive that may be encountered. A novel access pattern is applied to the disk drive and a novel technique used to interpret the measured results. In order to determine a data layout geometry of a disk drive, a plurality of sectors on the disk drive are accessed in sequentially decreasing order, starting from an initial sector. A completion time for each access is measured and parameters related to the data layout geometry of the disk drive are determined based on the measured access times. In order to determine the layout geometry, sectors immediately preceding track and cylinder skews are identified and a number of sectors per track and a number of tracks per cylinder are determined based on the identified sectors.

Abstract: An integrated circuit memory device and method incorporating Flash and ferroelectric random access memory arrays integrated on a common substrate. The present invention allows a relatively small amount of ferroelectric random access memory to mitigate many of the erase and write time disadvantages exhibited by current Flash technology devices. In particular, whether combined together as a single stand-alone memory device or embedded together as a portion of a processor, microcontroller or application specific integrated circuit (“ASIC”), a block of ferroelectric memory that is sized to match the largest sector of Flash memory can effectively compensate for the latter's slow erasure and write times.

Abstract: An FeRAM array replaces ROM, PROM, EPROM, and/or EEPROM in a programmable controlling device and thus provides non-volatile memory cells for code stores, data stores, registers (including peripheral registers), state machines and microcode (if included) in the device. The programmable controlling device contains a processor and non-volatile ferroelectric memory cells as well as a ferroelectric memory array. The array has a code store that holds a program to control the processor, a data store that stores temporary data from the processor, and one or more registers that hold data being manipulated by the processor. The code store, data store and registers are memory mapped onto the non-volatile ferroelectric memory array. The state machines and peripheral registers are made of ferroelectric memory cells. The programmable controlling device may also include microcode that cooperates with the processor to change the function of the processor.

Abstract: An associative memory device having a high speed and good performance is provided without degrading the simple design of a peripheral circuit of a conventional associative memory. The associative memory device has an N-bit first buffer and an M-bit second buffer in which W-bit data is stored through a data input port, detection device for detecting that the W-bit data is input to the first buffer k times or to the second buffer r times, a switch for alternately switching buffers in which the W-bit data is stored, and a search control for performing a search operation for a memory region by using data in the first or second buffer. By using data in the first or second buffer, during the search operation for the memory region of the associative memory, the W-bit data for the next search operation is input to the second or first buffer.

Abstract: An application-specific integrated circuit (ASIC) for enabling access to memory. ASIC includes a decryptor, a valid authorization storage component, an upgrade verifier, an upgrade storage component, and an enabling component. The decryptor inputs an encrypted authorization code and outputs a decrypted authorization code. The valid authorization storage component stores and outputs a valid authorization code. The upgrade verifier inputs the decrypted authorization code and the valid authorization code, compares the decrypted authorization code to the valid authorization code to determine whether access to the portion of memory is authorized, and outputs a signal to enable access to the portion of memory. The upgrade storage component stores the signal output from the upgrade verifier. The enabling component inputs a memory access signal and a signal stored in the upgrade storage component and outputs a signal indicating whether the portion of memory is enabled.