Storage Accessing And Control Patents (Class 711/100)
  • Patent number: 10735513
    Abstract: A method of accessing a remote storage subsystem from a host device separate from the remote storage subsystem and connected via interfaces to a data communications topology is disclosed. In one embodiment, the communications interface comprises an RDMA network fabric. In one embodiment, the method includes queuing a write command or a read command in a submission queue of the remote storage subsystem, and placing a write data into a memory of the remote storage subsystem. The method further includes transmitting a message to the remote storage subsystem indicating the write command or the read command has been submitted in the submission queue, and detecting a command completion status from a completion queue of the remote storage subsystem. The method further includes transmitting a message to the remote storage subsystem indicating the command completion status has been detected.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: August 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shimon Tsalmon
  • Patent number: 10733118
    Abstract: This computer system is configured by connecting a plurality of computers via a communication network. At least one computer among the computers has a storage device and a communication device. The communication device has: a controller that controls data transmission/reception via the communication network; and an intermediate memory that stores data transmitted/received between the storage device and other calculators on the communication network.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 4, 2020
    Assignee: HITACHI, LTD.
    Inventors: Sho Takizawa, Hideaki Fukuda, Kyohei Ide
  • Patent number: 10733148
    Abstract: A database may delete rows of data based on one or more predicate parameters. A method of data storage includes receiving a delete request for a database, where the delete request includes one or more predicate parameters and adding the predicate parameters to a set of deletion predicate parameters in metadata of the database. The method may further include performing a compaction of the database, where the compaction includes rewriting each data element of the database unless a key of the data element corresponds to at least one of the set of deletion predicate parameters.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: August 4, 2020
    Assignee: salesforce.com, inc.
    Inventor: Lars Hofhansl
  • Patent number: 10732844
    Abstract: The disclosure enables management of block storage more efficiently than with traditional free space bitmap approaches. An exemplary method includes segregating disk gap indices by differentiated gap sizes; maintaining a set of lists for segregated sizes, such that each list identifies gaps of a common size; comparing a length of a list with trigger criteria, and based at least on the length of the list meeting the criteria, writing at least a portion of the list into a disk gap. Writing gap locations into gaps in disk storage reduces memory burdens, and the gap data can later be extracted when the list becomes short. These processes can be performed iteratively. The prior need for traversing a free space bitmap to find a gap of a particular size is eliminated; the new method permits more rapid location of a particular size gap by selecting an element of the proper list.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: August 4, 2020
    Assignee: VMware, Inc.
    Inventors: Oleg Zaydman, Roman Zhirin
  • Patent number: 10725990
    Abstract: A hashing system can use a set of multiple numbers that are co-prime to the size of a hash table to select a probe offset when collisions occur. Selecting a probe offset that is co-prime to the hash table size ensures that each hash table slot is available for any insert operation. Utilizing different co-prime numbers for different keys helps avoid clustering of items inserted into the hash table. When a collision occurs, the hashing system can compute a next index to check by selecting a probe offset that is located at a computed index on a list of numbers that are each co-prime to the number of slots in the hash table. The hashing system can compute the index into the list of numbers by applying a hash function to the data item and calculating a modulus of the result with respect to a count of the co-prime numbers list.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: July 28, 2020
    Assignee: Facebook, Inc.
    Inventor: Alex Meyer
  • Patent number: 10725707
    Abstract: Data volumes for a customer can be placed on various storage tiers, including different hardware types or storage systems, that are determined to be appropriate for the anticipated usage of those data volumes. The actual usage can be monitored to determine one or more types of workload for the data volume, and a determination made as to whether all, or portions, of the data volume could obtain a significant performance improvement by being migrated to a different storage tier. In some instances the chunks or partitions of a volume can be concurrently distributed across multiple different storage tiers in order to satisfy various performance and/or cost criteria. Once workload information is available for a customer, that information can be used to determine the storage tiers for initial placement of subsequent data volumes.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 28, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Magee Greenwood, Gary Michael Herndon, Jr.
  • Patent number: 10713334
    Abstract: According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: July 14, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mark Himelstein, Bruce Wilford, Richard Van Gaasbeck, Todd Wilde, Rick Carlson, Vikram Venkataraghavan, Vishwas Durai, Blair Barnett, Kevin Rowett
  • Patent number: 10713746
    Abstract: Methods and devices for managing first-in first-out (FIFO) queues in graphics processing are described. A write operation can be executed by multiple write threads on a graphics processing unit (GPU) to write data to memory locations in the multiple pages of memory. The write operation can also include allocating additional pages of memory for the FIFO queue where a write allocation pointer is determined to achieve a threshold, such to grow the FIFO queue before the memory is actually needed for writing. Similarly, comprises a read operation can be executed by multiple read threads to read data from the memory locations. The read operation can also include deallocating pages of memory back to a memory pool where a read done pointer is determined to achieve a threshold, such as an end of a page.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 14, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jason M. Gould, Ivan Nevraev
  • Patent number: 10678936
    Abstract: A method, apparatus, computer-readable medium, and/or system described herein may be used to efficiently store, move, and/or process data across a plurality of computing clusters. For example, a computing device may receive an indication of one or more data storage locations within a first cluster of servers and/or an indication of one or more data storage locations within a second cluster of servers. The computing device may generate a data file comprising the indication of the one or more data storage locations within the first cluster of servers and/or the indication of one or more data storage locations within the second cluster of servers. Based on the generated data file, the computing device may generate a job to move data stored at the one or more data storage locations within the first cluster of servers to the one or more data storage locations within the second cluster of servers. Based on the job, the computing device may transmit, e.g.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 9, 2020
    Assignee: Bank of America Corporation
    Inventors: Sitaram C. Yarlagadda, Vijaya M. Anusuri
  • Patent number: 10678733
    Abstract: Described herein are a method and device for transferring data in a computer system. The device includes a host processor, a plurality of first memory architectures, a switch, a redundant array of independent drives (RAID) assist unit; and a second memory architecture. The host processor is configured to send a data transfer command to the RAID assist unit via the switch. The RAID assist unit is configured to create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, execute the set of parallel memory transactions via the local switch and absent interaction with the host processor; and notify the host processor upon completion of data transfer. In an implementation, the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: June 9, 2020
    Assignee: ATI Technologies ULC
    Inventor: Nima Osqueizadeh
  • Patent number: 10678716
    Abstract: A memory device includes: a plurality of first control signal interfaces respectively corresponding to a plurality of channels, and suitable for receiving control signals from a host; a plurality of first data interfaces respectively corresponding to the plurality of channels, and suitable for exchanging data and data strobe signals with the host; a second control signal interface suitable for receiving control signals through a selected one of the first control signal interfaces and a selected one of the channels and outputting the received control signals, in a monitoring mode; and a second data interface suitable for receiving a part of the data and data strobe signals exchanged through a selected one of the first data interfaces and the selected channel, and outputting the received part of the data and data strobe signals, in the monitoring mode.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Myeong-Jae Park, Seok-Woo Choi, Young-Jae Choi
  • Patent number: 10671296
    Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 2, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 10671299
    Abstract: The nonvolatile memory module includes at least one nonvolatile memory, and a device controller including a RAM to store data exchanged between a host and the at least one nonvolatile memory and a DIMM controller to control data exchange between the RAM and the at least one nonvolatile memory. An allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 2, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee Hyun Nam, Youngjin Cho
  • Patent number: 10664349
    Abstract: A file storage method and device are provided. The method includes: receiving a storage request for a to-be-stored file (S101); determining a target key for storing the to-be-stored file (S102); obtaining to-be-stored metadata of the to-be-stored file according to the determined target key (S103), wherein the to-be-stored metadata includes: fixed sub-metadata and variable sub-metadata; and storing the to-be-stored metadata in a metadata database, storing the fixed sub-metadata in a name of the determined target key, storing the variable sub-metadata in a preset storage area corresponding to the determined target key, and storing the to-be-stored file in a value of the determined target key (S104). By applying the file storage and device, the recovery of metadata is effectively ensured, while a storage space of a storage terminal is saved.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: May 26, 2020
    Assignee: Hangzhou Hikvision Digital Technology Co., Ltd.
    Inventors: Zhiyong Ding, Qiqian Lin, Wei Chen, Li Cao
  • Patent number: 10664275
    Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Susan E. Eisen, Hung Q. Le, Bryan J. Lloyd, Dung Q. Nguyen, David S. Ray, Benjamin W. Stolt, Shih-Hsiung S. Tung
  • Patent number: 10664166
    Abstract: Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: May 26, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Kushagra Vaid, Sompong Paul Olarig
  • Patent number: 10658056
    Abstract: An embodiment of a semiconductor package apparatus may include technology to attempt to program data in a first portion of a nonvolatile memory, determine if the attempt was successful, and recover the data to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Wayne Tran
  • Patent number: 10649893
    Abstract: Namespace planning of non-volatile memory that takes advantage of multi-channel accessing and considers multi-channel properties is provided. A data storage device includes a non-volatile memory and a controller. The controller accesses the non-volatile memory through multiple channels. When performing namespace planning on the non-volatile memory, the controller makes each assigned channel correspond to just one namespace.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: May 12, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Sheng-Liu Lin
  • Patent number: 10643193
    Abstract: A mainframe computing system includes a central processor complex, and a plurality of billing entities, each billing entity having a respective capacity limit, and a workload manager that schedules work requested by the plurality of billing entities on the central processor complex and tracks, by billing entity, a rolling average of service units. The mainframe computing system also includes a dynamic capping policy for the central processor complex that identifies a maximum service unit limit, a subset of the plurality of billing entities, and, for each identified billing entity, information from which to determine a service unit entitlement value. The mainframe computing system also includes a dynamic capping master that adjusts the respective capacity limits of the subset of the plurality of billing entities at scheduled intervals based on the dynamic capping policy to favor billing entities having high-importance workload within the maximum service unit limit.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: May 5, 2020
    Assignee: BMC SOFTWARE, INC.
    Inventors: Phat Tran, Edward Williams, Hemanth Rama, Robert Perini, Steven Degrange
  • Patent number: 10636462
    Abstract: A semiconductor device includes a command synthesis circuit synchronized with a first division clock signal to shift a command based on an offset signal and synchronized with a second division clock signal to generate a command synthesis signal from the shifted command. The semiconductor device also includes a strobe control signal synthesis circuit synchronized with the second division clock signal to generate a strobe synthesis signal from a strobe control signal. The semiconductor device further includes a drive control circuit generating a drive control signal from any one of the command synthesis signal and a drive signal based on the strobe synthesis signal.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Seung Wook Oh, Jin Il Chung
  • Patent number: 10635818
    Abstract: Technologies are disclosed herein for blocking access to some firmware variables during runtime. These firmware variables may be disallowed from runtime access (e.g., read/write access), by placing an indication of the firmware variables on a runtime blocklist. Upon completion of booting, runtime firmware services may access the runtime blocklist to determine if a firmware variable is to be accessed during runtime. In some cases, a firmware variable may be disallowed from runtime access by inclusion in the runtime blocklist, even if that firmware variable has an attribute that indicates that it is runtime accessible. The runtime blocklist may be generated based at least in part on indications of the firmware variables to be blocked during runtime. Additionally, runtime accessible firmware variables may be exposed to higher-level software, such as an O/S, if the firmware variables are not included in the runtime blocklist.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 28, 2020
    Assignee: American Megatrends International, LLC
    Inventor: Srinivasan N. Rao
  • Patent number: 10613996
    Abstract: In a data processing network comprising a Request, Home and Slave Nodes coupled via a coherent interconnect, a Home Node performs a read transaction in response to a read request from a Request Node. In a first embodiment, the transaction is terminated in the Home Node upon receipt of a read receipt from a Slave Node, acknowledging a read request from the Home Node. In a second embodiment, the Home Node sends a message to the Request Node indicating that a read transaction has been ordered in the Home Node and further indicating that data for the read transaction is provided in a separate data response. The transaction is terminated in the Home Node upon receipt of an acknowledge from the Request Node of this message. In this manner, the transaction is terminated in the Home Node without waiting for acknowledgement from the Request Node of completion of the transaction.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: April 7, 2020
    Assignee: Arm Limited
    Inventors: Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Tushar P. Ringe, Klas Magnus Bruce
  • Patent number: 10606805
    Abstract: Methods, systems, and computer program products are included for querying and retrieving objects from images. An example method includes traversing a persistent local mirror overlay filesystem (PLMO FS) to determine whether one or more objects of a requested image already exist on a local data storage device. If so, an I/O hit is determined, and the objects are not pulled from the registry. Conversely, if the objects are not found on the local data storage device, an I/O miss is determined, and the objects are pulled from the registry. A local copy of the requested image is then built using the already locally-existing I/O-hit objects and the newly retrieved I/O-missed objects, such that the local copy of the requested image is a mirror of the original requested image in the registry.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 31, 2020
    Assignee: RED HAT, INC.
    Inventor: Huamin Chen
  • Patent number: 10599530
    Abstract: Example implementations involve a plurality of servers, network, and storage systems, wherein some of the servers may execute data programs and store primary data in the memory of the servers. Some of the servers may also execute a standby data program. Storage devices may provide for a snapshot volume, a log volume, and a recovery volume, and executes a recovery program to store a recovery image into the recovery volume from the data of the snapshot volume and the log volume. On failure of the server, the standby data program loads the recovery image of the recovery volume, which can reduce the time to commit logs to the snapshot image.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: March 24, 2020
    Assignee: HITACHI, LTD.
    Inventor: Keisuke Hatasaki
  • Patent number: 10599366
    Abstract: A distributed file system may be configured with file blocks of a first type and file blocks of a second type, from allocation units that comprise a logical volume containing the file system. File blocks of the second type may be defined from one or more file blocks of the first type. A thick file may be instantiated with a number of allocation units totaling a size greater than or equal to a specified file size of the thick file. The allocation units may be allocated to the thick file in units of file blocks of the first type or file blocks of the second type, depending on the specified file size of the thick file.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 24, 2020
    Assignee: VMWARE, INC.
    Inventors: Asit Desai, Prasanna Aithal, Prasad Rao Jangam, Bryan Branstetter, Mahesh S Hiregoudar, Pradeep Krishnamurthy, Rohan Pasalkar, Raghavan Pichai, Srinivasa Shantharam
  • Patent number: 10592424
    Abstract: A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which data coherency is maintained across multiple caches. A tag search structure is maintained that identifies address tags and coherence states of cached data indexed by address tags. In response to a request from a device internal to or external from the coherence network, the tag search structure is searched to identify address tags of cached data for which the coherence state is to be modified and requests are issued in the data processing system to modify a coherence state of cached lines with the identified address tags. The request from the external device may specify a range of addresses for which a coherence state change is sought. The tag search structure may be implemented as search tree, for example.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: March 17, 2020
    Assignee: Arm Limited
    Inventors: Jonathan Curtis Beard, Stephan Diestelhorst
  • Patent number: 10585816
    Abstract: An information handling system includes a planar board and a peripheral interface device. The planar board includes a central processing unit, a baseboard management controller, and an interface logic circuit. The peripheral interface device includes a microcontroller and a serial communication interface device. The peripheral interface device is coupled to a peripheral device. The information handling system also includes an interconnect to couple signals from the planar board to the peripheral interface device. The interconnect includes a single wire to couple first information from the interface logic circuit to the peripheral interface device and to couple second information from the serial communication interface device to the interface logic circuit. The first information includes a first power control command.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 10, 2020
    Assignee: Dell Products, L.P.
    Inventors: Timothy M. Lambert, Jordan Chin, Jeremiah Bartlett, Jeffrey L. Kennedy
  • Patent number: 10579520
    Abstract: Examples of the present disclosure describe systems and methods for sharing memory using a multi-ring shared, traversable and dynamic database. In aspects, the database may be synchronized and shared between multiple processes and/or operation mode protection rings of a system. The database may also be persisted to enable the management of information between hardware reboots and application sessions. The information stored in the database may be view independent, traversable, and resizable from various component views of the database. In some aspects, an event processor is additionally described. The event processor may use the database to allocate memory chunks of a shared heap to components/processes in one or more protection modes of the operating system.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: March 3, 2020
    Assignee: Webroot Inc.
    Inventor: John R. Shaw, II
  • Patent number: 10572382
    Abstract: A method of operating a data storage device includes receiving size information of a region needed for a data transaction from a host, calculating the sum of a size of a first region available in an invisible region-to-user and a size of a second region available in a visible region-to-user based on the size information, and communicating a response indicating possibility of the data transaction to the host based on a calculation result.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Sik Yun, Youn Won Park, Sang Yoon Oh
  • Patent number: 10572480
    Abstract: A computer-implemented method includes identifying a query, including one or more predicates and one or more branches, wherein one or more branches includes one or more legs. The computer-implemented method further includes, for each branch, in parallel: determining a risk, determining a return row threshold, estimating a number of return rows; terminating access if the return rows exceed the threshold. The computer-implemented method further includes, for each leg, in parallel: determining a leg return row threshold; accessing the leg; fetching one or more return rows into one or more leg return row pages; terminating access if the return rows exceed the threshold; intersecting one or more leg return row pages into one or more intersected leg return row pages; and applying the one or more predicates to the one or more intersected leg return row pages. The method may be embodied in a corresponding computer system or computer program product.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Shuo Li, Heng Liu, Ke Wei Wei, Xin Ying Yang
  • Patent number: 10572466
    Abstract: Exemplary embodiments provide the ability to associate multiple collections of metadata to objects. In one embodiment, a storage system comprises: a processor; a memory; at least one object, each object including content data; system metadata associated with each object; and a plurality of named collections of user-defined metadata associated with each object. Each named collection of the plurality of named collections is separately addressable by a request. In some embodiments, at least one named collection of user-defined metadata of one object of the at least one object includes an access control list, and the access control list of a named collection specifies permissible access to the named collection. The one object has an object-level access control list which specifies permissible access to the one object and which is different from the access control list for the named collection associated with the one object.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: February 25, 2020
    Assignee: Hitachi Vantara Corporation
    Inventors: Scott Nyman, Clifford Grimm
  • Patent number: 10564876
    Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seonghoon Woo, Soon Suk Hwang
  • Patent number: 10565120
    Abstract: According to some embodiments, a backup storage system receives a request from a client for writing a data segment associated with a file object stored to a storage system. In response to the request, the system writes the data segment to one of many storage units of the storage system. The system determines whether the data segment is associated with a file region of the file object that is frequently accessed. The system writes the data segment in a first of many of write-evict units (WEUs) stored in a solid state device (SSD) operating as a cache memory device for caching data, after it is determined that the data segment is associated with the frequently accessed file region.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: February 18, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Satish Visvanathan, Rahul B. Ugale
  • Patent number: 10558393
    Abstract: A system is proposed to enable a hardware based host controller to perform operations related to Host-aware Performance booster (HPB). The host controller may retrieve a command packet from a host memory targeting a logical address of a storage location of the storage device, may retrieve a physical address of the storage device mapped to the logical address from the address map, and may send the command packet to the storage device. The sent command packet may have the physical address incorporated therein.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 11, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Hyunsuk Shin, David Teb, Hung Vuong
  • Patent number: 10552163
    Abstract: A method and system performs instruction scheduling in an out-of-order microprocessor pipeline. The method and system selects a first set of instructions to dispatch from a scheduler to an execution module, wherein the execution module comprises two types of execution units. The first type of execution unit executes both a first and a second type of instruction and the second type of execution unit executes only the second type. Next, the method selects a second set of instructions to dispatch, which is a subset of the first set and comprises only instructions of the second type. The method determines a third set of instructions, which comprises instructions not selected as part of the second set. Further, the method dispatches the second set for execution using the second type of execution unit and dispatching the third set for execution using the first type of execution unit.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventor: Nelson N. Chan
  • Patent number: 10552321
    Abstract: Enhanced data buffer control in data systems is presented herein. In one example, a method of handling data buffer resources in a graphics processor includes establishing a pool of available memory pages tracked by memory pointers for use in a growable data structure. Responsive to requests by at least a shader unit of the graphics processor for space in the growable data structure in which to write shader data, the method includes providing to the shader unit at least write pointers to locations within memory pages from the growable data structure in accordance with data sizes indicated in the requests. Responsive to exceeding a threshold fullness of the growable data structure, the method includes allocating at least one further memory page from the pool of available memory pages for inclusion in the growable data structure.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: February 4, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jason Matthew Gould, Ivan Nevraev
  • Patent number: 10545764
    Abstract: A data processing apparatus comprises register rename circuitry for mapping architectural register specifiers specified by instructions to physical registers to be accessed in response to the instructions. Available register control circuitry controls which physical registers are available for mapping to an architectural register specifier by the register rename circuitry. For at least one group of two or more physical registers, the available register control circuitry controls availability of the registers based on a group tracking indication indicative of whether there is at least one pending access to any of the physical registers in the group.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 28, 2020
    Assignee: ARM Limited
    Inventors: Luca Scalabrino, Frederic Jean Denis Arsanto, Thomas Gilles Tarridec, Cedric Denis Robert Airaud
  • Patent number: 10545863
    Abstract: According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies, based on a first management table corresponding to a copy-source block for garbage collection, only data corresponding to reference counts of non-zero from the copy-source block to a copy-destination block, and associates physical addresses respectively indicating locations in the copy-destination block, in which the data are copied, with respective intermediate addresses corresponding to the copied data.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: January 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Naoki Esaka
  • Patent number: 10545864
    Abstract: According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: January 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Naoki Esaka
  • Patent number: 10542171
    Abstract: There is provided with an information processing apparatus and a method of controlling the same. The apparatus sets a naming rule for an image file and determines whether or not the set naming rule satisfies a predetermined condition. If it is determined that the naming rule does not satisfy the predetermined condition, the information processing apparatus warns a user. On the other hand, if it is determined that the naming rule satisfies the predetermined condition, the information processing apparatus generates a file name of the image file in accordance with the set naming rule, and stores the image file with the file name.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 21, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Ryuta Mori, Makiya Tamura, Daijiro Miyamoto, Natsuki Kato
  • Patent number: 10534726
    Abstract: Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: January 14, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Jason G. McHugh, Praveen Kumar Gattu, Michael A. Ten-Pow, Derek Ernest Denny-Brown, II
  • Patent number: 10531125
    Abstract: A video compression method and a video compressor are provided to solve problems of huge resource consumption and high costs caused by performing both H.264 compression and HEVC compression. The method specifically includes: reading video signal data by using a sliding window to generate bitstream data, where bitstream data generated by reading the video signal data according to a first format is first bitstream data, and bitstream data generated by reading the video signal data according to a second format is second bitstream data; and coding the bitstream data to generate a bitstream, where a bitstream generated by coding the first bitstream data is a first bitstream, and a bitstream generated by coding the second bitstream data is a second bitstream, where the second format is a format preset according to the first format. The present invention is applied to video signal compression.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: January 7, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jian Gao, Feng Zhou, Yang Song
  • Patent number: 10521401
    Abstract: One or more techniques and/or computing devices are provided for data object retention. For example, a data retention policy may specify that files of a volume are to be locked down for a lockdown retention period (e.g., locked into a read only state for 4 months) when such files are not changed within an auto commit time period (e.g., files not changed within 13 hours). Waiting for a data scanner to evaluate files for lockdown may result in files violating the data retention policy until the data scanner evaluates such files. Accordingly, a file may be considered to be in the locked down state (e.g., instantaneous lockdown), such that commands to modify or delete the file are blocked, based upon a difference between a current time of an internal compliance clock and a current value of a data object change field exceeding the auto commit time period.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 31, 2019
    Assignee: NetApp Inc.
    Inventors: Raman Madaan, Akshatha Gangadharaiah, Vaiapuri Ramasubramaniam, Balamurugan Ramajeyam, Aftab Ahman Ansari
  • Patent number: 10515018
    Abstract: Functionality is described herein for memory-mapping an information unit (such as a file) into virtual memory by associating shared virtual memory resources with the information unit. The functionality then allows processes (or other entities) to interact with the information unit via the shared virtual memory resources, as opposed to duplicating separate private instances of the virtual memory resources for each process that requests access to the information unit. The functionality also uses a single level of address translation to convert virtual addresses to corresponding physical addresses. In one implementation, the information unit is stored on a bulk-erase type block storage device, such as a flash storage device; here, the single level of address translation incorporates any address mappings identified by wear-leveling and/or garbage collection processing, eliminating the need for the storage device to perform separate and independent address mappings.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: December 24, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jian Huang, Anirudh Badam
  • Patent number: 10509628
    Abstract: A FIFO memory device has a first number of data storage units and a second number of internal FIFO memories. Each internal FIFO memory has a third number of internal data storage units. The first number is a product of the second and third numbers. A fourth number of data inputs receives input data units in order. Input multiplexer circuitry connects each one of the data inputs to any one of the internal FIFO memories, for storage of input data units, in order, in a first layer of the FIFO memory device including corresponding storage locations in respective ones of the internal FIFO memories. The first layer may be physical, or may be logical and maintained by pointers. Output multiplexer circuitry coupled to the internal FIFO memories connects each of the internal FIFO memories to any one of the data outputs to read out the stored data units in order.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: December 17, 2019
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Eliya Babitsky, Yakov Tovar, Yaniv Azulay, Moran Noiman
  • Patent number: 10511598
    Abstract: Technologies for dynamic loading of integrity protected modules into a secure enclave include a computing device having a processor with secure enclave support. The computing device divides an executable image into multiple chunks, hashes each of the chunks with corresponding attributes that affect security to generate a corresponding hash value, and generates a hash tree as a function of the hash values. The computing device generates an initial secure enclave memory image that includes the root value of the hash tree. At runtime, the computing device accesses a chunk of the executable image from within the secure enclave, which generates a page fault. In response to the page fault, the secure enclave verifies the associated chunk based on the hash tree and accepts the chunk into the secure enclave in response to successful verification. The root value of the hash tree is integrity-protected. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Mark W. Shanahan, Bin Xing
  • Patent number: 10509660
    Abstract: Systems and methods for assessing configuration profiles for a user configurable device. The configuration profile may include sets configuration parameters and an associated configuration parameter values that may be analyzed to determine a set of current states for the user configurable device. The set of current states may be used to identify a candidate state that is related to a candidate configuration profile. The candidate configuration profile may include at least one set of a candidate configuration parameter and an associated candidate configuration parameter value. One or more prompts may be rendered via the customer device to set at least one of the configuration parameters and associated configuration parameter values based on the corresponding candidate configuration parameter values. A response is received via the user interface to the prompt, and an indication of such response may be transmitted to update the identification of the subsequent candidate configuration profiles.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: December 17, 2019
    Assignee: Datalogic IP Tech, S.r.l
    Inventors: Francesco D'Ercoli, Marco Cumoli, Francesco Paolo Muscaridola
  • Patent number: 10497409
    Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 3, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles A. Kilmer, Anil B. Lingambudi, Warren E. Maule, Diyanesh B. C. Vidyapoornachary
  • Patent number: 10496574
    Abstract: Systems, methods, and apparatuses relating to a memory fence mechanism in a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a plurality of operations, each by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. The processor also includes a fence manager to manage a memory fence between a first operation and a second operation of the plurality of operations.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Kermin Fleming, Kent D. Glossop, Simon C. Steely, Jr.
  • Patent number: 10496834
    Abstract: A computer system with multiple security levels, the system comprising a high-power processing device (130), a low-power processing device (110), and an interface unit (120) comprising functions for moving classified information between the high-power device (130) and the low-power device (110) according to formal rules for confidentiality and/or integrity. Additional security aspects, e.g. availability, may readily be accommodated. A method for implementing multiple levels of security along a number of independent security axes on the system is also disclosed.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 3, 2019
    Assignee: CUPP Computing AS
    Inventor: Omar Nathaniel Ely