Storage Accessing And Control Patents (Class 711/100)
  • Patent number: 11368448
    Abstract: Systems and methods for network security are provided. Various embodiments of the present technology provide systems and methods for an identity security gateway agent that provides for privileged access. Embodiments include a system and method that uses a single sign-on (SSO) (or similar) mechanism to facilitate a user accessing web-based service providers, but separates the assertion and entire SSO process from the user credential.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: June 21, 2022
    Assignee: SAILPOINT TECHNOLOGIES, INC.
    Inventors: Ryan Privette, Kris Keller
  • Patent number: 11354067
    Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: June 7, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kalyan Chakravarthy C. Kavalipurapu, Chang H. Siau, Shigekazu Yamada
  • Patent number: 11347668
    Abstract: A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 31, 2022
    Assignee: NVIDIA Corporation
    Inventors: Xiaogang Qiu, Ronny Krashinsky, Steven Heinrich, Shirish Gadre, John Edmondson, Jack Choquette, Mark Gebhart, Ramesh Jandhyala, Poornachandra Rao, Omkar Paranjape, Michael Siu
  • Patent number: 11347681
    Abstract: Files can be managed to mitigate undesirable reading of files from secondary storage component (SSC) associated with a storage system comprising primary storage component (PSC). File management component (FMC) can determine file identifiers for files stored in SSC and store them in reference files associated with such files. FMC can determine file identifiers for files stored in PSC and store them in a file entry data store. In response to a client request, FMC can determine whether a local file stored in PSC is a copy of an archived file stored in SSC based on whether the respective file identifiers of the archived file and local file or snapshot of the local file match. If there is a suitable match, FMC can read the snapshot of the local file and provide it to client device; if not, FMC can read the archived file and provide it to client device.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 31, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Shiv Kumar, Jai Gahlot, Avadut Mungre
  • Patent number: 11334488
    Abstract: A cache management circuit that includes a predictive adjustment circuit configured to predictively generate cache control information based on a cache hit-miss indicator and the retention ranks of accessed cache lines to improve cache efficiency is disclosed. The predictive adjustment circuit stores the cache control information persistently, independent of whether the data remains in cache memory. The stored cache control information is indicative of prior cache access activity for data from a memory address, which is indicative of the data's “usefulness.” Based on the cache control information, the predictive adjustment circuit controls generation of retention ranks for data in the cache lines when the data is inserted, accessed, and evicted.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 17, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rami Mohammad Al Sheikh, Arthur Perais, Michael Scott McIlvaine
  • Patent number: 11321318
    Abstract: Embodiments are disclosed for a method for dynamic access paths. The method includes generating real-time statistics (RTS) estimates based on a log of a database. Further, the method includes generating access paths based on a structured query language command and the RTS estimates. The method also includes training a machine learning model to map the RTS estimates to the access paths.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: May 3, 2022
    Assignee: International Business Machines Corporation
    Inventors: Peng Hui Jiang, Xiao Xiao Chen, Shuo Li, ShengYan Sun, Xiaobo Wang
  • Patent number: 11316671
    Abstract: A non-transitory computer-readable medium for sharing protected content, comprising instruction stored thereon. When executed on a processor, the instruction performs steps of deriving a shared secret, processing the shared secret using a secure hash algorithm 256 cryptographic hash to produce a primary encryption key, and encrypting a secondary encryption key using the primary encryption key. When the shared secret is derived between a private key and a public key of a first user, encrypting the protected content using the secondary encryption key, and transmitting the encrypted protected content to a server to be accessed by the second user. When the shared secret is derived between the private key of the first user and a public key of a second user, transmitting the secondary encryption key to the second user. The second user uses the secondary encryption key to decrypt the encrypted protected content on the server.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: April 26, 2022
    Assignee: Viasat, Inc.
    Inventors: Bruce D. Miller, Townsend J Smith, III, Vihar R Rai, Benjamin M Collins
  • Patent number: 11307942
    Abstract: A memory system, a memory controller and an operating method are disclosed. By dividing a read count table including read count values respectively for a plurality of memory blocks into one or more read count table segments each including one or more read count values of a resolution, and managing one or more flags respectively corresponding to the read count table segments, and set the flag corresponding to the read count table segment in which at least one read count value is changed among the read count table segments, it is possible to minimize additional operational costs required to recover the read count table upon occurrence of an SPO.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Jin Pyo Kim
  • Patent number: 11301235
    Abstract: Prior to an update of an operating system of a computing device, a configuration operation is performed with respect to a particular processor of the computing device, such that the particular processor is indicated to the operating system as being in an offline state while an application runs at the particular processor. The operating system is then updated. The update comprises a time interval in which the operating system is unavailable and the application performs one or more computations at the particular processor. After the update, the application is restarted.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: April 12, 2022
    Assignee: Amazon Technologies, Inc.
    Inventor: Tahsin Erdogan
  • Patent number: 11294994
    Abstract: An integrated circuit (IC) card of an embodiment includes a communicator, a storage storing biometric authentication information, an acquirer, and a processor. The communicator communicates with a terminal device. The acquirer acquires biometric information of a user. The processor collates the biometric information of the user acquired by the acquirer with the biometric authentication information stored in the storage and stores a collation result into the storage at an activation time.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 5, 2022
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions Corporation
    Inventor: Tomomi Tsuboi
  • Patent number: 11281378
    Abstract: A method of increasing operational life time of SSD RAID and a storage equipment using same, the method including: configuring a data storage device to have a plurality of storage areas, each storage area including a plurality of stripes, and each stripe including an individual block of a plurality of solid state disks, where at least one block in each stripe is a check bit block, the other blocks are data blocks; and configuring two neighboring stripes in each storage area to form a composite stripe according to a plurality of index combinations in a mapping table, where the composite stripe includes two neighboring blocks in each solid state disk, and the composite stripe is divided into a stripe writing area and an empty stripe area, so that each solid state disk in each storage area has a reserved space.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 22, 2022
    Assignee: QNAP SYSTEMS, INC.
    Inventor: Tsu-Yu Wu
  • Patent number: 11263131
    Abstract: Embodiments of the disclosure provide systems and methods for allocating memory space in a memory device. The system can include: a memory device for providing the memory space; and a compiler component configured for: receiving a request for allocating a data array having a plurality of data elements in the memory device, wherein each of the plurality of data elements has a logical address; generating an instruction for allocating memory space for the data array in the memory device based on the request; generating device addresses for the plurality of data elements in the memory device based on logical addresses of the plurality of data elements; and allocating the memory space for the data array in the memory device based on the device addresses and the instruction.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: March 1, 2022
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Shuangchen Li, Dimin Niu, Fei Sun, Jingjun Chu, Hongzhong Zheng, Guoyang Chen, Yingmin Li, Weifeng Zhang, Xipeng Shen
  • Patent number: 11262949
    Abstract: An approach is provided for reducing command bus traffic between memory controllers and PIM-enabled memory modules using special PIM commands. The term “special PIM command” is used herein to describe embodiments and refers to a PIM command for which the corresponding module-specific command information is provided to memory modules via a non-command bus data path. A memory controller generates and issues a special PIM command to multiple PIM-enabled memory modules via a command bus and provides module-specific command information (e.g., address information) for the special PIM command to the PIM-enabled memory modules via the non-command bus data path that is shared by the PIM-enabled memory modules and the memory controller.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 1, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Johnathan Alsop, Shaizeen Aga, Nuwan Jayasena
  • Patent number: 11249920
    Abstract: Disclosed are a non-volatile memory device and a method of operating the non-volatile memory device. A non-volatile memory device in which m logical pages are stored in a single physical page includes: a plurality of registers configured to be included in a flash translation layer (FTL) and to store at least part of the data of a write command received from a file system; and a controller configured to control operations of the plurality of registers based on the write command; wherein each of the plurality of registers is further configured to have a storage space associated with the size of the m logical pages; and wherein the controller is further configured to program the data of the write command into the non-volatile memory device and to store the data of the write command in the plurality of registers.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: February 15, 2022
    Assignee: KNU-INDUSTRY COOPERATION FOUNDATION
    Inventors: Seok Bin Seo, Wan Il Kim, Jin Young Kim, Se Jin Kwon
  • Patent number: 11250123
    Abstract: A method includes loading each section of an executable program code into a respective page of memory, configuring permissions for a first page including a first section of the executable program code to enable execution of the first section loaded into the first page. The first section associated with a first label. The method also includes configuring permissions for a second page of the memory including a second section of the executable program code to disable execution of the second section loaded into the second page. The second section associated with a second label. Responsive to a determination that a transition from the first section to the second section is allowed during execution of the executable program code, the method also includes changing the permissions of the second page to enable execution of the second section of the executable program code.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 15, 2022
    Assignee: Red Hat, Inc.
    Inventors: Peter Jones, Adam Jackson
  • Patent number: 11243692
    Abstract: A system, method, and machine-readable storage medium for analyzing a state of a data object are provided. In some embodiments, the method includes receiving, at a storage device, a metadata request for the data object from a client. The data object is composed of a plurality of segments. The method also includes selecting a subset of the plurality of segments and obtaining a segment state for each segment of the subset. Each segment state indicates whether the respective segment is accessible via a backing store. The method further includes determining a most restrictive state of the one or more segment states and sending state information to the client in response to the metadata request, the state information being derived from the most restrictive state.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: February 8, 2022
    Assignee: NETAPP, INC.
    Inventors: Raymond Yu Shun Mak, Aditya Kalyanakrishnan, Song Guen Yoon, Emalayan Vairavanathan, Dheeraj Sangamkar, Chia-Chen Chu
  • Patent number: 11237832
    Abstract: A module with a functional unit for generating a data stream with a data output for outputting the data stream to a serialization unit provided for receiving a data stream from a serialization unit of a first series. A serialization unit of a second series is set up to serialize the data stream and output it through the data output, and a configuration data input receives configuration data defining a first register configuration of a serialization unit. A mapping of register addresses of the serialization unit of the first series to register addresses of the serialization unit of the second series can be stored in a data memory of the module. The configuration unit is set up to read in the configuration data, to use the mapping, and to configure the registers of the serialization unit of the second series according to the configuration of the second register.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: February 1, 2022
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Gregor Sievers, Johannes Ax
  • Patent number: 11237750
    Abstract: A virtual storage volume that includes storage space on potentially many different physical disks may be mounted at a compute node. In order to replicate the virtual storage volume to a target compute node, a sequence of snapshots may be created that capture the state of the virtual storage volume at a sequence of points in time. The data associated with these snapshots may be transferred to the target compute node. When the difference between the snapshots is sufficiently small, the target virtual storage volume may be resynchronized.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: February 1, 2022
    Assignee: Portworx, Inc.
    Inventor: Ganesh Sangle
  • Patent number: 11232066
    Abstract: A method for data migration is provided. The method includes the following. A communication connection with a source migration terminal is established. A file list on the source migration terminal is acquired after the source migration terminal is accessed. First operations and second operations are executed in parallel. The first operations include reading out files on the source migration terminal according to the file list and storing the files read out on a migration terminal. The second operations include displaying the file list, receiving selection of a non-migrated file in the file list, and deleting the non-migrated file after the non-migrated file is migrated from the source migration terminal to the migration terminal and stored in the migration terminal. A terminal is further provided.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 25, 2022
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Xuan Zhou, Tianyang Lu
  • Patent number: 11221862
    Abstract: Data can be captured from a live web application to populate a demo application. In an example, automated input is provided to user interface touch points of a live application, and corresponding responses are captured. These responses are reformatted into a convention of the demo application, and used to populate demo response files. Then, when a demo application operates, it retrieves, processes, and displays information in these demo response files.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 11, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Aidan Hally, Conor E. O'Mahony, Caroline O'Connell
  • Patent number: 11210010
    Abstract: A method and a system for data migration on a multi-tiered storage system are provided. The method can include receiving a migration task indicating a dataset to migrate. The method can further include building a plurality of buffers onto at least one high-performance storage tier. The high-performance storage tier can be based on the read speed of that tier. The method can also include referencing a shadow mapping to locate physical data from the dataset stored on a first buffer. The method can include migrating the physical data from the first buffer to a migration destination. The method can further include deallocating the first buffer. The deallocation can allow allocation of additional physical data onto the first buffer for migration.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: December 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Qiang Xie, Hui Zhang
  • Patent number: 11210100
    Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 28, 2021
    Assignee: Apple Inc.
    Inventors: Aditya Kesiraju, Brett S. Feero, Nikhil Gupta, Viney Gautam
  • Patent number: 11204701
    Abstract: A method of processing transactions associated with a command in a storage system is provided. The method includes receiving, at a first authority of the storage system, a command relating to user data. The method includes sending a transaction of the command, from the first authority to a second authority of the storage system, wherein a token accompanies the transaction and writing data in accordance with the transaction as permitted by the token into a partition that is allocated to the second authority in a storage device of the storage system.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: December 21, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, Robert Lee, Igor Ostrovsky, Peter Vajgel
  • Patent number: 11204895
    Abstract: A data storage system implements aggregation, bifurcation, and/or reduction techniques to improve the efficiency of processing data storage requests. Data storage requests and/or their associated payloads may be aggregated based on one or more parameters. Data to be the stored and the associated commands may be separated so as to optimize a system's throughput and latency for each. Furthermore, extraneous commands and requests may be reduced or eliminated based on heuristics associated with the requests and the data.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: December 21, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Frank Charles Paterra, Eric Neilsen
  • Patent number: 11204705
    Abstract: A memory array controller includes memory media scanning logic to sample a bit error rate of memory blocks of a first memory device. A data management logic may then move data from the first memory device to a second memory device if the bit error rate matches a threshold level. The threshold level is derived from a configurable data retention time parameter for the first memory device. The configurable data retention time parameter may be received from a user or determined utilizing various known machine learning techniques.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: December 21, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao Sun, Pi-Feng Chiu, Dejan Vucinic
  • Patent number: 11194586
    Abstract: A firmware-based system and method for detecting an indicator of an override condition during a Unified Extensible Firmware Interface (UEFI) Secure Boot sequence. The indicator of the override condition may be detected based upon the pressing of a specialized button, designated key or keys or other received input that indicates both physical presence of the user and the desire, on the current boot, to bypass UEFI Secure Boot. An embodiment may work for only a single boot, not require access into a setup application, and may be accessed by externally accessible features of the computer system.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: December 7, 2021
    Assignee: Insyde Software Corp.
    Inventor: Timothy Andrew Lewis
  • Patent number: 11190445
    Abstract: A method is provided in one example embodiment and may include determining at a parent content node that a plurality of recipient content nodes are to receive a same content; generating, based on a determination that the same content is available at the parent content node, a multi-delivery header comprising a plurality of identifiers, wherein each identifier of the plurality of identifiers indicates each recipient content node that is to receive the same content; appending the multi-delivery header to one or more packets of an Internet Protocol (IP) flow associated with the same content; and transmitting packets for the IP flow to each of the plurality of the recipient content nodes.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: November 30, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Hendrikus G. P. Bosch, Sape Jurriën Mullender, Keith Burns, Jeffrey Napper, William Mark Townsley, Alessandro Duminuco, Andre Surcouf, Ijsbrand Wijnands, Humberto J. La Roche
  • Patent number: 11182285
    Abstract: A memory system may include: a nonvolatile memory device; a volatile memory suitable for storing write data; and a controller suitable for: allocating a normal write buffer in the volatile memory when normal write data are inputted, allocating a first write buffer in the volatile memory when first write data, which are grouped into a first transaction and first total size information on a total size of the first transaction, are inputted, allocating a second write buffer in the volatile memory when second write data, which are grouped into a second transaction and second total size information on a total size of the second transaction, are inputted, managing sizes of the first and second write buffers to change them in response to the first and second total size information, respectively, and managing a size of the normal write buffer to fix it to a set size.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Hae-Gi Choi
  • Patent number: 11176061
    Abstract: Memory access circuitry (26) enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry (8). The owner realm has a right to exclude other realms from accessing data within the memory region. Realm management circuitry (20) accesses a realm management tree storing realm management data for at least two realms in a tree structure having a variable number of levels. The realms are identified using a realm identifier which has a variable number of variable length bit portions each providing an index into a given level of the realm management tree.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: November 16, 2021
    Assignee: ARM Limited
    Inventors: Gareth Rhys Stockwell, Jason Parker, Matthew Lucien Evans, Martin Weidmann
  • Patent number: 11171854
    Abstract: Proposed are concepts for predicting workload of an application. Resource usage of a first application is monitored to obtain resource usage data associated with the first application. A workload signature for the first application is generated based on the obtained resource usage data, wherein the workload signature comprises information relating to static and time variant resource usage of the first application. Resource usage of a second application is predicted based on the workload signature of the first application.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Henry P. Nash
  • Patent number: 11169818
    Abstract: Systems and methods that may be implemented in a Unified Extensible Firmware Interface (UEFI) pre-boot environment time to dynamically locate and load bootable images stored in one or more operating system (OS) partitions on a system storage device/s (e.g., HDD, SSD) that is formatted with an advanced filesystem (e.g., such as NTFS, EXT3, etc.). An OS-based filesystem-independent method may be provided to access OS filesystem data during UEFI pre-boot time. Individual selected boot images stored across multiple OS filesystem partitions may be located and loaded to boot from UEFI pre-boot.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: November 9, 2021
    Assignee: Dell Products L.P.
    Inventors: Shekar Babu Suryanarayana, Ibrahim Sayyed
  • Patent number: 11163717
    Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
  • Patent number: 11157325
    Abstract: An illustrative embodiment disclosed herein is an apparatus including a processor having programmed instructions that identify a bucket identifier corresponding to a bucket. The bucket identifier includes a prefix. The processor has programmed instructions that determine that the prefix matches a predetermined prefix, assign an expiry duration to the bucket, and, after the expiry duration, delete the bucket identifier.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 26, 2021
    Assignee: Nutanix, Inc.
    Inventors: Manik Taneja, Dezhou Jiang, Ranjan Parthasarathy, Xingchi Jin
  • Patent number: 11157520
    Abstract: A dataset's uniqueness level may be calculated by analyzing a dataset to determine a uniqueness level. In cases where the uniqueness level may be too low for a particular purpose, meaning when the dataset may not provide enough anonymity, the dataset may be adjusted by recomputing the dataset with different resolutions of spatial data, temporal data, content data, and relationship data. By adjusting the resolution or accuracy of the data elements, the uniqueness level may thereby be adjusted. An error calculation may be determined by comparing the adjusted dataset to the original data, and the error value may represent the consistency of the data to the original data. The uniqueness level may be used as an assurance level of anonymity, which may be advertised when a dataset is sold or transferred to a third party for analysis.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 26, 2021
    Assignee: DataSpark, Pte Ltd.
    Inventors: The Anh Dang, Amy Xuemei Shi-Nash
  • Patent number: 11144462
    Abstract: In one embodiment, a task control block (TCB) for allocating cache storage such as cache segments in a multi-track cache write operation may be enqueued in a wait queue for a relatively long wait period, the first time the task control block is used, and may be re-enqueued on the wait queue for a relatively short wait period, each time the task control block is used for allocating cache segments for subsequent cache writes of the remaining tracks of the multi-track cache write operation. As a result, time-out suspensions caused by throttling of host input-output operations to facilitate cache draining, may be reduced or eliminated. It is appreciated that wait classification of task control blocks in accordance with the present description may be applied to applications other than draining a cache. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew G. Borlick, Jared M. Minch
  • Patent number: 11120126
    Abstract: A system and method is provided for implementing platform security on a consumer electronic device having an open development platform. The device is of the type which includes an abstraction layer operable between device hardware and application software. A secured software agent is provided for embedding within the abstraction layer forming the operating system. The secured software agent is configured to limit access to the abstraction layer by either blocking loadable kernel modules from loading, blocking writing to the system call table or blocking requests to attach debug utilities to certified applications or kernel components.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: September 14, 2021
    Assignee: IRDETO B.V.
    Inventor: Ron Vandergeest
  • Patent number: 11120002
    Abstract: The present teaching relates to concurrent database operation. In one example, a plurality of requests which includes a scan request to obtain first data associated with a plurality of first keys stored in a database is received concurrently. A global version number is updated upon receipt of the scan request. The first data associated with the plurality of first keys is obtained based on the updated global version number. The first data is provided in response to the scan request.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: September 14, 2021
    Assignee: Verizon Media Inc.
    Inventors: Edward Bortnikov, Anastasia Braginsky, Eshcar Hillel, Guy Gueta, Dmitry Basin, Moshe Sulamy
  • Patent number: 11113699
    Abstract: An identity system for the Internet of Things (IOT) that enables users and machines to identify, authenticate and interact with products and collectibles without relying on a third-party-controlled authentication service. The system includes wireless tamperproof tags coupled to products and an open registry database where a chain of ownership of the items is able to be stored. The open registry enables public access to the item identity and data combined with item registration anonymity.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 7, 2021
    Assignee: Chronicled, Inc.
    Inventors: Samantha Radocchia, David Aho, Ryan Orr, Maurizio Greco
  • Patent number: 11113262
    Abstract: Implementations of the present disclosure include associating a first transaction executed within a database system with a first transaction control block (TCB) index, setting a status of the first transaction to active and a lock status of the first transaction to holding in response to a first set of locks being established for the first transaction, the first set of locks including one or more locks that each inhibit access to a respective resource within the database system, providing a lock table that records, for a set of locks within the database system, a set of lock owners including one or more transactions identified based on respective TCB indexes and a wait queue, and determining that the first transaction has completed, and in response setting the status of the first transaction to indicate completion of the transaction and the lock status of the first transaction to released.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 7, 2021
    Assignee: SAP SE
    Inventors: Changgyoo Park, Byunghoon Kim
  • Patent number: 11115363
    Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for dynamically controlling ephemeral messaging threads and ephemeral message duration settings across computing devices while improving security by maintaining end-to-end encryption. In particular, in one or more embodiments, the disclosed systems can transmit encrypted ephemeral messages, including ephemeral message duration settings and ephemeral setting timestamps. The disclosed systems can decrypt received messages on receiving client devices and dynamically apply ephemeral message duration settings to different message threads. For example, the disclosed systems can modify existing duration settings at a receiving client device to match a received ephemeral message duration setting based on determining that the received ephemeral setting timestamp predates an existing setting timestamp.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: September 7, 2021
    Assignee: WHATSAPP LLC
    Inventors: Santiago Pina Ros, Jimmy Enrico Jacques Holzer, Shalini Sah, Elton Kyin-Fong Leong, Dafeng Ou, Christopher Luc, Nurzhan Bakibayev, Zafir Khan
  • Patent number: 11106465
    Abstract: Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: August 31, 2021
    Assignee: Arm Limited
    Inventors: Mbou Eyole, Nigel John Stephens, Neil Burgess, Grigorios Magklis
  • Patent number: 11099990
    Abstract: A system and method for efficiently forwarding cache misses to another level of the cache hierarchy. Logic in a cache controller receives a first non-cacheable load miss request and stores it in a miss queue. When the logic determines the target address of the first load miss request is within a target address range of an older pending second load miss request stored in the miss queue with an open merge window, the logic merges the two requests into a single merged miss request. Additional requests may be similarly merged. The logic issues the merged miss requests based on determining the merge window has closed. The logic further prevents any other load miss requests, which were not previously merged in the merged miss request before it was issued, from obtaining a copy of data from the returned fill data. Such prevention in a non-coherent memory computing system supports memory ordering.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: August 24, 2021
    Assignee: Apple Inc.
    Inventors: Gideon N. Levinsky, Brian R. Mestan, Deepak Limaye, Mridul Agarwal
  • Patent number: 11099980
    Abstract: One embodiment provides a method comprising maintaining, on a storage unit, mapping data between a first set of logical addresses (e.g., logical block addresses or LBAs) viewed by a host and a first set of physical addresses (e.g., physical block addresses or PBAs) and a second set of physical addresses of the storage unit. A first logical address (e.g., LBA) of the first set of logical addresses corresponds to a first physical address (e.g., PBA) of the first set of physical addresses that maintains current data for the first logical address. The first logical address further corresponds to a second physical address (e.g., PBA) of the second set of physical addresses that maintains prior data for the first logical address. The method further comprises receiving, at the storage unit, a command from the host to perform a multi-device operation involving the first logical address. The operation is performed atomically.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Hetzler, Robert M. Rees
  • Patent number: 11099948
    Abstract: Caching storage segments (e.g., pages) loaded from a remote storage such that, during recovery, the cached loaded storage segments may be at least partially recovered without reloading the storage segments from the remote storage. During normal operation of a computing system, storage segments are loaded from remote storage into local memory of a computing system. At some point, either due to eviction of the storage segment due to aging out of the storage segment, or due to writing of the storage segment, it is determined to write at least some of the loaded storage segments into local persistent storage. In conjunction with this, the corresponding storage segment is written to a respective storage address of the local persistent storage. Also, a correlation between an identifier of the storage segment and the respective address in the persistent storage is recorded in a persistent data structure.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 24, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Cristian Diaconu, Vikram Wakade, Naveen Prakash
  • Patent number: 11099740
    Abstract: Techniques manage a storage device. Such techniques involve: in response to receiving an I/O request for a storage device comprising a plurality of disks, determining, from the plurality of disks, at least one disk related to the I/O request; allocating, to each of the at least one disk, at least one access credit for completing the I/O request from total access credits of the disk, wherein the total access credits are associated with at least one of a type of the disk, a type of the I/O request and performance of the disk; and in response to respective access credits being allocated to the at least one disk, performing access requested by the I/O request to each of the at least one disk. Such techniques can effectively improve the overall access performance of the storage device.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: August 24, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Baote Zhuo, Jian Gao, Jibing Dong, Jianbin Kang, Geng Han
  • Patent number: 11093105
    Abstract: Systems and methods are provided for controlling playback of media content items on a media playback device. A graphical user interface displays media playback controls including an automatic playback switch. The switch is configured to enable or disable automatic playback of an autoplay queue of media content items. An initial queue of media content is selected for playback on the media playback device. When automatic playback is enabled, the system automatically generates a queue of media that is related to the initial queue and initiates playback on the media playback device after the initial queue concludes. Automatic playback options can also include repeating the initial queue or a single track within the initial queue.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 17, 2021
    Assignee: Spotify AB
    Inventors: Daniel Herzog, Glenn James Gentzke, Jeffrey Paul Baxter, Kylan McBride, Mark Kizelshteyn, Thomas Gayno
  • Patent number: 11086819
    Abstract: Disclosed are examples of systems, apparatus, methods and computer program products for deleting data of an object within a multi-tenant database. Described is a mechanism for performing operations such as an efficient delete operation by introducing a new delete operation (or method) that is configured to allow a data structure such as an object to identify one or more records to be deleted. In order to ensure that the operation is efficient, the mechanism may determine characteristics of a data store and determine whether the information provided within the data structure provides an efficient identification of the data to be deleted. Upon a successful validation, an initial delete request may be translated to an appropriate delete operation for the underlying database.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 10, 2021
    Assignee: salesforce.com, inc.
    Inventors: Jan Asita Fernando, Cody Marcel, Sahil Ramrakhyani, Samarpan Jain, Brian Esserlieu, James Ferguson, Saikiran Perumala, Charles Fineman, Jay Hurst, Seshank Kalvala
  • Patent number: 11068351
    Abstract: Switching from primary to backup data storage by preparing a backup copy of multiple data sets, where, prior to the preparing, the backup copy is updated in accordance with a backup protocol specifying synchronously updating the backup copy to reflect changes made to one type of data stored in a primary copy of the data sets, and asynchronously updating the backup copy to reflect changes made to another type of data stored in the primary copy, and where the preparing includes identifying any inconsistency in any interdependent data in the data sets of the backup copy in accordance with a predefined schema of interdependent data in the data sets, and correcting any identified inconsistency in the data sets of the backup copy in accordance with a predefined inconsistency correction protocol, and causing the backup copy to be used in place of the primary copy for directly servicing data transactions.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dean Har'el Lorenz, Roie Melamed, Alexey Roytman, Aidan Shribman
  • Patent number: 11068394
    Abstract: Provided is a neural network system for processing data transferred from an external memory. The neural network system includes an internal memory storing input data transferred from the external memory, an operator performing a multidimensional matrix operation by using the input data of the internal memory and transferring a result of the multidimensional array operation as output data to the internal memory, and a data moving controller controlling an exchange of the input data or the output data between the external memory and the internal memory. The data moving controller reorders a dimension order with respect to an access address of the external memory to generate an access address of the internal memory, for the multidimensional matrix operation.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 20, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeongmin Yang, Young-Su Kwon
  • Patent number: 11068191
    Abstract: In one aspect, adaptive replication modes in a storage system are provided. An aspect includes during an active replication session in which a first type of replication is performed at the storage system, monitoring write input/output (IO) operations, collecting data from the write IO operations, and determining, from the collected data, write IO latency. Upon determining that a threshold value has been met from the write IO latency, where the threshold value is defined for the first type of replication, an aspect includes automatically switching from the first type of replication to a second type of replication. The second type of replication is configured to compensate for operational deficiencies detected in response to the write IO latency.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 20, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Xiangping Chen, Ying Hu