Abstract: The disclosed technology relates determining a first subset of a plurality drives having a first zone size and a second subset of the plurality of drives having a second zone size different from the first zone size, within a redundant array of independent disks (RAID) group. A prevailing zone size between the first zone size and the second zone size is determined. One or more logical zones within the determined first subset of the plurality of drives and the determined second subset of the plurality of drives for a received input-output operation is reserved based on the determined prevailing zone size. The received input-output operation is completed within the reserved one or more logical zones within the determined first subset of the plurality of drives and the determined second subset of the plurality of drives.

Abstract: An apparatus for identification of an input data against one or more learned signals is provided. The apparatus comprising a number of computational cores, each core comprises properties having at least some statistical independency from other of the computational, the properties being set independently of each other core, each core being able to independently produce an output indicating recognition of a previously learned signal, the apparatus being further configured to process the produced outputs from the number of computational cores and determining an identification of the input data based the produced outputs.

Abstract: A real time, on-the-fly data encryption system is shown operable to encrypt and decrypt the data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.

Abstract: Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

Abstract: Systems and methods for managing keys in a computer memory are described. In some embodiments, location addresses are determined for two key elements. A periodic time interval that is based on a time duration for performing a transaction involving a distance between the key elements is determined. One key element may be stored at a location address and then relocated to another location address after the periodic time interval has passed. In some embodiments, areas the computer memory may remain static during relocation of the key element.

Abstract: A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.

Abstract: A system and methods are provided for using order descriptor identifiers in relation to orders being used in trading strategies. According to one example method, when a hedge order is submitted upon detecting a fill of another order, the hedge order includes one or more order descriptor identifiers conveying a purpose of the hedge order to a user. The order descriptor identifiers can be used to search for desired orders and perform more effective order management and post trade analysis.

Abstract: A write request is determined to comprise at least a partial translation unit. A size of the partial translation unit is smaller than a size of a predefined translation unit. A first entry in a translation map is identified. The translation map maps a plurality of translation units to a plurality of physical blocks. The first entry identifies a first physical block corresponding to the predefined translation unit. A second entry in the translation map is created. The second entry identifies a second physical block. An association between the first entry and the second entry is created, such that the second entry corresponds to the predefined translation unit. A write operation is performed to write a set of data corresponding to the partial translation unit to the second physical block.

Abstract: Host I/O requests directed to a logical storage volume are initially processed by accessing physical pages of non-volatile data storage having a default page size. An indication of an optimal page size for the logical storage volume is received, and the size of the physical pages of non-volatile data storage accessed to process host I/O requests directed to the logical storage volume is changed from the default page size to the optimal page size for the logical storage volume. The default page size is changed to the optimal page size for the logical storage volume by changing a size of physical pages of non-volatile data storage indicated by a mapping structure that maps logical addresses in an address space the logical storage volume to corresponding physical pages of non-volatile data storage from the default page size to the optimal page size for the logical storage volume.

Abstract: A white balance adjusting system for a display device includes a control member including a register storing white balance control commands and a preset white balance lookup table. A built-in self-test module is coupled to the control member and configured to store a test pattern. A first storage element is disposed in the display device. An optical sensor is configured to measure brightness and chroma data of the screen according to the test pattern. An external control device is operated by the control member to execute the white balance control commands so that white balance adjustment is implemented according to the preset white balance lookup table and the brightness and the chroma data of the screen, and a corrected white balance lookup table is produced. The corrected white balance lookup table is stored in the first storage element and provided to update the preset white balance lookup table.

Abstract: A method of task-based cache isolation includes: storing, in association with a cache controller, (i) a plurality of mask descriptors representing respective portions of a cache memory, and (ii) for each mask descriptor, a mask identifier; receiving, at the cache controller, a memory transaction request containing a memory address and an active one of the mask identifiers; retrieving, at the cache controller, an active one of the mask descriptors corresponding to the active mask identifier; generating, based on the memory address and the active mask descriptor, an index identifier corresponding to a cache element within the portion of the cache memory represented by the active mask descriptor; and applying the memory transaction to the cache memory at the index identifier.

Abstract: One bottleneck in 5G uplink messaging is the 6-byte MAC address of the recipient. Disclosed is a database, maintained by a base station, for each user. The database may include addresses of potential interest to the user, along with a code or index associated with each address. The user can then cite the code or index instead of the full MAC address in messages, and the base station can look up the destination address in the database according to the code or index. The database may include the user's contacts, return addresses of prior incoming messages, destination addresses of prior outgoing messages, and optionally certain administrative addresses. Versions include codes for commands, codes for emergencies, codes to modify the database, and algorithms developed by AI (artificial intelligence). The index may be provided as a scheduling request message, or on the random access channel concurrently with a scheduling request, or associated with a BSR message, or otherwise.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

Abstract: Techniques and apparatus for providing access to data in a plurality of storage formats are described. In one embodiment, for example, an apparatus may include logic, at least a portion of comprised in hardware coupled to the at least one memory, to determine a first storage format of a database operation on a database having a second storage format, and perform a format conversion process responsive to the first storage format being different than the second storage format, the format conversion process to translate a virtual address of the database operation to a physical address, and determine a converted physical address comprising a memory address according to the first storage format. Other embodiments are described and claimed.

Abstract: Methods, systems, and media for improving computer security and performance of security are disclosed. In one example, a computer security system comprises a key management monitor, and two key elements comprising a first key element and a second key element. The first key element is stored at a first location address within a computer memory and the second key element is stored at a second location address. The key management monitor is configured to determine or receive a time duration for performing a data dump of contents of the computer memory. In one example, the key management monitor is further configured to control a location of the first key element within the computer memory, wherein the location address of the first key element is changed within a time period that is less than the time duration for performing the data dump of contents of the computer memory.

Abstract: Systems, apparatuses and methods may provide for technology that detects a misalignment condition, wherein the misalignment condition includes a memory map being misaligned with a granularity of a register, automatically appends a protected range to the memory map, wherein the protected range eliminates the misalignment condition, and defines an operational characteristic of the memory map via the register. In one example, the protected range is a non-existent memory (NXM) range appended via a source address decoder (SAD) rule, the register is a memory type range register (MTRR), and the operational characteristic is a cache characteristic.

Abstract: A semiconductor device includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

Abstract: This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.

Abstract: Provided are systems and methods for an integrated circuit comprising a search engine, which a memory controller can use to manage a page table. In various implementations, the search engine can generate a series of read transactions to read the page table, which is stored in a memory. Each page table entry includes an address translation for processor memory. The memory controller may periodically change the address translations. The search engine can further determine whether data read from an entry in the page table corresponds to a search parameter. The search engine can further output a response, where the response is affirmative when the data read from the entry corresponds to the search parameters, and where the response is negative when no data read from any entry corresponds to the search parameter.

Abstract: Computer systems and associated methods are disclosed for performing custom code transformations using a compiler that does not support the custom transformations. In embodiments, a wrapper program intercepts a command to the compiler. The wrapper program generates intermediate code using the compiler in accordance with the command. The wrapper program then performs the code transformations on the intermediate code using a code transformer, for example, by performing a search and replace operation to replace particular code sequences in the intermediate code. The wrapper program then generates the binary code from the transformed intermediate code in accordance with the command. In this manner, software may be compiled with the custom code transformations without extensive changes to the source code or the compiler. In one application, the technique may be used to build a hot patch that applies a security update to a software using the software's original compiler.

Abstract: The disclosure relates to a memory access unit. One example embodiment is a memory access unit, for providing read-access to read an item from an arbitrary location in a physical memory, independently of addressable locations of the physical memory. The item includes a first number of bits and each addressable location of the physical memory includes a second number of bits. The second number of bits is different from the first number of bits. The memory access unit includes an address input, an address interpreter, an address output, a memory output, a data formatter, and a data output.

Abstract: A prefetcher maintains the state of stored prefetch information, such as a prefetch confidence level, when a prefetch would cross a memory page boundary. The maintained prefetch information can be used both to identify whether the stride pattern for a particular sequence of demand requests persists after the memory page boundary has been crossed, and to continue to issue prefetch requests according to the identified pattern. The prefetcher therefore does not have re-identify a stride pattern each time a page boundary is crossed by a sequence of demand requests, thereby improving the efficiency and accuracy of the prefetcher.

Abstract: The present invention relates to a device and a method for monitoring resources in a full virtualization system, the device and method generating a file table by parsing file information, generating a memory table when a memory is allocated, and then determining whether to execute a command by a process unit with reference to the file table and the memory table when the command is generated from a guest operating system or an application such that a virtual machine monitor is requested to execute the command.

Abstract: A data storage device includes a cache for a data storage and a processor. The data storage includes an object storage. The processor obtains cache hardware heuristics data for a first time period; makes a first determination that the cache hardware heuristics data for the first time period does not meet a goal associated with the first time period; and populates the cache using a reduced size index cache in response to the first determination during a second time period.

Abstract: Area-efficient logic circuitry for checkpointing a register file using a mapper in an “in-order” CPU (central processing unit). A pair of flops with a shared master stage latch circuit implement storage elements in a register file and a checkpointed copy of the same register file.

Abstract: The detection of a fault of the address signal system in memory access is aimed at. A semiconductor device according to the present invention includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

Abstract: In one embodiment, a processor includes logic, responsive to a first instruction, to perform an operation on a first source operand and a second source operand associated with the first instruction and write a result of the operation to a destination location comprising a third source operand. The write may be a partial write of the destination location to maintain an unmodified portion of the third source operand. Other embodiments are described and claimed.

Abstract: The system, process, and methods herein describe a mechanism for aligning IOs with block sizes. The alignment may occur on a storage system as part of a continuous replication process. The TO offset may be rounded down, and the size may be rounded up, so that each is a multiple of the block size.

Abstract: An apparatus (100) comprising a programmable memory transfer request processing (PMTRP) unit (120) and a programmable direct memory access (PDMA) unit (140). The PMTRP unit (120) comprises at least one programmable region descriptor (123). The PDMA unit (140) comprises at least one programmable memory-to-memory transfer control descriptor (148, 149, 150). The PDMA unit (140) is adapted to send (143) a memory transfer request to the PMTRP unit (120). The PMTRP unit (120) is adapted to receive (134) and successfully process a memory transfer request issued by the PDMA unit (120) that is addressed to a memory location that is associated with a portion of at least one of the at least one region descriptor (123) of the PMTRP unit (120).

Abstract: A processing system includes a processing core and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store a page table entry (PTE) comprising a mapping from a virtual memory page referenced by an application running on the processing core to an identifier of a memory frame of a memory, a first plurality of access permission flags associated with accessing the memory frame under a first privilege mode, and a second plurality of access permission flags associated with accessing the memory under a second privilege mode.

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an input/output (I/O) unit, configured to perform I/O operations via an I/O bus coupling an out-of-order processor to I/O resources.

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an input/output (I/O) unit, configured to perform I/O operations via an I/O bus coupling an out-of-order processor to I/O resources.

Abstract: A loop alignment instruction indicates a base address of an array as a first operand, an iteration limit of a loop as a second operand, and a destination. The loop contains iterations and each iteration includes a data element of the array. A processor receives the loop alignment instruction, decodes the instruction for execution, and stores a result of the execution in the destination. The result indicates the number of data elements at a beginning of the array that are to be handled separately from a remaining portion of the array, such that the base address of the remaining portion of the array aligns with an alignment width.

Abstract: A method and a system embodying the method for a memory address alignment, comprising configuring one or more naturally aligned buffer structure(s); providing a return address pointer in a buffer of one of the one or more naturally aligned buffer structure(s); determining a configuration of the one of the one or more naturally aligned buffer structure(s); applying a modulo arithmetic to the return address and at least one parameter of the determined configuration; and providing a stacked address pointer determined in accordance with the applied modulo arithmetic, is disclosed.

Abstract: Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

Abstract: A data processing system 2 includes a stack pointer register 26, 28, 30, 32 storing a stack pointer value for use in stack access operations to a stack data store 44, 46, 48, 50. Stack alignment checking circuitry 36 which is selectively disabled may be provided to check memory address alignment of the stack pointer value associated with a stack memory access. The action of the stack alignment checking circuitry 36 is independent of any further other alignment checking performed in respect of all memory accesses. Thus, general alignment checking circuitry 38 may be provided and independently selectively disabled in respect of any memory access.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and sorts data blocks of write data received in the random access memory of the data storage. A storage controller is communicatively coupled to the random access memory and the data storage and being configured to write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses. A method and processor-implemented process provide for sorting data blocks of write data received in random access memory of data storage. The method and processor-implemented process write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses.

Abstract: In one embodiment, an apparatus includes one or more memory devices, each memory device having non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices, the memory controller being configured to receive data to be stored to the one or more memory devices, store read-hot data within one error correction code (ECC) codeword as aligned data, and store read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data. According to another embodiment, a method for storing data to non-volatile memory includes receiving data to store to one or more memory devices, each memory device including non-volatile memory configured to store data, storing read-hot data within one ECC codeword as aligned data, and storing read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data.

Abstract: Systems and methods for generating synthetic backups and for consolidating a chain of related backups. The chain of related backups is merged on the fly to create a backup stream. A block allocation table (BAT) may be identified for each backup to be consolidated into a synthetic backup, and BAT entries from each backup may be merged or combined to create a new BAT table associated with the synthetic backup. The data included in the related backups may be reformatted on the fly from big endian to little endian or vice versa. The backup stream is stored on a target device or volume.

Abstract: Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The merging circuitry is configured to merge an output vector data sample set from execution units as a result of performing vector processing operations in-flight while the output vector data sample set is being provided over the output data flow paths from the execution units to the vector data memory to be stored. The merged output vector data sample set is stored in a merged form in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in execution units.

Abstract: Various systems and methods to perform efficiently a first processing task in conjunction with a plurality of data sets. A first code sequence comprises a plurality of general commands, and a specific command including a description of a first data processing task to be performed in conjunction with the data sets. The general commands are received and processed in a standard manner. The specific command is identified automatically by its nature, and the description within the specific command is then converted into a first sequence of executable instructions executable by a plurality of compute elements holding the plurality of data sets. The ultimate result is an efficient implementation of the first processing task. In some embodiments, the implementation of the first processing task is assisted by a pre-defined procedure that allocates the data sets to the compute elements and shares instances of executable instructions with the compute elements.

Abstract: Generating SIMD code from code statements that include non-isomorphic code statements. Code statements are received, each code statement has one or more operators in a respective operator order and each operator has a type and associated operands. At least two code statements among the code statements received have an operator of the same type in a different operator order position. A first operator order position is identified for the operators of the same type in each of the code statements. For each of the code statements, code is generated for operators and their associated operands having operator order positions preceding the first operator order positions. SIMD code is generated at least based on the identified first operator order positions, the corresponding operator type, and the operands associated with the operator type at the identified operator order positions.

Abstract: A processor, system, and method are described for continued retirement of operations during a commit of a speculative region of program code. For example, one embodiment of a method comprises the operations of identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete.

Abstract: An aspect includes implementing endian-mode-sensitive memory instructions for a vector processor. One such system includes a byte addressable memory and a processor. The processor includes a register that includes a plurality of byte elements 0 to S. The system is configured to perform a method that includes obtaining an instruction by the processor and determining that the instruction is a memory access instruction specifying the register and a memory address. In response to the determination that the instruction is a memory access instruction and independent of a current global endian mode setting that is selectable in the processor, the memory access instruction is executed by copying the byte data between the memory and the register so that the byte element n of the register corresponds to the memory address+n for n=0 to S.

Abstract: Generating SIMD code from code statements that include non-isomorphic code statements. Code statements are received, each code statement has one or more operators in a respective operator order and each operator has a type and associated operands. At least two code statements among the code statements received have an operator of the same type in a different operator order position. A first operator order position is identified for the operators of the same type in each of the code statements. For each of the code statements, code is generated for operators and their associated operands having operator order positions preceding the first operator order positions. SIMD code is generated at least based on the identified first operator order positions, the corresponding operator type, and the operands associated with the operator type at the identified operator order positions.