Address Formation Patents (Class 711/200)
  • Patent number: 11360672
    Abstract: Data is copied, to a first group of data blocks in a first plurality of groups of unmapped data blocks, from a second group of data blocks in a second plurality of groups of mapped data blocks. Upon copying data to the first group of data blocks from the second group of data blocks, the first group of data blocks is included in the second plurality of groups of mapped data blocks. Upon including the first group of data blocks in the second plurality of groups of mapped data blocks, a wear leveling operation is performed on the first group of data blocks, wherein performing the wear leveling operation comprises determining a base address of the first group of data blocks, the base address indicating a location at which the first group of data blocks begins. A request to access subsequent data at a logical address associated with a data block included in the first group of data blocks is received.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fangfang Zhu, Jiangli Zhu, Ning Chen, Ying Yu Tai
  • Patent number: 11316827
    Abstract: Examples relate to operating mode configuration. An apparatus may include a memory resource storing executable instructions. Instructions may include instructions to receive a message from a host computing device coupled to the apparatus. The message may include a Host Based Media Access Control Address (HBMA). Instructions may further include instructions to configure the apparatus using the HBMA in response to a determination that the apparatus is in a particular operating mode. The apparatus may further include a processing resource to execute the instructions stored on the memory resource.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 26, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey K. Jeansonne, Isaac Lagnado, Roger D. Benson
  • Patent number: 11297012
    Abstract: A buffer logic unit of a packet processing device including a power gate controller. The buffer logic unit for organizing and/or allocating available pages to packets for storing the packet data based on which of a plurality of separately accessible physical memories that pages are associated with. As a result, the power gate controller is able to more efficiently cut off power from one or more of the physical memories.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: April 5, 2022
    Assignee: Marvell Asia PTE, LTD.
    Inventor: Enrique Musoll
  • Patent number: 11199975
    Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: December 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daehoon Na, Jangwoo Lee, Jeongdon Ihm
  • Patent number: 11133075
    Abstract: Apparatus and methods are disclosed including a memory device or a memory controller configured to receive, from a host device over a host interface, a request for a device descriptor of a memory device, and to send to the host, over the host interface, the device descriptor, the device descriptor including voltage supply capability fields that are set to indicate supported voltages of the memory device, the supported voltages selected from a plurality of discrete voltages. The host device can utilize the supported voltages to supply an appropriate voltage to the memory device. Methods of operation are disclosed, as well as machine-readable medium, a host computing device, and other embodiments.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Greg A. Blodgett, Sebastien Andre Jean
  • Patent number: 11119923
    Abstract: A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of the program, the critical section being a portion of the program that confines access to shared, writeable data.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: September 14, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amin Farmahini Farahani, Nuwan Jayasena
  • Patent number: 11119561
    Abstract: Systems, devices, and methods related to non-volatile memory are described. A non-volatile memory array may be employed as a main memory array for a system on a chip (SoC) or processor. A controller may interface between the non-volatile memory array and the SoC or processor using a protocol agnostic to characteristics of non-volatile memory operation including different page sizes or access time requirements, etc. A virtual memory bank at the controller may be employed to facilitate operations between the SoC or processor and the non-volatile memory array. The controller may be coupled with a buffer to facilitate rapid data operation, and the controller may be configured to selectively access data at the non-volatile array to account for data stored in the virtual memory bank or the buffer. The controller, the virtual memory bank, and the buffer may be configured on one chip separate from the SoC or processor.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Robert Nasry Hasbun
  • Patent number: 11099984
    Abstract: To perform permutation processing at high speed. A number-of-elements determination unit (22) calculates the number of elements to be contained in each allocation destination. A start position determination unit (23) calculates a start position corresponding to each allocation destination. An allocation destination determination unit (24) calculates a sequence of values representing allocation destinations in a buffer. A permutation generating unit (25) calculates a sequence of values representing permutation destinations within the respective allocation destination. An initial position setting unit (31) sets the start position into a value indicating a position within processing corresponding to each allocation destination. A rearrangement unit (32) sets the elements of a vector into the respective allocation destinations in the buffer. A permutation execution unit (33) generates an output vector by executing an arbitrary inverse permutation algorithm on the respective allocation destinations.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: August 24, 2021
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventor: Dai Ikarashi
  • Patent number: 11074014
    Abstract: An apparatus includes a data storage medium having a plurality of tracks. The apparatus also includes a write history buffer configured to store a history of prior write commands to the plurality of tracks. The apparatus further includes a controller communicatively coupled to the write history buffer. The controller is configured to receive a new write command directed to a first portion of a first track of the plurality of tracks on the data storage medium. The controller is further configured to determine whether to update ATI contribution measures from the first track based on the history of write commands to the first track.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 27, 2021
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jian Qiang, Mark A. Gaertner, Kay Hee Tang, Chee Hou Peng
  • Patent number: 11044227
    Abstract: Approaches for, and articles of manufacturer that embody, dynamic assignment of a MAC address. A remote PHY node may comprise a non-volatile memory and a network element that comprises a CPU. For example, the network element may be a remote PHY device, an Ethernet switch, a Remote MACPHY Device (RMD), a Passive Optical Network (PON) Optical Line Terminal (OLT), a Passive Optical Network (PON) Optical Network Unit (ONU), or a Wi-Fi hot spot router. A communication link exists between the CPU of the network element and the non-volatile memory of the remote PHY node. A module on the network element causes the network element to retrieve, across the communication link, a MAC address from the non-volatile memory of the remote PHY node and adopt the MAC address to identify itself any time that the network element reboots.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: June 22, 2021
    Assignee: Harmonic, Inc.
    Inventor: Adi Bonen
  • Patent number: 11023230
    Abstract: The apparatus and method for calculating and retaining a bound on error during floating-point operations inserts an additional bounding field into the standard floating-point format that records the retained significant bits of the calculation with notification upon insufficient retention. The bounding field, accounting for both rounding and cancellation errors, includes the lost bits D Field and the accumulated rounding error R Field. The D Field states the number of bits in the floating-point representation that are no longer meaningful. The bounds on the represented real value are determined by the truncated floating-point value and the addition of the error determined by the number of lost bits. The true, real value is absolutely contained by these bounds. The allowable loss (optionally programmable) of significant digits provides a fail-safe, real-time notification of loss of significant digits. This allows representation of real numbers accurate to the last digit.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: June 1, 2021
    Inventor: Alan A. Jorgensen
  • Patent number: 11018898
    Abstract: The subject technology addresses a need for improving utilization of network bandwidth in a multicast network environment. More specifically, the disclosed technology provides solutions for extending multipathing to tenant multicast traffic in an overlay network, which enables greater bandwidth utilization for multicast traffic. In some aspects, nodes in the overlay network can be connected by virtual or logical links, each of which corresponds to a path, perhaps through many physical links, in the underlying network.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: May 25, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Kit Chiu Chu, Thomas J. Edsall, Navindra Yadav, Francisco M. Matus, Krishna Doddapaneni, Satyam Sinha, Sameer Merchant
  • Patent number: 10901696
    Abstract: A computer-implemented computer documentation validation method, the method comprising: manipulating a user interface of an operating system by taking control of a user input device to execute a command of a computer software documentation on behalf of the user; and outputting an error code when a failure is a result of the executed command.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vittorio Castelli, Radu Florian, Taesun Moon, Avirup Sil
  • Patent number: 10896127
    Abstract: A system and method for identifying from an address an appropriate target node and a location in that node that holds desired data related to that address is provided. The system and method includes a logical address generator that generates a logical address. The system and method includes a subspace index extraction module that extracts a subspace index from the logical address. The system and method includes a subspace configuration table that retrieves a plurality of parameters of the subspace index to locate the desired data.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: January 19, 2021
    Assignee: Lucata Corporation
    Inventor: Peter M. Kogge
  • Patent number: 10853256
    Abstract: Apparatuses and methods of operating apparatus are disclosed. A processing element performs data processing operations with respect to data items stored in data storage. In a first mode the processing element references the data items using physical addresses and in a second mode the processing element references the data items using virtual addresses. A data access request handling unit receives data access requests issued by the processing element and cache stores cache lines of temporary copies of the data items retrieved from the data storage, wherein a cache line in which a data item is stored in the cache is selected in dependence on an address index portion.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 1, 2020
    Assignee: Arm Limited
    Inventors: Andrew Merritt, Alex Beharrell, Saqib Rashid, Raghavendra Adiga Bandimutt
  • Patent number: 10776190
    Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Tomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
  • Patent number: 10740140
    Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor for processing instructions, the processor having a history buffer having a plurality of entries for storing information associated with a processor instruction evicted from a logical register, the history buffer having at least one recovery port; a logical register mapper for recovering information from the history buffer, the mapper having restore ports to recover information from the history buffer; and a restore multiplexor configured to receive as inputs information from one or more of the history buffer recovery ports, and configured to output information to one or more of the logical register mapper restore ports. The processor, system and/or method configured to improve flush recovery bandwidth.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
  • Patent number: 10733111
    Abstract: Apparatus comprises input circuitry to receive a translation request defining an input memory address within an input memory address space; and address translation circuitry comprising: permission circuitry to detect whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and output circuitry to provide an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 4, 2020
    Assignee: ARM Limited
    Inventors: Jason Parker, Andrew Brookfield Swaine
  • Patent number: 10713172
    Abstract: A cache memory for a processor including an arbiter, a tag array and a request queue. The arbiter arbitrates among multiple memory access requests and provides a selected memory access request. The tag array has a first read port receiving the selected memory access request and has a second read port receiving a prefetch request from a prefetcher. The tag array makes a hit or miss determination of whether data requested by the selected memory access request or the prefetch request is stored in a corresponding data array. The request queue has a first write port for receiving the selected memory access request when it misses in the tag array, and has a second write port for receiving the prefetch request when it misses in the tag array. The additional read and write ports provide a separate and independent pipeline path for handing prefetch requests.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 14, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Qianli Di, Weili Li
  • Patent number: 10714124
    Abstract: According to one embodiment, in a storage device, a selection circuit selects one mapping rule from a plurality of mapping rules in which each of bit labels having a bit length of (n+1) or more is mapped to n M-ary symbols, when M is defined as an integer of 3 or more and n is defined as an integer of or more. A first conversion circuit converts a data block in data into an M-ary symbol sequence using the selected one mapping rule. A second conversion circuit converts the converted M-ary symbol sequence into an M-step pulse width signal. The recording medium records the converted M-step pulse width signal. A readback circuit equalizes the signal read from the recording medium to the M-ary symbol sequence and restores the data.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: July 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kohsuke Harada
  • Patent number: 10649841
    Abstract: Disclosed are methods and devices for supporting multiple page lengths with unique error correction coding via Galois field dimension folding. In one embodiment, a method comprises receiving a write instruction, the write instruction including user data; generating extended user data based on the user data, the extended user data including at least one symbol comprising a bit of the user data and a pre-stored bit pattern; generating parity data by encoding the extended user data; generating parity extension data by encoding the bit of the user data; writing a codeword to a page of a non-volatile memory device, the codeword including the parity extension data, the user data, and the parity data.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 12, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventor: Shu Li
  • Patent number: 10628202
    Abstract: This disclosure generally relates to hypervisor memory virtualization. Techniques disclosed herein improve peripheral component interconnect express (PCI-e) device interoperability with a virtual machine. As an example, when a direct-memory access request is received from a PCI-e device but the target memory is currently unmapped, an indication may be provided to a memory paging processor so as to page-in the memory, such that the PCI-e device may continue to function normally. In some examples, the access request may be buffered and replayed once the memory is paged-in, or the access request may be retried, among other examples.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: April 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Aditya Bhandari, Bruce J. Sherwin, Jr., Xin David Zhang
  • Patent number: 10623206
    Abstract: The subject technology addresses a need for improving utilization of network bandwidth in a multicast network environment. More specifically, the disclosed technology provides solutions for extending multipathing to tenant multicast traffic in an overlay network, which enables greater bandwidth utilization for multicast traffic. In some aspects, nodes in the overlay network can be connected by virtual or logical links, each of which corresponds to a path, perhaps through many physical links, in the underlying network.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 14, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Kit Chiu Chu, Thomas J. Edsall, Navindra Yadav, Francisco M. Matus, Krishna Doddapaneni, Satyam Sinha, Sameer Merchant
  • Patent number: 10600493
    Abstract: A semiconductor device includes a mode control circuit suitable for selectively masking first and second initial input control signals and an initial feedback signal depending on a mode control signal and outputting first and second input control signals and a feedback signal; and a multiple-input shift register (MISR) circuit including a plurality of input selectors and a plurality of registers which are alternatively coupled in series with one another, wherein each of the plurality of input selectors combines an output signal of a previous stage register among the plurality of registers and an external input signal depending on the first and second input control signals and the feedback signal and provides an input signal for a next stage register among the plurality of registers.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Young-Jun Ku
  • Patent number: 10540143
    Abstract: The apparatus and method for calculating and retaining a bound on error during floating point operations inserts an additional bounding field into the standard floating-point format that records the retained significant bits of the calculation with notification upon insufficient retention. The bounding field, accounting for both rounding and cancellation errors, includes the lost bits D Field and the accumulated rounding error R Field. The D Field states the number of bits in the floating point representation that are no longer meaningful. The bounds on the represented real value are determined by the truncated floating point value and the addition of the error determined by the number of lost bits. The true, real value is absolutely contained by these bounds. The allowable loss (optionally programmable) of significant digits provides a fail-safe, real-time notification of loss of significant digits. This allows representation of real numbers accurate to the last digit.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 21, 2020
    Inventor: Alan A. Jorgensen
  • Patent number: 10509666
    Abstract: A register protection mechanism for a virtualized accelerated processing device (“APD”) is disclosed. The mechanism protects registers of the accelerated processing device designated as physical-function-or-virtual-function registers (“PF-or-VF* registers”), which are single architectural instance registers that are shared among different functions that share the APD in a virtualization scheme whereby each function can maintain a different value in these registers. The protection mechanism for these registers comprises comparing the function associated with the memory address specified by a particular register access request to the “currently active” function for the APD and disallowing the register access request if a match does not occur.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: December 17, 2019
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Anthony Asaro, Yinan Jiang, Kelly Donald Clark Zytaruk
  • Patent number: 10503537
    Abstract: This disclosure generally relates to hypervisor memory virtualization. Techniques disclosed herein improve peripheral component interconnect express (PCI-e) device interoperability with a virtual machine. As an example, when a direct-memory access request is received from a PCI-e device but the target memory is currently unmapped, an indication may be provided to a memory paging processor so as to page-in the memory, such that the PCI-e device may continue to function normally. In some examples, the access request may be buffered and replayed once the memory is paged-in, or the access request may be retried, among other examples.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 10, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Aditya Bhandari, Bruce J. Sherwin, Jr., Xin David Zhang
  • Patent number: 10430345
    Abstract: A method of operating an electronic device and the electronic device are provided. The method includes mounting at least one lower file system, which is configured to generate a file object managing a page cache, and mounting a highest file system, to which a virtual file system directly accesses, at a higher layer of a layer corresponding to the lower file system; in response to a file mapping request of a software program, generating a virtual memory area including a virtual address for a file corresponding to the file mapping request; and generating a first virtual address link between a file object of at least one lower file system having a page cache of a file corresponding to the file mapping request and the virtual memory area.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Woo-Joong Lee, Sang-Woo Lee, Jun-Beom Yeom, Min-Jung Kim
  • Patent number: 10402252
    Abstract: A peripheral device may implement alternative reporting of errors and other events detected at the peripheral device. A peripheral device may monitor the operations of the peripheral device for reporting events. Upon detecting a reporting event, a notification of the reporting event may be generated and sent to a remote data store. The remote data store may store the reporting event and evaluate the reporting event for a responsive action that may be performed. If a responsive action is determined, then the remote data store may direct the performance of the responsive action. The remote data store may provide access to stored reporting events for a peripheral device.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: September 3, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Adi Habusha, Eric Jason Brandwine
  • Patent number: 10379867
    Abstract: Techniques are disclosed for performing a flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying one or more entries of the HB to restore to a register file in the processing unit. For each of the one or more HB entries, a determination is made whether to send the HB entry to the register file via a first restore bus or via a second restore bus, different from the first restore bus, based on contents of the HB entry. Each of the one or more HB entries is then sent to the register file via one of the first restore bus or the second restore bus, based on the determination.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle, Brian D. Barrick, Sundeep Chadha, Albert J. Van Norstrand, Jr.
  • Patent number: 10324860
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 18, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 10282205
    Abstract: Method and system for restoring data to a register file of a processing unit are provided. A history buffer entry (HBE) is marked for restoration to a register file entry. Result data and control information is sent from the HBE to an Issue Queue (ISQ). The ISQ issues an instruction for loading the result data into the register file entry based on the control information. A write back operation is performed to restore the result data to the register file entry, in response to issuing of the instruction.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Susan E. Eisen, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 10236066
    Abstract: A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 19, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Michele Alessandro Carrano, Gaetano Di Stefano, Roberto Sebastiano Ruggirello
  • Patent number: 10223959
    Abstract: A portable information handling system having rotationally coupled housing portions disposes first and second OLED display films in an overlapped configuration having the display films slide relative to each other as the housing portions rotate. Presentation of visual images at one or both of the OLED display films in the overlapped portion is adjusted to blend with the images presented at non-overlapping portions of the OLED display films.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: March 5, 2019
    Assignee: Dell Products L.P.
    Inventors: Deeder M. Aurongzeb, Stefan Peana, David M. Meyers
  • Patent number: 10187463
    Abstract: An example method includes: identifying, by a new node, an address of a shared data store comprising information on a current membership in a peer-to-peer system, wherein the shared data store is shared by a plurality of nodes that are current members of the peer-to-peer system, wherein the shared data store is a container for storing data in a storage cloud; sending, by the new node, a first message comprising an address of the new node to the shared data store; requesting, by the new node, at least one membership data structure from the shared data store; receiving, by the new node, a second message comprising the at least one membership data structure; generating, by the new node, a new membership data structure comprising the address of the new node and the plurality of addresses for the plurality of nodes identified in the at least one membership data structure; sending, by the new node, a third message comprising the new membership data structure to the shared data store; and joining, by the new node, t
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 22, 2019
    Assignee: Red Hat, Inc.
    Inventors: Manik Surtani, Bela Ban
  • Patent number: 10175908
    Abstract: A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol. The commands include a write command with blocks of data to be stored in the memory device and contextual file system data for the blocks of data. The contextual file system data includes file metadata, file attributes, or both that identify an association of the one or more blocks of data with a file. The file is made up of the one or more blocks of data. The controller identifies the association of the one or more blocks of data with the file and executes the one or more commands, such that the one or more blocks of data are stored in the memory device with a placement based upon the association.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Graziano Mirichigni, Gianfranco Santopietro, Gianfranco Ferrante, Emanuele Confalonieri
  • Patent number: 10102141
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Brent S. Baxter, Clifford D. Hall, Prashant Sethi, William H. Clifford
  • Patent number: 10049048
    Abstract: A processor cache is logically partitioned into a main partition, located in the cache itself, and an enclave partition, located within an enclave, that is, a hardware-enforced protected region of an address space of a memory. This extends the secure address space usable by and for an application such as a software cryptoprocessor that is to execute only in secure regions of cache or memory.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: August 14, 2018
    Assignee: Facebook, Inc.
    Inventors: Oded Horovitz, Stephen A. Weis, Sahil Rihan, Carl A. Waldspurger
  • Patent number: 10019376
    Abstract: A memory system includes a memory device including first and second storage regions, each comprising a plurality of memory blocks and a controller suitable for selecting a first mode or a second mode based on a method for accessing data stored in the memory device and mapping a logical address of the data into a physical address of the first storage region in the first mode and into a physical address of the second storage region in the second mode.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: July 10, 2018
    Assignee: SK Hynix Inc.
    Inventor: Ambrose Gihan de Silva
  • Patent number: 10001928
    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided, wherein the memory storage device includes a rewritable non-volatile memory module and a buffer memory. The method includes: loading at least one first address information of at least one first logical-physical mapping table from the rewritable non-volatile memory module to a first buffer area when the memory storage device is operated in a first mode, wherein the first address information has a first data quantity; and loading at least one second address information of at least one second logical-physical mapping table from the rewritable non-volatile memory module to the first buffer area when the memory storage device is operated in a second mode, wherein the second address information has a second data quantity, and the first data quantity is less than the second data quantity.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: June 19, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9996353
    Abstract: An approach is provided in which a mapper control unit receives first dispatch information corresponding to a first instruction that identifies a first register and a first register type. The mapper control unit dynamically configures a first history buffer entry to support the first register type and, in turn, stores content from the first register into the first history buffer entry. The mapper control unit then receives second dispatch information corresponding to a second instruction that identifies a second register and a second register type, which is different than the first register type. The mapper control unit dynamically configures a second history buffer entry to support the second register type and, in turn, stores content from the second register into the second history buffer entry.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Kenneth L. Ward
  • Patent number: 9965418
    Abstract: A semiconductor device is provided which can quickly detect a malfunction of high priority modules by frequently checking a coupling state between the high priority modules and a communication bus. According to an embodiment, a host controller includes a module control circuit that performs data communication with a plurality of externally-provided modules through a communication bus, a coupling state check circuit which is coupled to the communication bus and which checks the presence or absence of a response from the modules, and selected from the modules based on information of a check list, and a control circuit that selectively causes the module control circuit and the coupling state check circuit to operate.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: May 8, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koichiro Noguchi
  • Patent number: 9921971
    Abstract: A method, medium, and system to receive a request to add a resource to a cache, the resource including a data object and a context item key associated with the resource and uniquely identifying a context of use referenced by the context item key; determine whether the resource is stored in the cache; store, in response to the determination that the resource is not stored in the cache, the resource in the cache; and add the context item key of the resource stored in the cache to a record of reference list of resources.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: March 20, 2018
    Assignee: SAP PORTAL ISRAEL LTD.
    Inventors: Eyal Nathan, Oleg Kossoy, David Malachi
  • Patent number: 9921897
    Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Manoj Dusanapudi, Shakti Kapoor, Paul F. Lecocq, John A. Schumann
  • Patent number: 9875132
    Abstract: In an example embodiment, a hypervisor exposes a virtual input-output memory management unit (IOMMU) to a first virtual machine. The first virtual machine includes a first guest operating system (OS). The hypervisor exposes a first virtual device to the first virtual machine. The hypervisor exposes a shared memory device to a second virtual machine. The second virtual machine includes a second guest OS. The hypervisor detects that the first guest OS modified the virtual IOMMU to provide access to a memory page of the first virtual machine. The hypervisor receives a base address from the second virtual machine. The base address is programmed into the shared memory device by the second virtual machine. The hypervisor maps the memory page into the second virtual machine at a page address, which is determined from the base address and a bus address.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: January 23, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 9864722
    Abstract: A communication system coupled to a data-acquisition circuit and to a data-processing circuit is provided, including at least one shift register, an addressing circuit and a multiplexer. The shift register includes a serial input for inputting and storing data in series, a serial output for outputting data in series, and parallel outputs for outputting data stored in the shift register in parallel. The addressing circuit is coupled to the shift register in order to identify the positions of stored data, and the multiplexer is coupled to the parallel outputs of the shift register in order to output the stored data to the data-processing circuit in series. Methods for communication between a data-acquisition circuit and a data-processing circuit are also provided.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 9, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Stephane Chevobbe, Marc Duranton
  • Patent number: 9817662
    Abstract: The apparatus and method for calculating and retaining a bound on error during floating point operations inserts an additional bounding field into the standard floating-point format that records the retained significant bits of the calculation with notification upon insufficient retention. The bounding field, which accounts for both rounding and cancellation errors, has two parts, the lost bits D Field and the accumulated rounding error R Field. The D Field states the number of bits in the floating point representation that are no longer meaningful. The bounds on the real value represented are determined from the truncated floating point value (first bound) and the addition of the error determined by the number of lost bits (second bound). The true, real value is absolutely contained by the first and second bounds. The allowed loss (optionally programmable) of significant bits provides a fail-safe, real-time notification of loss of significant bits.
    Type: Grant
    Filed: October 23, 2016
    Date of Patent: November 14, 2017
    Inventor: Alan A Jorgensen
  • Patent number: 9740613
    Abstract: A cache memory system has a first cache memory comprising one or more levels, to store data corresponding to addresses, a second cache memory comprising a plurality of non-volatile memory cells, which has higher speed capability than a main memory, has a larger capacity than the first cache memory and stores data corresponding to addresses, and a first storage to store address conversion information from a virtual address issued by a processor to a physical address and to store flag information indicating whether data is stored in the second cache memory by a page having a larger data amount than a cache line, the first cache memory being accessed by the cache line.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: August 22, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Noguchi, Shinobu Fujita
  • Patent number: 9712340
    Abstract: After acquiring a network address, a computing device accesses a shared data store and writes the network address to the shared data store. The computing device additionally reads a plurality of network addresses from the shared data store, wherein the plurality of network addresses are for a plurality of nodes that are members of a peer-to-peer system. The computing device then joins the peer-to-peer system based on communicating with the plurality of nodes using the plurality of network addresses.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: July 18, 2017
    Assignee: Red Hat, Inc.
    Inventors: Manik Surtani, Bela Ban
  • Patent number: 9654385
    Abstract: The subject technology addresses the need in the art for improving utilization of network bandwidth in a multicast network environment. More specifically, the disclosed technology addresses the need in the art for extending multipathing to tenant multicast traffic in an IP overlay network, which enables the network to fully utilize available bandwidth for multicast traffic. In some examples, nodes in the overlay network may be connected by virtual or logical links, each of which corresponds to a path, perhaps through many physical links, in the underlying network.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: May 16, 2017
    Assignee: Cisco Technology, Inc
    Inventors: Kit Chiu Chu, Thomas J. Edsall, Navindra Yadav, Francisco M. Matus, Krishna Doddapaneni, Satyam Sinha, Sameer Merchant