Abstract: The present invention is a system for implementing a meta-disk aggregation model for storage controllers. The system includes a storage controller configured for communicatively coupling with a server. The system further includes a meta-disk drive group having a plurality of disk drives, the meta-disk drive group configured for being communicatively coupled with the storage controller, each of the plurality of disk drives including a drive interface connector. Additionally, each drive interface connector of the plurality of disk drives of the meta-disk drive group is configured for being communicatively coupled to each of the remaining drive interface connectors of the plurality of disk drives, thereby allowing the plurality of disk drives to communicate as a single device with the storage controller.

Abstract: A design information generating equipment is provided. A control component of the design information generating equipment, when a basic function of the plurality of functions constitutes a requested function, and design information that corresponds to the basic function is stored in a second memory area, uses the stored design information, and, when the design information that corresponds to the basic function of the plurality of functions is not stored in the second memory area, uses a source program corresponding to the basic function of the plurality of functions stored in a first memory area, and performs control so as to generate design information corresponding to the basic function of the plurality of functions and stores the generated design information in the second memory area, and, using the generated design information, reconfigures a design configured to execute the requested function, and executes the requested function with the reconfigurable design information.

Abstract: A dual-mode prefetch mechanism for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags for identifying the data stored in the data array; a set of checkpoint tags for storing data identification; a cache controller including prefetch logic, the prefetch logic including a checkpoint prefetch controller and a checkpoint prefetch operator.

Abstract: The data processing apparatus according to an embodiment of the present invention includes: a first processor; a second processor; and an external RAM to/from which the first processor writes/reads data, the first processor including a cache memory for storing data used in the first processor in association with an address on the external RAM, and the data being written to the cache memory by the second processor not through the external RAM.

Abstract: A redundant array of independent disk (RAID) stack determines a first number of processor cycles to reload first data from a first memory address of a main memory into a processor of a data processing system. The RAID stack loads second data from a second memory address of the main memory into the processor, where the second memory address is configured to be an address offset from the first memory address. The RAID stack reloads the first data from the first memory address of the main memory and determines a second number of processor cycles to reload the first data from the first memory address of the main memory. An alias offset of a cache memory associated with the processor of the data processing system is determined based on the first number of processor cycles and the second number of processor cycle.

Abstract: A method and apparatus for optimizing a target program including a pattern of instructions to be replaced. The method is performed by execution of program code by a processor of an information processing apparatus that includes an output device and a computer readable storage medium storing the program code. At least one transformation is performed on the target program to generate a transformed target subprogram in which dependencies among the instructions included in the target subprogram are matched with dependencies in the pattern to be replaced. The transformed target subprogram is replaced, with a post-replacement instruction stream determined to correspond to the pattern to be replaced, to generate a replaced target subprogram. An optimized target program that includes the replaced target subprogram is outputted to the output device. The at least one transformation includes a first transformation, a loop transformation, or both the first transformation and the loop transformation.

Abstract: A redundant array of independent disk (RAID) stack loads a first parity block of RAID data into a first memory address of a main memory of a data processing system. A first parity calculation is performed on a first plurality of data blocks of the RAID data with the first parity block loaded from the first memory address of the main memory into a register of the processor of the data processing system and a cache memory associated with the processor. The RAID stack loads subsequent parity blocks of RAID data into subsequent memory addresses of the main memory, where a difference between the first memory address and the subsequent memory addresses equals to one or more multiples of an alias offset associated with the cache memory. A second parity calculation is performed on a second plurality of data blocks and the second parity block of the RAID data.

Abstract: In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted.

Abstract: A data processing system includes a data store having storage locations storing entries which can be used for a variety of purposes, such as operand value prediction, branch prediction, etc. An entry profile store stores profile data for more candidate entries than there are storage locations within the data store. The profile data is used to determine replacement policy for entries within the data store. The profile data can include hash values used to determine whether predictions associated with candidate entries were correct without having to store the full predictions within the profile data.

Abstract: A memory system includes a controller that reads out, data written in a nonvolatile second storing area, from which data is read out and in which data is written in a page unit, to a first storing area as a cache memory included in a semiconductor memory and transfers the data to the host apparatus. The controller performs, when a readout request from the host apparatus satisfies a predetermined condition, at least one of first pre-fetch for reading out, to the first storing area data from a terminal end of a logical address range designated by a readout request being currently processed to a boundary of a logical address aligned in the page unit and a second pre-fetch for reading out data from the boundary of the logical address aligned in the page unit to a next boundary of the logical address.

Abstract: Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or processing may be reduced. First, data is received and pre-scanned to generate a sample fingerprint. Fingerprints stored in a faster memory that are similar to the sample fingerprint are identified. Data stored in the slower memory associated with the identified stored fingerprints is copied into the faster memory. The copied data may be compared to the received data. Various embodiments may be included in a network memory architecture to allow for faster data matching and instruction generation in a central appliance.

Abstract: This invention is a system and method for managing provisioning of resources for one or more data storage networks using a new architecture.

Abstract: A data prefetching technique uses predefined prefetching criteria and prefetching models to identify and retrieve prefetched data. A prefetching model that defines data to be prefetched via a network may be stored. It may be determined whether prefetching initiation criteria have been satisfied. Data for prefetching may be identified based on the prefetching model when the prefetching initiation criteria have been satisfied. The identified data may be prefetched, via the network, based on the prefetching model.

Abstract: A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.

Abstract: Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. In the present application, we present a virtualisation layer consisting of an operating system extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system.

Abstract: During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.

Abstract: Provided are a method, computer program product and system for determining an end of valid log in a log of write records. Records are written to a log in a storage device in a sequential order, wherein the records include a next pointer addressing a next record in a write order and a far ahead pointer addressing a far ahead record in the write order following the record. The far ahead pointer and the next pointer in a plurality of records are used to determine an end of valid log from which to start writing further records.

Abstract: Techniques are provided for enabling execution of a process employing a cache Method steps can include obtaining a first probability of accessing a given artifact in a state Si, obtaining a second probability of using a predicate from a current state Sc in the state Si, determining a benefit of prefetching the given artifact using the predicate based on at least the first probability and the second probability, and whether and/or when a cache replacement should be conducted, based at least on the benefit determined.

Abstract: A memory control apparatus, a memory control method and an information processing system are disclosed. Fetch response data retrieved from a main storage unit is received, while bypassing a storage unit, by a first port in which the received fetch response data can be set. The fetch response data retrieved from the main storage unit, if unable to be set in the first port, is set in a second port through the storage unit. A transmission control unit performs priority control operation to send out, in accordance with a predetermined priority, the fetch response data set in the first port or the second port to the processor. As a result, the latency is shortened from the time when the fetch response data arrives to the time when the fetch response data is sent out toward the processor in response to a fetch request from the processor.

Abstract: In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to identify a prefetch stream in cache misses from the data cache, and the prefetch unit is configured to issue prefetches predicted by the prefetch stream to prefetch data into the data cache. More particularly, the prefetch unit implements one or more stream engines that generate prefetches for respective prefetch streams. Each stream engine is configured to maintain limit data that indicates a number of prefetches that are permitted to be outstanding beyond a most recent demand access. The stream engine is configured to increase the limit responsive to the number of demand accesses that consume prefetched data at least equaling the limit.

Abstract: Just-in-time segment cleaning obtains the location of blocks of a storage system predicted to be targeted by a future write operation and cleans the blocks targeted for the future write operation prior to the occurrence of the future write operation. In one aspect, just-in-time segment cleaning is performed in proportion to previous user-initiated write operations. In another aspect, just-in-time segment cleaning applies a cost analysis determination to minimize the work of cleaning.

Abstract: A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock.

Abstract: Dynamically controlling a prefetching range of a software controlled cache is provided. A compiler analyzes source code to identify at least one of a plurality of loops that contain irregular memory references. For each irregular memory reference in the source code, the compiler determines whether the irregular memory reference is a candidate for optimization. Responsive to identifying an irregular memory reference that may be optimized, the complier determines whether the irregular memory reference is valid for prefetching. If the irregular memory reference is valid for prefetching, a store statement for an address of the irregular memory reference is inserted into the at least one loop. A runtime library call is inserted into a prefetch runtime library to dynamically prefetch the irregular memory references. Data associated with the irregular memory references are dynamically prefetched into the software controlled cache when the runtime library call is invoked.

Abstract: In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to detect one or more prefetch streams corresponding to load operations that miss the data cache, and includes a memory configured to store data corresponding to potential prefetch streams. The prefetch unit is configured to confirm a prefetch stream in response to N or more demand accesses to addresses in the prefetch stream, where N is a positive integer greater than one and is dependent on a prefetch pattern being detected. The prefetch unit comprises a plurality of stream engines, each stream engine configured to generate prefetches for a different prefetch stream assigned to that stream engine. The prefetch unit is configured to assign the confirmed prefetch stream to one of the plurality of stream engines.

Abstract: A method for prefetching data in a bus system is provided. First, according to an address signal from a master, a prefetching address generator generates a prefetching address signal and transfers it to a first select circuit. In response to a signal from the master indicates that the address is related to the previous address and the control signal is identical to the previous transfer, or in response to a signal from the master indicates that the address and control signals are unrelated to the previous transfer but is matched to a hit logic, a prefetching controller directs the first select circuit to transfer the prefetching address signal to a slave. And the prefetching controller also directs a second select circuit to transfer the prefetched data which is corresponding to the prefetching address signal from the slave to a master.

Abstract: The data processing apparatus according to an embodiment of the present invention includes: a first processor; a second processor; and an external RAM to/from which the first processor writes/reads data, the first processor including a cache memory for storing data used in the first processor in association with an address on the external RAM, and the data being written to the cache memory by the second processor not through the external RAM.

Abstract: A segment encompasses a number of segment records less than the total number of records of a database. The segment records have values for a field of the database. Lowest and highest values of the segment records for the field, and a bitmap for the segment, can be determined and stored. Selected bits of the bitmap each correspond to a value for the field. Each selected bit is set to one where at least one segment record has the value to which the bit corresponds. An index relating to just the segment records can be determined and stored. The lowest and highest values, and the bitmap, are adapted to permit determination of whether the segment has to be loaded into memory to locate records that satisfy a query. The index is adapted to permit searching of the segment records after the segment has been loaded into the memory.

Abstract: A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs.

Abstract: A data processing apparatus includes a pre-fetch unit configured to divide and store data, a validation setting unit configured to store information regarding whether or not the data stored in the pre-fetch unit are valid, an address generation unit configured to generate an address for reading/storing the data from/in the pre-fetch unit, and a pre-fetch control unit configured to control a storage position of the data in the pre-fetch unit by using the address and information of the address generation unit and the validation setting unit.

Abstract: Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or processing may be reduced. First, data is received and pre-scanned to generate a sample fingerprint. Fingerprints stored in a faster memory that are similar to the sample fingerprint are identified. Data stored in the slower memory associated with the identified stored fingerprints is copied into the faster memory. The copied data may be compared to the received data. Various embodiments may be included in a network memory architecture to allow for faster data matching and instruction generation in a central appliance.

Abstract: A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates load/store requests to transfer data between the system memory and the microprocessor. The microprocessor also includes a stream prefetch unit that generates a plurality of prefetch requests to prefetch the data stream from the system memory into the microprocessor. The prefetch requests specify the stream prefetch priority. The microprocessor also includes a bus interface unit (BIU) that generates transaction requests on the bus to transfer data between the system memory and the microprocessor in response to the load/store requests and the prefetch requests. The BIU prioritizes the bus transaction requests for the prefetch requests relative to the bus transaction requests for the load/store requests based on the stream prefetch priority.

Abstract: A caching filter driver which is adapted for communicating with a universal serial bus (USB) mass storage device, the caching filter driver is adapted to: (a) receive a first reading request for a first size data from a USB mass storage driver; (b) determine if requested data which is requested in the first reading request is included in a prefetched read data cache; (c) issue a second reading request for a second size data to the USB mass storage device; and store the second size data in the prefetched read data cache, if the requested data is not included in the prefetched read data cache; and to (d) provide the requested data from the prefetched read data cache; wherein the second size is larger than the first size and the second size data includes the first size data; wherein the caching filter driver resides below the USB mass storage driver.

Abstract: A method includes detecting a cache miss. The method further includes, in response to detecting the cache miss, traversing a plurality of linked memory nodes in a memory storage structure being used to store data to determine if the memory storage structure is a binary tree. The method further includes, in response to determining that the memory storage structure is a binary tree, prefetching data from the memory storage structure. An associated machine readable medium is also disclosed.

Abstract: According to the present invention, methods and apparatus are provided improving reading of a remote tape device by a host through multiple fibre channel switches. A fibre channel switch preemptively sends read requests to a tape device before read requests are received from a host. Flow control, buffer management, and error handling mechanisms are implemented to allow accelerated tape back up restoration while working to prevent buffer overflow and underflow.

Abstract: Upon receipt of a read command or a write command from an external device, a disk apparatus stores an obtained address as a primary address and a secondary address in an address storing unit, increments a counter value of the secondary address, and selects the secondary address of which the counter value indicates the largest number. Upon receipt of the read command for the primary address, the disk apparatus reads data specified by the primary address from a disk and stores it in a buffer memory in advance. Upon receipt of the read command, the disk apparatus sends the data from the buffer to the external device.

Abstract: The present invention discloses methods for improving data-retrieval times from a non-volatile storage device. A method for preloading data to improve data-retrieval times from a non-volatile storage device, the method including the steps of: providing a cache memory for preloading the data upon a host-system request to read the data; determining that a plurality of data segments that constitute a non-contiguous data object, stored in the storage device such that at least one data segment is non-contiguous to a preceding data segment in the data object, are in a predictable sequence; and preloading a non-contiguous next data segment in the predictable sequence into the cache memory after loading a current data segment into a host system from the cache memory, wherein the next data segment is preloaded prior to the host-system request to read the next data segment.

Abstract: A method and system for creating and injecting code into a running program that identifies a hot data stream, and prefetching data elements in the stream so they are available when needed by the processor. The injected code identifies the first few elements in a hot data stream (i.e. the prefix), and prefetches the balance of the elements in the stream (i.e., the suffix). Since the hot data stream identification code and prefetch code is injected at run time, pointer related time-dependencies inherent in earlier prefetch systems are eliminated. A global deterministic finite state machine (DFSM) is used to help create conceptual logic used to generate the code injected into the program for prefix detection.

Abstract: A cache is used in a network storage system that includes a plurality of data storage nodes in a storage cluster, to automatically spread read and write access load, by a plurality of storage clients, for file system data and metadata, across the plurality of data storage nodes.

Abstract: A system to facilitate virtual page translation. An embodiment of the system includes a processing device, a front end unit, and address translation logic. The processing device is configured to process data of a current block of data. The front end unit is coupled to the processing device. The front end unit is configured to access the current block of data in an electronic memory device and to send the current block of data to the processor for processing. The address translation logic is coupled to the front end unit and the electronic memory device. The address translation logic is configured to pre-fetch a virtual address translation for a predicted virtual address based on a virtual address of the current block of data. Embodiments of the system increase address translation performance of computer systems including graphic rendering operations.

Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.

Abstract: A prefetch processing apparatus includes a central-processing-unit monitor unit that monitors processing states of the central processing unit in association with time elapsed from start time of executing a program. A cache-miss-data address obtaining unit obtains cache-miss-data addresses in association with the time elapsed from the start time of executing the program, and a cycle determining unit determines a cycle of time required for executing the program. An identifying unit identifies a prefetch position in a cycle in which a prefetch-target address is to be prefetched by associating the cycle determined by the cycle determining unit with the cache-miss data addresses obtained by the cache-miss-data address obtaining unit. The prefetch-target address is an address of data on which prefetch processing is to be performed.

Abstract: A computer processor and a method of using the computer processor take advantage of information in the event address register of the computer processor by saving information from the event address register to an event address register history buffer. Thus, the event address register history buffer includes a cluster of events associated with execution of a computer program. The cluster of events is analyzed and the computer program modified, either statically or dynamically, to eliminate or at least ameliorate the effects of such events in further execution of the computer program.

Abstract: A memory protection method includes setting a memory area in at least one address setting register; setting a trap type in a trap type setting register corresponding to the address setting register; generating a trap of the trap type set in the trap type setting register in accordance with an access request to the memory area set at the address setting register; setting a size of an inaccessible area in a memory; allocating, in accordance with a memory allocation request from an application, a memory area to the application as an accessible area and an inaccessible area having the inaccessible area size right after the accessible area; setting the inaccessible area in a first address setting register and a first trap type in a first trap type setting register; and generating a memory image of the application and closing the application when a trap of the first trap type occurred.

Abstract: The invention concerns a method for read-addressing a site among a plurality of storage units using a coded address derived from an instruction. The method comprises the following steps: a) predicting (104) the storage unit corresponding to the site to be addressed; b) decoding (108) the address of the site to be addressed and determining (109) the storage unit to be addressed; c) managing (105) a potential read and rewrite conflict assuming that the predicted storage unit is the storage unit to be addressed; d) controlling (111) the addressing of the predicted storage unit at the end of the managing step (105); e) at the end of step b), determining (110) whether the storage unit to be addressed corresponds to the predicted storage unit; and f) if the storage unit to be addressed does not correspond to the predicted storage unit, managing (115) a possible read and rewrite conflict in the storage unit to be addressed and addressing the site of the storage unit to be addressed.

Abstract: Systems and methods are disclosed for updating owner predictor structures. In one embodiment, a multi-processor system includes an owner predictor control that provides an ownership update message corresponding to a block of data to at least one of a plurality of owner predictors in response to a change in an ownership state of the block of data. The update message comprises an address tag associated with the block of data and an identification associated with an owner node of the block of data.

Abstract: A system and method for handling speculative read requests for a memory controller in a computer system are provided. In one example, a method includes the steps of providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a computer system includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.

Abstract: A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.

Abstract: Described is a technology by which high latency problems with respect to web requests are reduced by having a web proxy server predict and pre-fetch content, in parallel, that is to be requested by a client. The web proxy analyzes a main web page requested by a client to predict subsequent client requests. The web proxy pre-fetches content before the client requests it, by making concurrent requests for the page's embedded objects that exceed the client's limited number of (e.g., two) connections. In one example, the web proxy sends HTTP requests substantially in parallel to a web server, thereby reducing overall latency. In another example, the web proxy server sends parallel requests to a remote web proxy coupled to a web server. The remote web proxy requests only a limited number of objects (e.g., two) at a time, but does so over fast (low latency) connections to the web server.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.

Abstract: A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.