Operand Address Generation Patents (Class 711/214)
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Patent number: 7788471Abstract: A system and method for performing vector arithmetic is disclosed. The method includes loading two operand vectors, each composed of a number of vector elements, into two storage locations. A selected arithmetic operation is performed on the operand vectors to produce a result vector having the number of vector elements. Each vector element of the result vector is associated with an arithmetic logic cell that has a first input that can receive any vector element from the first vector and a second input that can receive any vector element from the second vector. Accordingly each vector element of the result vector is a function of any two individual vector elements of the operand vectors. By applying the operand vector elements to the appropriate arithmetic logic cells, and by selecting the appropriate arithmetic operation, complex vector operations can be performed efficiently.Type: GrantFiled: September 18, 2006Date of Patent: August 31, 2010Assignee: Freescale Semiconductor, Inc.Inventor: Chengke Sheng
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Publication number: 20100217950Abstract: A computer system with a physical computer having a physical processor, physical memory, virtual computer and virtual computer controller is disclosed. The virtual computer has its own processor and memory, which are virtual components that are provided by logically dividing the physical processor and memory, respectively. The virtual computer also has a page table storing a physical/virtual memory address correspondence relationship, and a protection object table for address management of a protected address space in the virtual memory. The controller includes a protection exception processing unit, protection exception save region, virtual/physical memory address converter, and instruction analyzer. Upon execution of protection exception processing, the controller compares an instruction address at which was generated the protection exception processing to an instruction address of protection exception information saved.Type: ApplicationFiled: November 23, 2009Publication date: August 26, 2010Applicant: HITACHI, LTD.Inventors: Youji TANAKA, Eiichiro OIWA, Naoya HATTORI
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Publication number: 20100138630Abstract: A data-processing unit comprises a register unit (10) comprising a register (20, R0-R3). The data-processing unit further comprises an address-generation unit (30) for generating a memory address to a memory unit (60). The address-generation unit (30) is adapted to fetch, from the register (20, R0-R3), a base address stored in a first portion (20a) of the register (20, R0-R3) and a first offset address stored in a second portion (20b) of the register (20, R0-R3). The base address and the first offset address are represented with fewer bits than the memory address. The address generation unit (30) is adapted to receive a first instruction and, in response thereto, generate a second offset address based on the first offset address, and generate the memory address by adding the base address and the second offset address. A method for generating the memory address is also disclosed.Type: ApplicationFiled: December 12, 2007Publication date: June 3, 2010Applicant: Telefonaktiebolaget L M Ericsson (publ)Inventors: Per Persson, Harald Gustafsson
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Patent number: 7720669Abstract: A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.Type: GrantFiled: June 30, 2008Date of Patent: May 18, 2010Assignee: International Business Machines CorporationInventors: William J. Lewis, Wei-Yi Xiao
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Patent number: 7711539Abstract: A system and method for emulating SCSI reservations using network file access protocols is provided. The system and method enable applications or operating systems on a networked computer designed to utilize SCSI reservations on only locally attached storage to also access networked data storage. The emulation occurs transparently to higher levels of operating systems or applications so that the applications or operating systems which are designed to only access locally attached storage may be enabled to access networked storage.Type: GrantFiled: August 12, 2002Date of Patent: May 4, 2010Assignee: NetApp, Inc.Inventors: Jeffrey S. Kimmel, Robert Hawley
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Patent number: 7577818Abstract: An address-generating arrangement for a microprocessor has, in addition to its base address-generating unit, one or more address-generating expansion units, connected to the basic unity by an interface. The interface comprises one or more input data buses supplying data from the base unit to the expansion unit and an output data bus supplying data from the expansion unit to the basic unit under control of the microprocessor.Type: GrantFiled: May 6, 2002Date of Patent: August 18, 2009Assignee: NXP B.V.Inventors: Wolfram Drescher, Uwe Porst
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Patent number: 7571076Abstract: A performance monitor device includes an input unit to input both of address information and event occurrence information, an address mask unit to determine an address area to which each piece of the inputted address information belongs, an execution frequency counter to count a number of times of execution of programs in the address areas, an execution frequency holding unit to hold a counting result of the number of times of execution, an event occurrence information counter to count the event occurrence information corresponding to the address areas having the counting result of the number of times of execution included within a predetermined number of highest ranks, a holding unit to hold a counting results of the event occurrence information, and a storing unit to store the counting result of the event occurrence information corresponding to the address area having the highest number of times of execution in predetermined periods.Type: GrantFiled: April 10, 2007Date of Patent: August 4, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hidenori Matsuzaki, Seiji Maeda
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Patent number: 7549036Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.Type: GrantFiled: August 9, 2007Date of Patent: June 16, 2009Assignee: Intel CorporationInventors: Kalpesh Dhanvantrai Mehta, Wen-Shan Wang
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Patent number: 7533242Abstract: A software agent assembles prefetch hint instructions or prefixes defined in an instruction set architecture, the instructions/prefixes conveying prefetch hint information to a processor enabled to execute instructions according to the instruction set architecture. The prefetch hints are directed to control operation of one or more hardware memory prefetcher units included in the processor, providing for increased efficiency in memory prefetching operations. The hints may optionally provide any combination of parameters describing a memory reference traffic pattern to search for, when to begin searching, when to terminate prefetching, and how aggressively to prefetch. Thus the hardware prefetchers are enabled to make improved traffic prediction, providing more accurate results using reduced hardware resources. The hints may include any combination of specific pattern hints (one/two/N-dimensional strides, indirect, and indirect-stride), modifiers including sparse and region, and a prefetch-stop directive.Type: GrantFiled: April 15, 2006Date of Patent: May 12, 2009Assignee: Sun Microsystems, Inc.Inventors: Laurent R. Moll, Jorel D. Hartman, Peter N. Glaskowsky, Seungyoon Peter Song, John Gregory Favor
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Patent number: 7523261Abstract: A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a succession of instruction words having address information, the succession of instruction words prescribing a sequence of machine words which are intended to be processed by an arithmetic and logic unit which is coupled to a buffer store, altering the association between at least a portion of the set of machine words and at least a portion of the set of addresses, changing the address information in the succession of instruction words based on the alteration of the association, storing the changed succession of instruction words in a memory, and storing the set of machine words in the memory, so that it is possible to access the machine words using the associated addresses.Type: GrantFiled: November 6, 2006Date of Patent: April 21, 2009Assignee: Infineon Technologies AGInventors: Josef Haid, Michael Smola, Dietmar Scheiblhofer
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Patent number: 7502909Abstract: A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register, a STRIDE register, and a plurality skip generators, each having SKIP, SPAN and COUNT registers. An address value is initialized to a first address and each COUNT register is initialized. For each address of the sequence an address value is output and a stride value is added to the address value. For each dimension of the data structure the COUNT register associated with the dimension is updated as each address is generated. For all dimensions, when the COUNT register value becomes zero, the skip value associated with the dimension is added to the address value and its COUNT register is reset to a specified value.Type: GrantFiled: October 11, 2005Date of Patent: March 10, 2009Assignee: Motorola, Inc.Inventors: Kent D. Moat, Raymond B. Essick, Michael A. Schuette
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Patent number: 7502725Abstract: A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.Type: GrantFiled: April 29, 2004Date of Patent: March 10, 2009Assignee: International Business Machines CorporationInventors: William J. Lewis, Wei-Yi Xiao
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Patent number: 7464188Abstract: Since no control of accesses made by a computer as accesses to a storage apparatus is executed, the computer can be used illegally to steal and improperly change data stored in the storage apparatus. Thus, an access-control mechanism external to the computer is constructed to solve this problem. That is to say, the control of accesses is executed in the storage apparatus and a network apparatus for each program executed by the computer. In order to enhance the implementability of such control of accesses, the control is executed without extending a variety of protocols of communications among the computer, the network apparatus and the storage apparatus. By implementing the control of accesses in this way, a program other than programs specified in advance is not capable of making an access to data stored in the storage apparatus. Thus, even if the computer is used illegally, data stored in the storage apparatus can be prevented from being stolen and changed improperly.Type: GrantFiled: January 20, 2004Date of Patent: December 9, 2008Assignee: Hitachi, Ltd.Inventors: Akira Shimizu, Shinji Fujiwara
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Patent number: 7447871Abstract: A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit offset field but with a fixed addressing mode and a second form utilizing a shorter 8-bit offset field but with an addressing mode specified within a manipulation mode control field of the data access instruction.Type: GrantFiled: February 7, 2007Date of Patent: November 4, 2008Assignee: ARM LimitedInventors: David James Seal, Vladimir Vasekin
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Patent number: 7444494Abstract: According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.Type: GrantFiled: May 31, 2005Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: Benjiman L. Goodman, Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams
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Patent number: 7406569Abstract: Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.Type: GrantFiled: August 12, 2002Date of Patent: July 29, 2008Assignee: NXP B.V.Inventor: Jan-Willem van de Waerdt
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Patent number: 7401202Abstract: Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand to provide a shifted, sign-extended operand, and adding the shifted, sign-extended operand to the second operand. The second operand has a different bit length than the first operand.Type: GrantFiled: September 14, 2005Date of Patent: July 15, 2008Assignee: Azul Systems, Inc.Inventor: Cliff N. Click, Jr.
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Patent number: 7398370Abstract: In an information processing apparatus, a program processing unit executes a program described as an object-oriented language executed by a platform-independent machine language. A monitor unit monitors a change of a network address of the information processing apparatus. A reference provision unit provides a new network address of the information processing apparatus for another information processing apparatus when said monitor unit detects the change of the network address of the information processing apparatus.Type: GrantFiled: June 23, 2005Date of Patent: July 8, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Tetsuro Kimura
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Patent number: 7386702Abstract: Systems and methods are provided for accessing thread private data in a computer. In one embodiment, a method is provided for accessing thread private data in a computer for a program executed by using a plurality of threads, wherein each of the plurality of threads may be associated with a different area of its respective stack for storage of thread private data. Further, the stacks of threads may cover a coherent address space in a memory of the computer, starting at a base address. The method may include determining a thread identifier of the one of the plurality of threads based on the base address and a stack pointer of one of the plurality of threads. In addition, the method may include accessing thread private data of one of the stacks based on the determined thread identifier.Type: GrantFiled: August 4, 2004Date of Patent: June 10, 2008Assignee: SAP AGInventor: Ivan Schreter
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Patent number: 7366882Abstract: A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle.Type: GrantFiled: May 10, 2002Date of Patent: April 29, 2008Inventors: Zohair Sahraoui, Gary Ciambella
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Patent number: 7360058Abstract: Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.Type: GrantFiled: February 9, 2005Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: Rachel Marie Flood, Scott Bruce Frommer, David Allen Hrusecky, Sheldon B. Levenstein, Michael Thomas Vaden
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Patent number: 7356811Abstract: A method, apparatus, and computer instructions for referencing a constant pool. A determination is made as to whether a bytecode references the constant pool. A relative offset to the constant pool is identified for the bytecode, in response to the bytecode referencing the constant pool. The bytecode is then replaced with a new bytecode containing the relative offset. The relative offset is used to reference the constant pool.Type: GrantFiled: July 8, 2004Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: Peter Wiebe Burka, Graham Alan Chapman, Trent A. Gray-Donald, Karl Michael Taylor
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Publication number: 20080059754Abstract: A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a succession of instruction words having address information, the succession of instruction words prescribing a sequence of machine words which are intended to be processed by an arithmetic and logic unit which is coupled to a buffer store, altering the association between at least a portion of the set of machine words and at least a portion of the set of addresses, changing the address information in the succession of instruction words based on the alteration of the association, storing the changed succession of instruction words in a memory, and storing the set of machine words in the memory, so that it is possible to access the machine words using the associated addresses.Type: ApplicationFiled: November 6, 2006Publication date: March 6, 2008Applicant: INFINEON TECHNOLOGIES AGInventors: Josef Haid, Michael Smola, Dietmar Scheiblhofer
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Patent number: 7308555Abstract: A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Next, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.Type: GrantFiled: November 17, 2004Date of Patent: December 11, 2007Assignee: Sunplus Technology Co., Ltd.Inventor: Bor-Sung Liang
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Patent number: 7308554Abstract: A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Then, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.Type: GrantFiled: November 15, 2004Date of Patent: December 11, 2007Assignee: Sunplus Technology Co., Ltd.Inventor: Bor-Sung Liang
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Patent number: 7308556Abstract: A device for writing data in a processor to memory at unaligned location. The data is stored in an internal register of the processor for writing to unaligned addresses of a memory partitioned by word boundaries into a plurality of words. A rotator is coupled to the internal register for rotating data of the internal register to a first position in accordance with written unaligned address. A store combine register is coupled to the rotator for temporarily storing data of the rotator. A mask selector is coupled to the rotator and the store combine register for selectively masking their data in accordance with the written unaligned address and storing the data masked to the memory.Type: GrantFiled: November 17, 2004Date of Patent: December 11, 2007Assignee: Sunplus Technology Co., LtdInventor: Bor-Sung Liang
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Patent number: 7308553Abstract: A processor device capable of cross-boundary alignment of plural register data and the method thereof. The processor includes a decoder to decode a multiple shift instruction, a register unit with plural N-bit registers, a shifter to combine a first and a second output contents of the register unit to form a 2N-bit word and shift the word by w bits, thereby outputting first N bits of the word shifted, a controller to set the register unit in accordance with the multiple shift instruction decoded, thereby reading contents of corresponding registers for shifting w bits by the shifter and then writing an output of the shifter to the register unit.Type: GrantFiled: November 15, 2004Date of Patent: December 11, 2007Assignee: Sunplus Technology Co., Ltd.Inventor: Bor-Sung Liang
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Patent number: 7302524Abstract: An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits a data cache into multiple regions and each region is selected according to a thread ID indicator in an instruction register. The data cache is split when the apparatus is in the multi-threading execution mode indicated by an enable cache split bit.Type: GrantFiled: September 25, 2003Date of Patent: November 27, 2007Assignee: International Business Machines CorporationInventor: David A. Luick
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Patent number: 7293155Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.Type: GrantFiled: May 30, 2003Date of Patent: November 6, 2007Assignee: Intel CorporationInventors: Kalpesh Dhanvantrai Mehta, Wen-Shan Wang
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Patent number: 7234025Abstract: A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP string instruction prefix. The programmer specifies the count of cache lines to be prefetched in the ECX register, similarly to the repeat count of a REP string instruction. The effective address of the first cache line is specified similar to the conventional PREFETCH instruction. The REP PREFETCH instruction stops if the address of the current prefetch cache line misses in the TLB, or if the current processor level changes. Additionally, a line is prefetched only if the number of free response buffers is above a programmable threshold. The prefetches are performed at a lower priority than other activities needing access to the cache or TLB.Type: GrantFiled: November 3, 2004Date of Patent: June 19, 2007Assignee: IP-First, LLCInventor: Rodney E. Hooker
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Patent number: 7152147Abstract: A computer system comprises a primary volume 22P having a plurality of storage blocks P, and a differential volume 22D having a plurality of storage blocks D. Differential data corresponding to one among the plurality of storage blocks P is stored in at least one among the plurality of storage blocks D. A control device 210 identifies differential data which is unnecessary for a host device 100, based on a snapshot management table S or C indicating whether data has been read by the host device 100 from any one of storage blocks P, and on a differential management table 400 indicating to which storage block P differential data corresponds and in which storage block D the data is stored, and performs at least one among removal of the identified differential data from the differential volume 22D, and removal of an unnecessary information element from the differential management table 400.Type: GrantFiled: August 13, 2004Date of Patent: December 19, 2006Assignee: Hitachi, Ltd.Inventor: Takashi Suzuki
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Patent number: 7136987Abstract: An apparatus and a system, as well as a method and article, may operate to control a bandwidth of a memory coupled to a plurality of data processing units responsive to protocol indications, such as a number of data processing units in use. In some embodiments, apparatus and systems, as well as methods and articles, may operate to select a memory access group size of about 2N memory banks responsive to receiving an indication of a change in a protocol type, wherein the group is selected from a number B of banks, and N is associated with the protocol type.Type: GrantFiled: March 30, 2004Date of Patent: November 14, 2006Assignee: Intel CorporationInventor: Inching Chen
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Patent number: 7133996Abstract: A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second address which define a logical address map indicating a logical shape of the memory array. An address map changing unit is operatively coupled to the memory array, for receiving a first address signal for generating the first address and a second address signal for generating the second address. The address map changing unit is capable of changing the logical address map by altering a part of one of the first address signal and the second address signal.Type: GrantFiled: October 25, 2002Date of Patent: November 7, 2006Assignee: Fujitsu LimitedInventors: Shinichiro Ikeda, Yoshiharu Kato
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Patent number: 7093085Abstract: Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to a predetermined interleaving rule to randomly output the data from the memory. If a first index I is greater than data size S, a second index is generated and output prior to outputting invalid data stored in the memory at the location of the first index.Type: GrantFiled: September 27, 2004Date of Patent: August 15, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Jae-Hong Lee
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Patent number: 7080056Abstract: A method for generating a simple kind of computer based artificial consciousness, which means to give a in a computer running invention-pursuant program the capability to act and to know the effects of its actions and to plan further actions consciously. This is realized by giving the computer the capability to program its processor by its own and to plan that self-programming targeted. This works, because the computer learns to program in machine-code by its own and it has got a dynamical valuation system to weight if its actions are useful or not. Further basic needs like “no_pain” and “no_hunger” are modelled to make it act to fulfill its basic needs. It has also the capability to solve a pregiven by several formulas determined programming aim, which means to develop logical programs which then can be implemented by users into their projects.Type: GrantFiled: November 2, 2000Date of Patent: July 18, 2006Inventor: Gerd Krämer
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Patent number: 7069393Abstract: A computer system in which a host computer is connected to a storage unit, the storage unit operating in a unit of a file. A file attribute control unit and the storage unit execute the processing being linked together so that, in response to a request from a client computer, the host computer executes a file attribute control program to add a particular attribute to the file, and that the storage unit operates in response to the attribute that is added.Type: GrantFiled: October 16, 2002Date of Patent: June 27, 2006Assignee: Hitachi, Ltd.Inventors: Kenichi Miyata, Naoto Matsunami, Koji Sonoda, Manabu Kitamura
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Patent number: 7032100Abstract: A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the device, thereby reducing the surface area required, and associated costs. A variety of techniques are also employed to ease the task of programming the processor for cryptographic processes, and to optimize the efficiency of instructions that are expected to be commonly used in the programming of such processes. In a preferred low-cost embodiment, a single-port random-access memory (RAM) is used for operand storage, few data busses and registers are used in the data-path, and the instruction set is optimized for parallel operations within instructions.Type: GrantFiled: December 17, 1999Date of Patent: April 18, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: George Samuel Fleming, Farrell L. Ostler, Antoine Farid Dagher
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Patent number: 6978357Abstract: A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.Type: GrantFiled: July 24, 1998Date of Patent: December 20, 2005Assignee: Intel CorporationInventors: Lance Hacking, Shreekant Thakkar, Thomas Huff, Vladimir Pentkovski, Hsien-Cheng E. Hsieh
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Patent number: 6965987Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.Type: GrantFiled: November 17, 2003Date of Patent: November 15, 2005Assignee: Seiko Epson CorporationInventors: Cheryl Senter Brashears, Johannes Wang, Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Patent number: 6950922Abstract: A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a source register and a destination registr. In this digital signal processor, data is extracted from the source register and inserted into the destination register using a position value, which represents the reference position of data extraction, and an offset value, which represents the size of data to be extracted. Accordingly, a sequence of data packets, the size of which are given in neither byte nor word unit, are effectively extracted or inserted, thus saving the space of a memory.Type: GrantFiled: March 13, 2003Date of Patent: September 27, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-jae Chung, Yong-chun Kim
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Patent number: 6941444Abstract: A computer has its programs in instructions and operand descriptors to specify the operands of the instructions. Apparatus for identifying data coherency and encaching requirements and providing access control in a computer system with operands of its instructions specified by operand descriptors is described hereby. In a computer system wherein data items (operands) are represented by operand descriptors that can comprise object numbers, addresses, data types and sizes, vector information and other relevant information concerning the operands, with one bit to identify if the data coherency is to be maintained, another bit to identify if the data is cached, and a field to provide information on the privilege of Read, Write and Execute, and Supervisor or User mode. When an operand is accessed, the respective access control code is checked to validate if any protection is violated, whether caching is activated and whether it is required to maintain data coherency.Type: GrantFiled: September 13, 2001Date of Patent: September 6, 2005Assignee: City U Research LimitedInventor: Anthony S. Fong
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Patent number: 6934828Abstract: A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of when floating point addresses are stored.Type: GrantFiled: September 17, 2002Date of Patent: August 23, 2005Assignee: Intel CorporationInventors: Rajesh S. Parthasarathy, Aravindh Bakthavathsalu
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Patent number: 6931508Abstract: In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to seventh selectors appropriately select either the first address or the second address, and supply the selected address to first to seventh memory areas, respectively. An eighth memory area is supplied with the first address.Type: GrantFiled: December 13, 2002Date of Patent: August 16, 2005Assignee: Fujitsu LimitedInventors: Hiroshi Okano, Fumihiko Hayakawa
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Patent number: 6931517Abstract: A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives a macro instruction that prescribes the pop-compare operation, and generates a pop-compare micro instruction. The pop-compare micro instruction directs pipeline stages in a microprocessor to perform the pop-compare operation. The load logic is coupled to the paired operation translation logic. The load logic receives the pop-compare micro instruction, and retrieves a first operand from an address in memory, where the address is specified by contents of a register. The register is prescribed by the pop-compare micro instruction. The execution logic is coupled to the load logic. The execution logic receives the first operand, and compares the first operand to a second operand.Type: GrantFiled: October 22, 2002Date of Patent: August 16, 2005Assignee: IP-First, LLCInventors: Gerard M. Col, G. Glenn Henry, Terry Parks
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Patent number: 6895429Abstract: A technique enables a server, such as a filer, configured with a plurality of virtual servers, such as virtual filers (vfilers), to participate in a plurality of private network address spaces having potentially overlapping network addresses. The technique also enables selection of an appropriate vfiler to service requests within a private address space in a manner that is secure and distinct from other private address spaces supported by the filer. An IPspace refers to each distinct address space in which the filer and its storage operating system participate. An IPspace identifier is applied to translation procedures that enable the selection of a correct vfiler for processing an incoming request and an appropriate routing table for processing an outgoing request.Type: GrantFiled: December 28, 2001Date of Patent: May 17, 2005Assignee: Network Appliance, Inc.Inventors: Gaurav Banga, Mark Smith, Mark Muhlestein
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Patent number: 6877069Abstract: An address translation logic and method for generating an instruction's operand address. The address generation logic includes an address generation circuit having adders that perform partial sum additions of the instruction operand's base register value with a displacement value in the instruction. The address generation logic also includes a carry prediction history block associated with the instruction that provides predicted carry-in values to the adders during the partial sum addition operation. In a related embodiment, the carry prediction history block that, in an advantageous embodiment, is appended to the instruction includes a predicted row access select (RAS) carry-in value, a predicted column access select (CAS) carry-in value and a confirmation flag that indicates whether the previous carry-in predictions for the previous predicted RAS and CAS carry-in values for the instruction were correct.Type: GrantFiled: March 28, 2002Date of Patent: April 5, 2005Assignee: International Business Machines CorporationInventor: David Arnold Luick
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Patent number: 6871270Abstract: Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to a predetermined interleaving rule to randomly output the data from the memory. If a first index I is greater than data size S, a second index is generated and output prior to outputting invalid data stored in the memory at the location of the first index.Type: GrantFiled: December 3, 2001Date of Patent: March 22, 2005Assignee: Samsung Electronics Co., Ltd.Inventor: Jae-Hong Lee
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Patent number: 6862676Abstract: A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.Type: GrantFiled: January 16, 2001Date of Patent: March 1, 2005Assignee: Sun Microsystems, Inc.Inventors: Micah C. Knapp, Poonacha P. Kongetira, Marc E. Lamere, Julie M. Staraitis
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Patent number: 6851033Abstract: The present invention relates to techniques for predicting memory access in a data processing apparatus and particular to a technique for determining whether a data item to be accessed crosses an address boundary and will hence require multiple memory accesses. An earlier indication can be provided that at least two memory accesses may be required to access a data item by performing a prediction based upon one or more operands generated from a memory instruction instead of waiting for a memory access generation stage to generate the memory access. Prediction logic can generate a prediction signal to prevent the memory access generation stage from receiving signals from a preceding pipeline stage while at least two memory accesses are being generated.Type: GrantFiled: October 1, 2002Date of Patent: February 1, 2005Assignee: Arm LimitedInventor: Richard Roy Grisenthwaite
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Patent number: RE41012Abstract: A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single vector instruction nor to repeat or loop instructions. Rather, the technique, termed register file indexing (RFI) allows full programmer flexibility in control of the block data operational facility and provides the capability to mix non-RFI instructions with RFI instructions. The block-data operation facility is embedded in the iVLIW ManArray architecture allowing its generalized use across the instruction set architecture without specialized vector instructions or being limited in use only with repeat or loop instructions.Type: GrantFiled: June 3, 2004Date of Patent: November 24, 2009Assignee: Altera CorporationInventors: Edwin Franklin Barry, Gerald George Pechanek, Patrick R. Marchand