Abstract: Systems and methods are provided for using an algorithm and data structure for efficient and accurate classification of data items into recovery classes. When a target recovery time (TRT) is specified for a data set, a system may obtain version metadata regarding data items in the data set. The metadata may be obtained in reverse chronological order such that the latest record representing a version or other storage operation is first, followed by the second latest record, and so on. The system may use a bidirectional doubly linked list to efficiently store version data for a particular data item in memory. As version metadata records are read and added to the data structure in reverse chronological order, classification determinations may be triggered when certain conditions are met.

Abstract: A method begins by a processing module concurrently receiving a first data stream and a second data stream for transmission to a receiving entity. The method continues with the processing module dividing each of the first and second data streams to produce a first plurality of data blocks corresponding to the first data stream and a second plurality of data blocks corresponding to the second data stream, where data blocks of the first plurality of data blocks are time aligned with data blocks of the second plurality of data blocks. The method continues with the processing module creating a data matrix from the first and second plurality of data blocks and generating a coded matrix from the data matrix and an encoding matrix. The method continues with the processing module outputting a plurality of pairs of coded values of the coded matrix to the receiving entity.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for calculating tensor data based on a computer, a medium, and a device. The method includes: determining, from a second tensor, a dimension different from a dimension of a first tensor based on dimensions of the first tensor and dimensions of the second tensor; updating stride in the different dimension to a predetermined value; reading a to-be-operated data block of the second tensor from a buffer module based on updated stride with the predetermined value in each dimension of the second tensor, where the to-be-operated data block is a data block for which padding processing is performed; and performing binary operation on the first tensor based on the to-be-operated data block of the second tensor. According to the present disclosure, broadcasting may be conveniently achieved without difficulty of hardware design being increased.

Abstract: A system and method of query processing in a multi-level storage system having a unified table architecture. A query is received by a common query execution engine connected with the unified table architecture, the query specifying a data record. The common query execution engine performs a look-up for the data record based on the query at the first level storage structure. If the data record is not present at the first level storage structure, the common query execution engine performs separate look-ups in each of the second level storage structure and the main store.

Abstract: A signal receiving device includes a sampling device configured to sample an input signal to output a plurality of sampling values, and an output circuit configured to output data based on the sampling values. The output circuit outputs the data by performing majority voting based on first to third sampling values of the sampling values in response to a first control signal, and outputs the data and first and second error count signals based on the first sampling value and fourth and fifth sampling values of the sampling values in response to a second control signal. The first error count signal is generated by comparing the first sampling value sampled under a reference condition with the fourth sampling value sampled under a first offset condition, and the second error count signal is generated by comparing the first sampling value with the fifth sampling value sampled under a second offset condition.

Abstract: Systems, methods, and other embodiments associated with dynamic inclusion of custom columns into a logical model are described. In one embodiment, a method includes: accepting a mapping between a placeholder logical column of a static logical model and a custom physical column; generating an enriched dataset that combines a description of the custom physical column with values of the custom physical column; placing the enriched dataset into the placeholder logical column; and presenting the static logical model with the enriched dataset in the placeholder logical column.

Abstract: A hardware accelerator may be used for assisting a separate processor in performing sparse embedding vector lookup operations, each non-zero index of a sparse embedding vector referencing a respective dense embedding vector. The hardware accelerator comprises: a plurality of Dynamic Random Access Memory (DRAM) modules, each DRAM module comprising a distinct packaged device or chiplet; one or more memory controllers, each memory controller being configured to address a subset of the plurality of DRAM modules, each memory controller and associated subset of the DRAM modules defining a memory channel; and processing logic, arranged to control the one or more memory controllers. More than one dense embedding vector may be read from multiple memory channels in parallel and/or multiple copies of a dense embedding vector are stored in a memory channel.

Abstract: A disclosed system may include a hardware distortion data pipeline that may include (1) a quantization module that generates a quantized data set, (2) an inverse quantization module that generates, from the quantized data set, an inverse quantized data set by executing an inverse quantization of the quantized data set, and (3) an inverse transformation module that generates an inversely transformed data set by executing an inverse transformation of the inverse quantized data set. The system may also include a hardware determination pipeline that determines a distortion metric based on the inversely transformed data set and the residual frame data set, and a hardware token rate pipeline that determines, based on the quantized data set, a token rate for an encoding of the residual frame data set via a video encoding pipeline. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The present disclosure generally relates to a storage snapshot management system. When updated data is written to the memory device, rather than rewriting all of the data, only the updated data is written to a new namespace. A snapshot of the new namespace indicates which LBAs in the new namespace contain data. New namespaces are added each time data is updated. When the updated data is to be read, the data storage device reads the updated LBA from the new namespace, and also gathers the non-updated data from the previous namespace. Eventually, the number of namespaces for the data reaches a threshold, and thus some namespaces need to be evicted. To evict a namespace, the updated data in the namespace is moved to a different namespace, or the non-updated data is moved to a namespace that contains updated data. In either case, the now unused namespaces are evicted.

Abstract: A system and method of query processing in a multi-level storage system having a unified table architecture. A query is received by a common query execution engine connected with the unified table architecture, the query specifying a data record. The common query execution engine performs a look-up for the data record based on the query at the first level storage structure. If the data record is not present at the first level storage structure, the common query execution engine performs separate look-ups in each of the second level storage structure and the main store.

Abstract: A method of video processing includes performing a conversion between a video comprising a picture that includes multiple sub-pictures and a coded representation of the video using a coding mode according to a rule. The rule specifies that certain stored information about a previous sub-picture is reset prior to processing each next sub-picture of the multiple sub-pictures.

Abstract: The present disclosure includes methods and systems for protecting network resources. An exemplary method comprises starting, by a processor, copy-on-write snapshotting for modifications to a plurality of files in storage, the modification initiated by a suspicious application, detecting, by the processor, a modification of a file of the plurality of files, determining, by the processor, whether the file is stored on a shared network resource or a local resource, in response to determining that the file is stored on a shared network resource, determining, by the processor, that a current region being modified is not already saved in a snapshot, and if the current region is not saved, saving the current region to a snapshot, marking, by the processor, the current region as being saved and analyzing all saved regions that were modified for malicious activity to determine that the suspicious application modifying the saved regions is malicious.

Abstract: Described is a computing system for vector prefetching which includes a hierarchical memory including multiple caches, a missing address storage unit (MASU) associated with each cache which stores prefetch requests suffering a cache miss, a prefetcher which sends prefetch requests towards the hierarchical memory, and a vector prefetch unit. The vector prefetch unit determines existence of at least one of a relationship between a cache block associated with the prefetch request and cache blocks associated with one or more entries in a MASU, or a relationship between cache blocks associated with different entries in a MASU, and sends a vector prefetch request based on related prefetch requests including indicators indicating a starting cache block and a number of related cache blocks to a higher memory level to obtain data associated with each cache block. The hierarchical memory stores the data received in at least one response message from the higher memory level if available.

Abstract: Systems, methods, and other embodiments associated with dynamic inclusion of custom columns into a logical model are described. In one embodiment, a method includes mapping a selected custom logical column in the logical model to a custom physical column represented as a row in a physical table in real time by assigning a column sequence identifier uniquely associated with the selected custom logical column to the custom physical column; retrieving a custom column definition for the custom physical column in real time to form an enriched dataset of custom column records; pivoting the enriched dataset into the selected custom logical column in real time to integrate the custom logical column into the logical model; and presenting the logical model including the mapped custom logical columns for access in a business intelligence environment.

Abstract: Technology for determining an amount of time to wait to retry requests to a representational state transfer (REST) server system for a REST resource, where the time to wait is always chosen to be a prime number of time units (for example, slots, milliseconds). While currently conventional systems will sometimes use a prime number of time units to wait for a retry request, various embodiments of the present invention will always, and invariably, use a prime number of time units. The REST resource may be, for example, a REST application programming interface (API) that is requested by and delivered to a client system using hypertext transfer protocol (HTTP).

Abstract: Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is scalable to a plurality of machines and includes a data manager component, an object manager component and a distributed object manager component, which can be implemented in a modular fashion. Moreover, the layering arrangement can provide for an explicit cache tier (e.g., cache-aside architecture) that applications are aware about, wherein decision are made explicitly which objects to put/remove in such applications (as opposed to an implicit cache wherein application do not know the existence of the cache).

Abstract: Providing quality of service levels to a plurality of sources that perform access requests to a disk resource includes providing a disk resource queue containing access requests for the disk resource, providing a source queue for each of the sources containing access requests generated by a corresponding one of the sources, determining if a new access request from a particular source is urgent according to a specified number of I/O operations per second for the particular source and a time since a previous access request from the particular source, adding the new access request to the disk resource queue if the new access request is urgent, and adding the new access request the source queue of the particular source if the new access request is not urgent and the length of the disk resource queue is greater than a predetermined queue depth value.

Abstract: A method begins by a dispersed storage (DS) processing module concurrently receiving a first data stream and a second data stream for transmission to a receiving entity. The method continues with the DS processing module segmenting each of the first and second data streams to produce a first plurality of data segments and a second plurality of data segments, dividing one of the first plurality of data segments into a first plurality of data blocks, and dividing one of the second plurality of data segments into a second plurality of data blocks. The method continues with the DS processing module creating a data matrix from the first and second plurality of data blocks and generating a coded matrix from the data matrix and an encoding matrix. The method continues with the DS processing module outputting one or more pairs of coded values of the coded matrix to the receiving entity.

Abstract: Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

Abstract: Provided is a remote copy system capable of guaranteeing the time ordering of data to be handled by a remote site even when the tasks at the remote site are operated across a plurality of storages or a plurality of volume groups. A consistency group consisting of a secondary journal volume and a replica is associated with a journal group consisting of a primary data volume, a primary journal volume, a secondary journal volume, and a secondary data volume. Upon backing up a secondary data volume and forming a replica, the host system issues a backup time reservation command to a storage apparatus, and the storage apparatus creates a replica by comparing the time stamp added to the journal data and the backup reservation time.

Abstract: Incoming data frames are parsed by a hardware component. Headers are extracted and stored in a first location along with a pointer to the associated payload. Payloads are stored in a single, contiguous memory location.

Abstract: A method is provided for accessing data in an external virtual memory. A host receives from a storage manager a created handle for autonomous access of a volume. The volume forms part of accessible volumes in the virtual memory. The host autonomously provisions the handle to a selected volume from among the accessible volumes, and the host accesses the selected volume through the handle.

Abstract: A method for operating a graphic user interface is provided. The operation method comprises the following steps. An N-dimensional physical machine resource entity is provided. A first OS system graphic object is generated in a specific resource column of each of N?1 resource plane. Resource graphic objects are generated to occupy one of the resource blocks of each of the resource columns besides the specific resource column. The first OS system graphic object is deformed to display a usage of a first resource and a specific resource, and the number of the resource graphic objects is changed to display a remaining amount of the first resource and the specific resource.

Abstract: This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area.

Abstract: A method, system, and apparatus a method for remote data back up with de-duplication and recovery from clustered secondary storage arrays are disclosed. In one embodiment, a method includes writing a set of data of a primary storage module (e.g., may be coupled to the secondary storage cluster with a fiber channel network) to a secondary storage module of a secondary storage cluster, writing an other set of data of the primary storage module to an other secondary storage module coupled to the secondary storage module, writing the set of data from the secondary storage module to the other secondary storage module of the secondary storage cluster (e.g., the other secondary storage module may contain both the set of data and the other set of data), and writing the other set of data from the other secondary storage module to the secondary storage module.

Abstract: A method and corresponding apparatus for enhancing the capacity of communication and memory devices, said method comprising the representation of information by lattice points confined to a cubic region of an n-dimensional space, by means of which for example capacity gains of 50% or 100% and more may be achieved, relative to ‘conventional’ communication and storage methods.

Abstract: A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.

Abstract: A data processing system is provided with a memory controller (130) converting memory addresses (170) into selecting signals (120) for a memory device (100). The mapping between memory addresses and selecting signals is provided by mapping logic (140) within the memory device. The configuration of the mapping logic, also known as a mapping scheme, is defined by data stored in mapping specifying data storage (150), which may be altered by operating system software or application software (160) running on the system. Altering this configuration may be as a result of signals received from a monitoring unit (135) which monitors the efficiency with which the current mapping scheme is accessing data stored in the memory device. More than one mapping scheme may be used within a single memory device.

Abstract: In one aspect, a method of consolidating snapshots includes storing snapshots using a journal in a continuous data protection environment. Each entry of the journal corresponds to one of a unique group of DO METADATA stream data blocks and a unique group of UNDO METADATA stream data blocks. The method also includes receiving a user input designating at least two snapshots to consolidate, storing changes to the data blocks from the at least two snapshots in a temporary stream on the journal and consolidating the at least two snapshots by replacing the at least two snapshots in the journal with a single consolidated snapshot comprising the changes for each data block from the temporary stream. Storing changes includes storing one of the oldest changes of the UNDO METADATA stream data blocks and the latest changes of the DO METADATA stream data blocks.

Abstract: A controller, a memory device including a memory array, and a method for accessing the memory device. The method includes, during a first access, activating a first page of the memory array corresponding to a first row address and accessing data from the first page with a first column address. The method further includes, during a second access, activating a first sub-page of the memory array corresponding to a second row address and accessing data from the first sub-page with a second column address. The activated first sub-page of the memory array is smaller than the first page of the memory array. The method further includes activating a second sub-page without receiving a separate activate command.

Abstract: Illustrative embodiments provide a computer implemented method for incremental storage de-allocation during a clean process within a point-in-time copy storage management system. The computer implemented method determines whether to perform the clean process and responsive to a determination to perform the clean process, determines whether a set of discrepant bits is present. Responsive to the determination that the set of discrepant bits is present, the computer implemented method copies each dirty grain for each discrepant bit in the set of discrepant bits to a downstream target to form a set of copied dirty grains and determines whether a particular dirty grain in the set of copied dirty grains has been allocated to a space efficient storage unit. Responsive to a determination that the particular dirty grain was allocated to a space efficient storage unit, the computer implemented method de-allocates the particular grain from an upstream source.

Abstract: Techniques for continuous data protection can include creating snapshots of one or more underlying storage volumes upon specific file system events. Generating snapshots upon every file close event can protect the files in a storage system by keeping a snapshot of every version or modification of each file. Removal of redundant snapshots can mitigate the impact on storage capacity associated with creating these large numbers of volume snapshots upon each file close event. Additionally, file closure lists can be employed to allow generating snapshots only when a previously closed file is reopened. Such an approach can protect the previous version of a file prior to the opening of a new version of the file. Such an approach can also mitigate storage capacity impact without the creation of redundant snapshots.

Abstract: The present invention relates to mechanisms for handling and detecting collisions between threads (5, 6, 7) that execute computer program instructions out of program order. According to an embodiment of the present invention each of a plurality of threads (5, 6, 7) are associated with a respective data structure (9, 10, 11) comprising a number of bits (12) that correspond to memory elements (m0, m1, m2, mn) of a shared memory (4). When a thread accesses a memory element in the shared memory, it sets a bit in its associated data structure, which bit corresponds to the accessed memory element. This indicates that the memory element has been accessed by the thread. Collision detection may be carried out after the thread has finished executing by means of comparing the data structure of the thread with the data structures of other threads on which the thread may depend.

Abstract: A refresh controller transmits two refresh request signals of a first request signal which indicates a time at which a refresh operation of a DRAM may be performed and a second request signal which indicates a time at which a refresh operation of the DRAM must be performed, to an arbitrator. On the other hand, also transfer request signals each of which requests a data transfer are transmitted from plural data transfer parts, respectively, to the arbitrator. If no transfer request signal is input when a first request signal is input to the arbitrator, a refresh operation of the DRAM is performed. As a result, a refresh operation is performed when the crowding level of a bus is relatively low. This improves an efficiency in a data transfer.

Abstract: A nonvolatile semiconductor device includes a first flash memory device; a second flash memory device in which data programming and/or reading is faster than in said first flash memory device; an address conversion table which correlates a logical address of a memory cell to a physical address designating said memory cell of said first and/or said second flash memory; an interface part which accepts an access request to a memory cell, an address conversion table search part which searches a physical address an access part which accesses a memory cell a counting part which counts the number of times a physical address has been accessed and generates an access count value of said physical address; a comparison part which compares whether said access count value of said physical address is more than a threshold or not; and a transmitting part which transmits data to said second flash memory device.

Abstract: A memory system includes a nonvolatile semiconductor memory and a controller. The memory has a plurality memory blocks each including memory cells capable of holding data. The data in each of the memory blocks is erased simultaneously. The data is written simultaneously in pages in each of the memory blocks. Each of the pages is a set of a plurality of memory cells. The controller transfers write data and a first row address to the memory and issues a change instruction for the transferred first row address and a second row address differing from the first row address. The memory writes the write data into the memory cells corresponding to the first row address when the change instruction has not been issued, and writes the write data into the memory cells corresponding to the second row address when the change instruction has been issued.

Abstract: A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

Abstract: Subject matter disclosed herein relates to management of a memory device.

Abstract: A method for re-allocating memory partition space is provided. The method comprises determining when a first memory partition is full or has reached a threshold value, determining that a second memory partition has unused storage space that can be allocated to the first memory partition, and assigning the unused storage space from the second memory partition to the first memory partition. A memory controller embedded within the mass storage device and having an interface to an external host assigns the unused storage space from the second memory partition to the first memory partition.

Abstract: Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive.

Abstract: An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

Abstract: An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

Abstract: A system and method for storing and retrieving a sparse matrix from memory of a computing device while minimizing the amount of data stored and costly jumps in memory. The computing device may be an FPGA having memory and processing elements. The method comprises storing non-zero data elements of the matrix in a data array and storing their corresponding column address values in a column index array. To read this stored data from memory, each preceding value of the column index array may be compared with each current value of the column index array to determine if the data array value corresponding with the current column index array value belongs on the next row of the matrix. The method may include pre-ordering the matrix with zero-pad placeholders or creating a row increment pointer array which typically stores fewer values than the number of rows in the matrix.

Abstract: One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and costs associated with testing. A background data loading circuit according to one embodiment of the invention includes a buffer, a data loading circuit, and a pattern generating logic. The buffer is coupled to the array of memory cells. The data loading circuit is coupled to load data into the buffer to be transferred to a respective row of the memory cells. The pattern generating logic is coupled to the data loading circuit. The pattern generating logic applies a pattern generating algorithm corresponding to a test mode when the memory devices is in the test mode and generates patterns of data each for a respective row of the memory cells according to the pattern generating algorithm.

Abstract: A flash memory device includes a memory cell array, a peri circuit unit, an I/O controller, and a controller. The memory cell array includes a plurality of memory cells respectively connected to a plurality of bit line pairs and a plurality word lines. The peri circuit unit is configured to program data into the memory cell array or read data stored in the memory cell array in response to a command input through a control bus. The I/O controller is configured to receive data for programming and supply the data to the peri circuit unit in response to a command provided through a data input/output (I/O) bus. The controller is configured to control the I/O controller to perform a voltage setup operation for a program while the data for program is received.

Abstract: A memory system for providing a slow command decode over an untrained high-speed interface. The memory system includes a memory system having a memory interface device, an untrained high-speed interface, and a memory controller. The untrained high-speed interface is in communication with the memory interface device. The memory controller generates slow commands and transmits the slow commands to the memory interface device via the untrained high-speed interface. The slow commands operate at a first data rate that is slower than a second data rate utilized by the high-speed interface after it has been trained. The memory interface device receives the slow commands via the untrained high-speed interface, decodes the slow commands, and executes the slow commands.

Abstract: A memory device comprises a nonvolatile memory including memory areas that are defined in accordance with a security levels, and a controller configured to write to a first area that is part of the memory areas in an M-value mode and to a second area that is part of the memory areas and provides lower security level than the first area in an N-value mode (N>M).

Abstract: Embodiments of the present invention provide functionality, within a storage-shelf-router integrated circuit, an I/O-controller integrated circuit, or other integrated-circuit implementations of complex electronic devices, for interconnecting all possible pairs of communications ports, a first member of each pair selected from a first set of communications ports and a second member of each pair selected from a second set of communications ports. Embodiments of the present invention employ a time-division-multiplexed global shared memory in order to provide full cross-communications between two or more sets of serial-communications ports, using modest controlling clock rates and wide data-transfer channels.