Accessing, Addressing Or Allocating Within Memory Systems Or Architectures (epo) Patents (Class 711/E12.001)
  • Patent number: 10296242
    Abstract: Techniques for supporting replication and recovery of virtual volumes are provided. In various embodiments, these techniques can include workflows and application programming interfaces (APIs) that facilitate: (1) the provisioning of virtual volumes with metadata indicating that the virtual volumes should be replicated from one virtual volume-enabled storage array/site to another; (2) the discovery of a replication topology across virtual volume-enabled storage arrays/sites; (3) the orchestration of a test failover of a set of virtual volumes; and (4) the orchestration of an actual failover of a set of virtual volumes.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: May 21, 2019
    Assignee: VMWARE, INC.
    Inventor: Sudarsana R Piduri
  • Patent number: 10042726
    Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyu-Hyoun Kim, Warren E. Maule, Kevin M. Mcilvain, Saravanan Sethuraman
  • Patent number: 9043586
    Abstract: Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: May 26, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: William H. Cox, Jr., Jimmy G. Foster, Sr., Sumeet Kochar, Ivan R. Zapata
  • Patent number: 9043562
    Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: May 26, 2015
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Thomas Fahrig
  • Patent number: 9037789
    Abstract: A sensing device and an electronic apparatus in which impairment of performance due to destruction of parameters can be reduced are to be provided. Parameters (sensor parameters 1 to n (n?1)) associated with sensors 1 to N (N?1) are stored in a ROM. A memory control unit reads out the sensor parameters 1 to n from the ROM and writes the sensor parameters into the RAM, and after that, carries out refresh processing to read out the sensor parameters from the ROM and overwrite the RAM with the sensor parameters in predetermined timing. A processing unit carries out signal processing of the sensors 1 to N based on the sensor parameters 1 to n written in the RAM.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: May 19, 2015
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Taketo Chino
  • Patent number: 9032166
    Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. Jeddeloh, Ralph James
  • Patent number: 9026724
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Patent number: 9026714
    Abstract: In one embodiment, a method includes receiving from a memory controller, a request to access memory stored at memory modules, the request directed to one of a plurality of logical ranks, mapping at a rank aggregator, the logical rank to one of a plurality of physical ranks at the memory modules, and forwarding the request to one of the memory modules according to the mapping. Two or more of the memory modules are combined to represent the number of logical ranks at the memory controller such that there is a one-to-one mapping between the logical ranks and the physical ranks. An apparatus for rank aggregation is also disclosed.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: May 5, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Jay Evan Scott Peterson, Philip Manela
  • Patent number: 9015408
    Abstract: A method is disclosed for providing memory bus timing of a load reduction dual inline memory module (LRDIMM). The method includes: determining a latency value of a dynamic random access memory (DRAM) of the LRDIMM; determining a modified latency value of the DRAM that accounts for a delay caused by a load reduction buffer (LRB) that is deployed between the DRAM and a memory bus; storing the modified latency value in a serial presence detector (SPD) of the LRDIMM; and providing memory bus timing for the LRDIMM based on the modified latency value, wherein the memory bus timing is compatible with a registered dual inline memory module (RDIMM).
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: April 21, 2015
    Assignee: Diablo Technologies, Inc.
    Inventors: Maher Amer, Michael Lewis Takefman
  • Patent number: 9015430
    Abstract: Systems and methods for copy on write storage conservation are presented. In one embodiment a copy on write storage conservation method includes creating and mounting a snapshot; mounting a snapshot; monitoring interest in the snapshot; initiating a copy on write discard process before a backup or replication is complete; and deleting the snapshot when the backup or replication is complete. In one embodiment the method also includes marking a file as do not copy on write. In one embodiment, the copy on write discard process includes discarding copy on write data when a corresponding read on the file in the snapshot is successful. Initiating a copy on write discard process can be done at a variety of levels (e.g., a file level, an extent level, a block-level, etc.).
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 21, 2015
    Assignee: Symantec Corporation
    Inventor: Dilip Madhusudan Ranade
  • Patent number: 9015418
    Abstract: A method and system for self-sizing dynamic cache for virtualized environments is disclosed. The preferred embodiment self sizes unequal portions of the total amount of cache and allocates to a plurality of active virtualized machines (VM) according to VM requirements and administrative standards. As a new VM may emerge and request an amount of cache, the cache controller reclaims currently used cache from the active VM and reallocates the unequal portions of cache required by each VM. To ensure cache availability, a quick reclamation amount of cache is immediately available to each new VM as it makes the request begins operation. After reallocation, the newly created VM may rely on a guaranteed minimum quota of cache to ensure performance.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: April 21, 2015
    Assignee: LSI Corporation
    Inventor: Luca Bert
  • Patent number: 9009420
    Abstract: A design structure for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance with one embodiment of the present invention, a first process initially requests an action to be performed by a second process. A reservation is set at a cacheable memory location via a store operation. The first process reads the cacheable memory location via a load operation to determine whether or not the requested action has been completed by the second process. The load operation of the first process is stalled until the reservation on the cacheable memory location is lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventor: Charles R. Johns
  • Patent number: 9009438
    Abstract: An approach to efficient space reclamation in multi-layered thinly provisioned systems. A parent storage volume is thinly provisioned, and uses one or more child storage volumes that are also thinly provisioned for storage. A reclamation command sent to the device providing the parent thinly provisioned storage volume identifies that data has been released, and that the physical storage storing that data can be placed in a free pool and used to satisfy future write requests in the parent storage volume. An identify module identifies which child storage volumes supporting the parent storage volume are thinly provisioned. The data is released at the level of the parent storage volume, and the reclamation command is sent to the child storage volumes supporting the parent storage volume and that are themselves thinly provisioned. The storage is thus released by all affected thinly provisioned storage volumes, and not just the parent storage volume that received the reclamation command.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rahul M. Fiske, Carl E. Jones, Subhojit Roy
  • Patent number: 9009426
    Abstract: A method of storing data on a data storage device having a cache, includes receiving, by the data storage device, a write command indicating a data portion and a range of addresses on the data storage device, the write command instructing the data storage device to write the data portion to each address in the range of addresses; and storing, in the cache, indicia that each address in the range of addresses comprises the data portion.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 14, 2015
    Assignee: EMC Corporation
    Inventors: Walter A. O'Brien III, David W. Harvey
  • Patent number: 9003164
    Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley
  • Patent number: 9003133
    Abstract: An apparatus for storing or reading data in a memory array of a transponder and a corresponding transponder, read/write device and program element is described. Therein, a data file system for storing data within the memory array is defined by a predetermined protocol. The storing additional data includes checking whether a memory size of the application data file is larger than the memory size indicated by the application data length indicator; and storing second application data in a partial memory area of the application data file not occupied by the first application data. Thereby, memory areas which, according to the predetermined protocol, are not used can be used for new applications, data can be hidden in these areas such that they can not be read by protocol compliant reader devices and the data structure read or written is compatible with the former predetermined protocol.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: April 7, 2015
    Assignee: NXP, B.V.
    Inventors: Francesco Gallo, Hauke Meyn
  • Patent number: 9003132
    Abstract: A data processing apparatus may include a plurality of buffer units that stores data, a data write control unit that writes input data to any one of the plurality of buffer units by exclusively controlling the plurality of buffer units, and a data read control unit that reads data to be output from any one of the plurality of buffer units by exclusively controlling the plurality of buffer units. The data write control unit may output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may output a data read completion signal indicating that the reading of the data is completed when the reading of the data to be output is completed.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: April 7, 2015
    Assignee: Olympus Corporation
    Inventors: Keisuke Nakazono, Yoshinobu Tanaka, Akira Ueno
  • Patent number: 8996785
    Abstract: A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: March 31, 2015
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Kesheng Wang
  • Patent number: 8996784
    Abstract: The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: March 31, 2015
    Assignee: Mediatek Inc.
    Inventors: Chung-Hung Tsai, Ming-Shiang Lai
  • Patent number: 8996566
    Abstract: For data backup and recovery based on linked file repositories with each of the linked file repositories representing an individual file system capable of storing at least one version of a file and being connected to at least one server system, each of the linked file repositories are placed in a certain position for storing a certain version of the file. Each position of each of the linked file repositories is continuously numbered. A number of the versions of the file are determined by the position of the one of the linked file repositories. A version-movement process over each of the linked file repositories is implemented to perform a read operation of the at least one version of the file.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nils Haustein, Thorsten Krause, Harald Seipp, Daniel J. Winarski
  • Patent number: 8990519
    Abstract: An electronic component is provided having a plurality of functionalities. The electronic component comprises a control logic, and a non-volatile storage element. The control logic is coupled to the non-volatile storage element and is adapted for storing values in the non-volatile storage element based on an external input signal to the electronic component, each value being indicative for one or more functionalities of the plurality of functionalities. The control logic is adapted for controlling the availability of the plurality of functionalities based on one or more values stored in the non-volatile storage element and for outputting a confirmation signal being indicative for the availability of the plurality of functionalities.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: March 24, 2015
    Assignee: Quotainne Enterprises LLC
    Inventor: Philippe Teuwen
  • Patent number: 8990536
    Abstract: A constrained computing device is provided. The constrained computing device includes a memory, a processor coupled to the memory, and a journaling component executed by the processor in kernel mode. The journaling component is configured to receive information descriptive of a device control, allocate, in the memory, a variable record structured according to a variable definition associated with the device control, store the information within the variable record, receive updated information descriptive of the device control, allocate, in the memory, an update record structured according to an update variable definition, store the updated information within the update record, and link the variable record to the update record.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: March 24, 2015
    Assignee: Schneider Electric IT Corporation
    Inventor: Sean White
  • Patent number: 8990486
    Abstract: Methods and apparatus relating to a hardware and file system agnostic mechanism for achieving capsule support are described. In one embodiment, content associate with a capsule are stored in a non-volatile memory prior to a cold reset. A capsule descriptor may also be constructed, prior to the reset, which includes information about the physical location of the capsule content on the non-volatile memory. Other embodiments are also described and claimed.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: March 24, 2015
    Assignee: Intel Corporation
    Inventors: Michael A. Rothman, Vincent J. Zimmer
  • Patent number: 8990521
    Abstract: According to an embodiment, an information processing device that includes a first storage unit and a second storage unit having power consumption different from that of the first storage unit. The information processing device also includes a control unit configured to make a control to determine a priority of information that is to be stored in the first storage unit or the second storage unit. The control unit is configured to store the information into the first storage unit or into the second storage unit based on the determined priority.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Ishihara, Yoshimichi Tanizawa, Kotaro Ise
  • Patent number: 8990492
    Abstract: Aspects of the disclosure provide for increasing the capacity of ternary content addressable memories (TCAMs). For example, one aspect provides a method for adding rules to a TCAM, wherein the TCAM comprises multiple configurable banks. According to this method, a range of candidate banks in which the proposed rule may be stored is identified based on a priority of the proposed rule, and one of the candidate banks is selected for storing the proposed rule based on a width of the proposed rule and widths of the candidate banks. Another aspect provides a method for deleting one or more rules from a TCAM comprising multiple configurable banks. According to this method, once the rule is deleted, the bank from which it was deleted may be reduced in width, and therefore increased in capacity. For example, wider rules stored in this bank may be relocated to other banks using the method for adding rules to a TCAM.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: March 24, 2015
    Assignee: Google Inc.
    Inventors: Junlan Zhou, Zhengrong Ji
  • Patent number: 8984223
    Abstract: Multiple applications request data from multiple storage units over a computer network. The data is divided into segments and each segment is distributed randomly on one of several storage units, independent of the storage units on which other segments of the media data are stored. At least one additional copy of each segment also is distributed randomly over the storage units, such that each segment is stored on at least two storage units. This random distribution of multiple copies of segments of data improves both scalability and reliability. When an application requests a selected segment of data, the request is processed by the storage unit with the shortest queue of requests. Random fluctuations in the load applied by multiple applications on multiple storage units are balanced nearly equally over all of the storage units.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 17, 2015
    Assignee: Avid Technology, Inc.
    Inventors: Eric C. Peters, Stanley Rabinowitz, Herbert R. Jacobs, Peter J. Fasciano
  • Patent number: 8984254
    Abstract: A technique for operating a processor includes translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number in the translation lookaside buffer. The technique also includes translating, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: March 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thang M. Tran, Edmund J. Gieske
  • Patent number: 8972358
    Abstract: A file storage apparatus comprises: duplication determination unit that determines whether file supplied from client apparatus and file stored in storage unit coincide with each other in same format, and stores the file supplied from client apparatus in the storage unit if the files do not coincide in the same format; and storage management unit that associates, if duplication determination unit determines that the files coincide in the same format, format of the file supplied from the client apparatus with the file stored in the storage unit, reads file stored in the storage unit in response to file read request from client apparatus, converts, if format associated with the read file exists, the read file into the format, and provides the converted file.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: March 3, 2015
    Assignee: NEC Corporation
    Inventor: Satoshi Yamakawa
  • Patent number: 8972695
    Abstract: Embodiments described herein are directed to providing scalability to software applications. A computer system partitions a portion of data stored in a directory services system into multiple different data partitions. Each data partition includes a primary writable copy and at least one secondary read-only copy of the data. The computer system receives a client request for a portion of the data that is stored in the directory services system and accesses various stored partition mappings to determine which of the different data partitions includes the requested data. The computer system also accesses a dynamic copy locator to determine which of the read-only copies of the indicated partition to access and provide the accessed primary writeable copy of the indicated partition and the determined read-only copy to the client in a virtualized manner so that the client is not aware of the data partitions.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: March 3, 2015
    Assignee: Microsoft Corporation
    Inventors: Jeffrey Bruce Parham, Bhalchandra Pandit, Mark Robbin Brown, Murli Satagopan
  • Patent number: 8966189
    Abstract: To provide delayed updating of shared data, a concept of dualistic sequence information is introduced. In the concept, if during local modification of data, a modification to the data is published by another user, a local deviation is created, and when the modification is published, it is associated with an unambiguous sequence reference and the local deviation.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: February 24, 2015
    Assignee: Tekla Corporation
    Inventor: Teemu Rantanen
  • Patent number: 8954670
    Abstract: A RAID bad block module is added to a RAID controller. The bad block module intercepts bad block errors and marks them in a bad block table. When a bad block error is intercepted the bad block module logs the error and determines, based on the error and previously received errors logged in the table, whether the RAID controller can handle the error without failing the entire array. If so, the bad block module passes the error to the RAID controller. Else, the bad block module passes the error to an application or operating system where it is handled like any other disk error. Thus, instead of failing the entire array, the bad block errors are dealt with by the operating system.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: February 10, 2015
    Assignee: American Megatrends, Inc.
    Inventors: Srikumar Subramanian, Raghavan Sowrirajan, Udita Chatterjee
  • Patent number: 8954653
    Abstract: A data storage system configured to efficiently manage system data, efficiently organize system data, and reduce system data redundancy is disclosed. In one embodiment, the data storage system can maintain memory allocation information configured to track defective allocation units. Memory allocation information can be further configured to provide information for locating the memory allocation units or memory locations in physical memory. Separate information that indicates locations of the data allocation units or memory locations and/or records defective memory locations may not be needed. Hence, redundancy can be reduced, efficiency can be increased, and improved performance can be attained.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: February 10, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jerry Lo, Johnny A. Lam
  • Patent number: 8949526
    Abstract: A method is used in reserving storage space in data storage systems. A set of logical units (LUs) predefined as file based storage hardware specific LUs are reserved in a restricted access storage space of a block based storage system. The restricted access storage space is accessed by a file based storage system for storing information required for initializing the file based storage system. The file based storage system is initialized using the information stored in the file based storage hardware specific LUs.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: February 3, 2015
    Assignee: EMC Corporation
    Inventors: Mohamed Elayouty, Russell Laporte, Phillip H. Leef, Michael P. Gordon, Ashok Ramakrishnan
  • Patent number: 8938590
    Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.
    Type: Grant
    Filed: October 18, 2008
    Date of Patent: January 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, Mark Jurenka, Gavin Huggins
  • Patent number: 8938579
    Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: determining that a first search value is associated with a first range field; determining a first bitmap associated with the first search value, wherein the first bitmap indicates at least one range encompassing the first search value; generating a search key based on the first bitmap; and accessing the ternary content addressable memory based on the search key.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: January 20, 2015
    Assignee: Alcatel Lucent
    Inventors: Toby J. Koktan, Andre Poulin, Michel Rochon
  • Patent number: 8938581
    Abstract: A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: January 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hyun Cho, Dongin Kim, Junseok Park, Taemin Lee, Chaesuk Lim
  • Patent number: 8935458
    Abstract: Systems and methods of managing computing system restore points may include an apparatus having logic to receive a command to start a restore point for a solid state drive (SSD). The logic may also conduct a context drop of an indirection table from a volatile memory of the SSD to a non-volatile memory of the SSD in response to the command to start the restore point.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Robert J. Royer, Jr., Amber D. Huffman
  • Patent number: 8935462
    Abstract: For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Stephen L. Blinick, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao-Yu Hu, Matthew J. Kalos, Ioannis Koltsidas, Karl A. Nielsen, Roman A. Pletka
  • Patent number: 8930649
    Abstract: A method begins by a dispersed storage (DS) processing module concurrently receiving a first data stream and a second data stream for transmission to a receiving entity. The method continues with the DS processing module segmenting each of the first and second data streams to produce a first plurality of data segments and a second plurality of data segments, dividing one of the first plurality of data segments into a first plurality of data blocks, and dividing one of the second plurality of data segments into a second plurality of data blocks. The method continues with the DS processing module creating a data matrix from the first and second plurality of data blocks and generating a coded matrix from the data matrix and an encoding matrix. The method continues with the DS processing module outputting one or more pairs of coded values of the coded matrix to the receiving entity.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: January 6, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8930658
    Abstract: In electronic equipment 1, a limitation level on reading data from a USB flash drive (storage device) 2 is set to a setting section 3 in advance. The USB flash drive 2 ascertains the setting at the setting section 3 when connected to the electronic equipment 1 and limits reading data based on the determined setting. If the limitation level does not match with the condition for permitting data read-out as determined in USB flash drive 2, the USB flash drive 2 prohibits the electronic equipment 1 from reading out data. By executing the processing for limiting data read-out at the side of the USB flash drive 2, unauthorized leakage of data can easily be prevented.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: January 6, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tatsuaki Amemura
  • Patent number: 8930623
    Abstract: After a file is stored in a storage device, the file is segmented into a first segment and a second segment, the latter of which is relocated to a removable security device only when the removable security device is connected to the storage device. After the removable security device is removed from the storage device, as long as the removable security device is kept by the owner of the file, the file cannot be accessible for someone other than the owner even if said someone takes the storage device. Security of the file is thus assured.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: January 6, 2015
    Assignee: Transcend Information, Inc.
    Inventors: Chien-Liang Wu, Kuan-Jen Chen
  • Patent number: 8924651
    Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Perry P. Tang, Hemant G. Rotithor, Ryan L. Carlson, Nagi Aboulenein
  • Patent number: 8924658
    Abstract: The techniques introduced here provide for efficient management of storage resources in a modern, dynamic data center through the use of virtual storage appliances. Virtual storage appliances perform storage operations and execute in or as a virtual machine on a hypervisor. A storage management system monitors a storage system to determine whether the storage system is satisfying a service level objective for an application. The storage management system then manages (e.g., instantiates, shuts down, or reconfigures) a virtual storage appliance on a physical server. The virtual storage appliance uses resources of the physical server to meet the storage related needs of the application that the storage system cannot provide. This automatic and dynamic management of virtual storage appliances by the storage management system allows storage systems to quickly react to changing storage needs of applications without requiring expensive excess storage capacity.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: December 30, 2014
    Assignee: Netapp, Inc.
    Inventors: Lakshmi Narayanan Bairavasundaram, Garth Goodson, Vipul Mathur, Shankar Pasupathy, Gokul Soundararajan, Kiran Srinivasan, Kaladhar Voruganti
  • Patent number: 8924657
    Abstract: A data storage apparatus acquires rule information that is used by the external device when performing data access and that defines a relation between the type of access operation and a data read condition, and status information including information for specifying data currently displayed on the external device, and indicates a current display status of the external device. Then, the data storage apparatus determines data to be pre-read from a storage medium and stored in a temporary data storage unit based on the rule information and the status information, and reads the determined data from the storage medium, and stores the read data in a temporary data storage unit. In the case where a data access request is received from the external device, if the requested data is stored in the temporary data storage unit, the requested data is read from the temporary data storage unit, and is output.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: December 30, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toru Kikuchi
  • Patent number: 8918575
    Abstract: A semiconductor chip may be operable to receive and copy an OTP programming vector presented by the semiconductor chip programming device into its memory after it boots up from the boot read-only memory (ROM). The OTP programming vector which is a computer program may comprise an encrypted data to be programmed into the one-time programmable (OTP) memory in the semiconductor chip and may be signed with an electronic signature. The semiconductor chip may be operable to authenticate the OTP programming vector in the memory. The authenticated OTP programming vector in the memory may be executed to decrypt the data and program the data in a random data format into the OTP memory and then report the status via one or more general purpose input/output (GPIO) pins on the semiconductor chip.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: December 23, 2014
    Assignee: Broadcom Corporation
    Inventors: John Markey, Love Kothari, Paul Chou
  • Patent number: 8918598
    Abstract: A newer generation game terminal according to one embodiment of the present invention is provided with a storage access control unit. The storage access control unit accesses a newer generation storage according to a request for access from an application designed to execute a synchronization process based on the assumption of a speed of access to an older generation storage. The storage access control unit estimates time required to access the older generation storage in accordance with an evaluation function for calculating the required time. The storage access control unit executes an adjustment process to fill a time gap between the time required to access the newer generation storage and time estimated to be required to access the older generation storage.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: December 23, 2014
    Assignees: Sony Corporation, Sony Computer Entertainment Inc.
    Inventor: Keiichi Aoki
  • Publication number: 20140372695
    Abstract: A new data block to be stored in the dispersed storage system is received. When it is determined that a previous data segment contains sufficient space for the new data block, the previous data segment is retrieved from a plurality of dispersed storage units. A revised data segment is generated by aggregating the new data block with at least one existing data block of the previous data segment. A plurality of slices are generated for the revised data segment. The plurality of slices are stored in the plurality of dispersed storage units.
    Type: Application
    Filed: March 30, 2010
    Publication date: December 18, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Zachary J. Mark, S. Christopher Gladwin
  • Patent number: 8914603
    Abstract: A device is provided for use with a content provider that is operable to provide content, which includes a plurality of content components. The device includes a communication portion, a memory portion, a parsing portion, a counting portion and a processing portion. The communication portion can receive the content from the content provider. The parsing portion can parse the content into the plurality of content components and can store the parsed plurality of content components within the memory portion. The counting portion can provide a counter for each of the parsed plurality of content components within the memory portion, respectively. The processing portion can retrieve and process one of the parsed plurality of content components within the memory portion. The counting portion can further increment the counter associated with the retrieved one of the parsed plurality of content components within the memory portion.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: December 16, 2014
    Assignee: Motorola Mobility LLC
    Inventor: Krishna Prasad Panje
  • Patent number: 8914567
    Abstract: A computer system (a method) for providing storage management solution that enables server virtualization in data centers is disclosed. The system comprises a plurality of storage devices for storing data and a plurality of storage management drivers configured to provide an abstraction of the plurality of the storage devices to one or more virtual machines of the data center. A storage management driver is configured to represent a live disk or a snapshot of a live disk in a virtual disk image to the virtual machine associated with the driver. The driver is further configured to translate a logical address for a data block to one or more physical addresses of the data block through the virtual disk image. The system further comprises a master server configured to manage the abstraction of the plurality of the storage devices and to allocate storage space to one or more virtual disk images.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: December 16, 2014
    Assignee: VMware, Inc.
    Inventors: Alex Miroshnichenko, Serge Pashenkov, Serge Shats
  • Patent number: 8909863
    Abstract: A request for application information can be received from an application running in a process. The application information can be requested from an information repository, and received back from the repository in a first format. The application information can be converted to a second format, and passed to the application in the second format. In addition, the application information can be saved in the second format in a cache in the process. Also, when application information has been cached in response to a request for the information for a first user object, and a subsequent request for the application information for a second user object is received, it can be determined whether the second user object is authorized to access the application information. If so, then the application information can be fetched from the cache and returned for use by the second user object.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: December 9, 2014
    Assignee: Microsoft Corporation
    Inventors: Matthew A. Neerincx, Zlatko V. Michailov, Chadwin J. Mumford