Accessing, Addressing Or Allocating Within Memory Systems Or Architectures (epo) Patents (Class 711/E12.001)
  • Patent number: 11966301
    Abstract: An application may store data to a dataset comprising a plurality of volumes stored on a plurality of storage systems. The application may request a dataset image of the dataset, the dataset image comprising a volume image of each volume of the dataset. A dataset image manager operates with a plurality of volume image managers in parallel to produce the dataset image, each volume image manager executing on a storage system. The plurality of volume image managers respond by performing requested operations and sending responses to the dataset image manager in parallel. Each volume image manager on a storage system may manage and produce a volume image for each volume of the dataset stored to the storage system. If a volume image for any volume of the dataset fails, or a timeout period expires, a cleanup procedure is performed to delete any successful volume images.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: April 23, 2024
    Assignee: NetApp, Inc.
    Inventors: Stephen Wu, Prathamesh Deshpande, Manan Patel
  • Patent number: 11966487
    Abstract: A system deletes and sanitizes files in a distributed file system. The system also randomizes rotation of data in a distributed file system.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: April 23, 2024
    Assignee: Raytheon Company
    Inventors: Nicholas Wayne Barrett, Gregory Andrew Early
  • Patent number: 11966600
    Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Deping He, David Aaron Palmer
  • Patent number: 11960732
    Abstract: A method for allocating a drive letter to hot-swapped, newly-inserted, or doubly-identified hard disks obtains a number of hard disks connected and information of each device, the device information comprises slot information of the hard disk. A transitional drive letter is allocated to the hard disk according to their number and information of those devices, the transitional drive letter comprises a slot number corresponding to the slot information. A system drive letter is reallocated to the hard disk according to an order of the drive letter issued as a transitional drive letter. An electronic device and a non-volatile storage medium therein, for performing the above-described method, are also disclosed.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: April 16, 2024
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventor: Jian-Hua Zhu
  • Patent number: 11960426
    Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: April 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Rajat Rao, Patrick James Meaney, Glenn David Gilda, Michael Jason Cade, Robert J Sonnelitter, III, Hubert Harrer, Xiaomin Duan, Christian Jacobi, Arthur O'Neill
  • Patent number: 11962513
    Abstract: A method for managing data processes in a network of computing resources includes: receiving at least one child request being routed from an intermediary device to at least one corresponding destination device, the at least one child request requesting execution of at least one corresponding child data process, each of the at least one child data process for executing at least a portion of the at least one parent data process from an instructor device, and each of the at least one child request including a destination key derived at least in part from the at least one instructor key; storing the at least one child request in at least one storage device; modifying the at least one child request upon receiving a child request modification signal; and generating signals for communicating the child requests to one or more requesting devices.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: April 16, 2024
    Assignee: ROYAL BANK OF CANADA
    Inventors: Walter Michael Pitio, Philip Iannaccone, James Brown, Stephen Arthur Bain
  • Patent number: 11954065
    Abstract: A process of extending retention periods of records. In operation, an electronic computing device identifies a retention period associated with the record. The device obtains information related to a future event. The information includes a time period during which the future event is predicted or scheduled to occur and a location at which the future event is predicted or scheduled to occur. When the device determines that the record is contextually related to the future event based at least in part on the time period or the location of the future event, the retention period associated with the record is extended. The device may also automatically extend retention periods of records based on a number of other retention-related factors associated with the record including recording content, record trustworthiness, recording time, recording location, recording data type, recording source, recording officers' profile and their association, crime statistics, incident severity, and the like.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: April 9, 2024
    Assignee: MOTOROLA SOLUTIONS, INC.
    Inventors: Stuart J Boutell, Chris A Kruegel, Stefan Koprowski, Grzegorz Gustof
  • Patent number: 11954350
    Abstract: A storage device includes a memory device, and a memory controller configured to receive data and a log related to a property of the data from an external host, allocate a super block in which the data in the memory device is to be stored and a physical zone in the super block based on the log of the data, and store information for the log of the data stored for each physical zone and a time point at which a physical zone of a full state in which an empty area does not exist is switched to the full state. The memory controller controls the memory device to perform garbage collection according to the number of physical zones of an empty state, and selects a victim physical zone based on the information for the log of the data and a full state switch time point.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: April 9, 2024
    Assignee: SK hynix Inc.
    Inventors: Soon Yeal Yang, Jung Ki Noh
  • Patent number: 11954078
    Abstract: Examples described herein include virtualized file servers which may include cloned instances of the virtualized file server. Cloning a virtualized the server may allow for testing of new and/or revised features, disaster recovery plans, or other configurations while maintaining availability of the parent (e.g., source) virtualized file server.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: April 9, 2024
    Assignee: Nutanix, Inc.
    Inventors: Kalpesh Ashok Bafna, Anil Kumar Gopalapura Venkatesh, Devyani Suryakant Kanada, Saurabh Tyagi, Vijaykumar Bellubbi, Mausumi Ranasingh, Rishabh Sharma
  • Patent number: 11954351
    Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory regions; and a controller in communication with the nonvolatile memory device to control operations of the nonvolatile memory device and configured to: receive a first write request including a first logical address and a second logical address; determine a duplicate physical address mapped to the second logical address; and selectively map the first logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: April 9, 2024
    Assignee: SK HYNIX INC.
    Inventor: Eu Joon Byun
  • Patent number: 11954335
    Abstract: Reliability in a storage system can be easily and appropriately improved. In a computer system including a storage system configured to provide a plurality of instances in any one of a plurality of subzones divided by risk boundaries, a processor of the computer system is configured to make a storage controller that controls I/O processing for a volume based on a capacity pool provided by a plurality of storages redundant to the plurality of instances provided in the plurality of subzones.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: April 9, 2024
    Assignee: HITACHI, LTD.
    Inventors: Takaki Nakamura, Hideo Saito, Naruki Kurata, Takahiro Yamamoto
  • Patent number: 11954337
    Abstract: A method, a computer program product, and a system for initializing components to monitor for unauthorized encryptions of filesystem objects stored on a computing system. The method includes configuring an encryption monitor register to establish monitoring preferences of filesystem objects and allocating a predetermined size of persistent memory as a backup memory area for storing pre-encrypted versions of the filesystem objects. The method also includes inserting a starting address of the backup memory area in data bits of the encryption monitor register, and setting encryption monitor bits of page table entries in a hardware page table that correspond to at least one filesystem object, thereby establishing encryption monitoring of the filesystem object.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ramanjaneya Sarma Burugula, Joefon Jann, Niteesh Kumar Dubey, Ching-Farn Eric Wu
  • Patent number: 11954349
    Abstract: The embodiments of the present disclosure relate to a memory system and operating method thereof. According to embodiments of the present disclosure, the memory system may include i) a memory device including a plurality of memory blocks each including a plurality of pages, and ii) a memory controller configured to monitor a program operation on a first super memory block among a plurality of super memory blocks each including at least one of the plurality of memory blocks, and execute a target operation on the first super memory block based on the state of the first super memory block when it is determined that the program operation on the first super memory block has not been executed for a preset time period from a preset reference time point.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 9, 2024
    Assignee: SK hynix Inc.
    Inventor: Young Soo Lim
  • Patent number: 11947843
    Abstract: Provided is a method of controlling a RAID controller, the method including generating, by the RAID controller, a command sequence, and transmitting, by the RAID controller, when a first cache barrier command included in the command sequence is identified, at least one cache barrier command to an arbitrary disk constituting a RAID before transmitting a first write command arranged after the first cache barrier command in the command sequence to the arbitrary disk.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: April 2, 2024
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventor: Youjip Won
  • Patent number: 11947803
    Abstract: Techniques for providing effective utilization of different drive capacities in storage appliances. The techniques include providing a storage drive array that has a first set of storage drives and a second set of storage drives. Each storage drive in the first set has a first drive capacity and each storage drive in the second set has a second drive capacity. The first drive capacity is higher than the second drive capacity. The techniques include allocating, within the first drive capacity, at least a first sub-capacity and a second sub-capacity. The first sub-capacity is equal to the second drive capacity. The techniques include placing blocks of hot data in the first sub-capacities of the storage drives in the first set and/or the second drive capacities of the storage drives in the second set, and placing blocks of cold data in the second sub-capacities of the storage drives in the first set.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 2, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Daniel E. Cummins, Vamsi K. Vankamamidi, Shuyu Lee
  • Patent number: 11947839
    Abstract: A storage device includes: protected memory including one or more log pages; non-volatile memory; and a storage controller. The storage controller includes: a command fetcher to receive a data request command associated with data including first metadata and second metadata, and execute the data request command in the non-volatile memory; a logger to identify the second metadata, and log the second metadata in the one or more log pages; and a log page fetcher/eraser to retrieve the second metadata from the one or more log pages in response to a separate command.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: April 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rekha Pitchumani, Yangwook Kang, Yang Seok Ki
  • Patent number: 11941290
    Abstract: A memory access command to be performed on a die of a memory device is received, wherein the memory access command comprises a base partition number and a base page address. The memory access command is converted into a plurality of commands based on a number of partitions associated with the die. A respective partition number derived from the base partition number is determined for each command of the plurality of commands. A respective page address associated with each command of the plurality of commands is determined using the base page address. The plurality of commands is executed using, for each command of the plurality of commands, the respective partition number and the respective page address.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Bharani Rajendiran, Jason Duong, Chih-Kuo Kao, Fangfang Zhu
  • Patent number: 11942174
    Abstract: Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Chun S. Yeung, Deping He, Jonathan S. Parry
  • Patent number: 11941476
    Abstract: A contactless communication medium according to an embodiment of the present technology includes an IC module, a first member, a second member, and a print layer. The IC module is capable of performing a contactless communication. The first member is made of a first transparent resin material, the first member including a first surface and a second surface, the first surface being a surface in which a concave portion that accommodates therein the IC module is formed, the second surface being situated opposite to the first surface. The second member is made of a second transparent resin material, the second member being connected to the first surface or the second surface. The print layer is arranged between the first member and the second member.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 26, 2024
    Assignee: SONY GROUP CORPORATION
    Inventor: Aki Nakano
  • Patent number: 11940907
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: March 26, 2024
    Assignee: INTEL CORPORATION
    Inventors: Martin-Thomas Grymel, David Bernard, Niall Hanrahan, Martin Power, Kevin Brady, Gary Baugh, Cormac Brick
  • Patent number: 11940926
    Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Stephen Hanna
  • Patent number: 11934266
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Patrick Khayat, Sampath Ratnam, Kishore Kumar Muchherla, Jiangang Wu, James Fitzpatrick
  • Patent number: 11928492
    Abstract: Techniques are provided for managing quality of service (QoS) policies in a virtual storage environment. A data storage system receives a request from a host system to connect to a target virtual volume in a storage array of the data storage system, and determines a protocol endpoint which has an assigned QoS policy which corresponds to a QoS policy of the target virtual volume. The data storage system binds the target virtual volume to the protocol endpoint which is determined to have an assigned QoS policy which corresponds to the QoS policy of the target virtual volume, and sends a unique identifier of the protocol endpoint, which is bound to the target virtual volume, to the host system. The data storage system utilizes the protocol endpoint, which is bound to the target virtual volume, to handle data access requests received from the host system for accessing the target virtual volume.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 12, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Osnat Shasha, Rivka Matosevich
  • Patent number: 11929133
    Abstract: An apparatus is provided, comprising a controller, a plurality of memory devices operably connected to the controller, circuitry configured to measure a performance metric for each of the plurality of memory devices, and circuitry configured to select, based upon the measured performance metric, a subset of the plurality of memory devices to disable in response to a recovery command. Information corresponding to the selected subset cam be stored in a mode register of the apparatus, and the apparatus can further comprise circuitry configured, in response to a recovery command, to disable the subset of the plurality of memory devices.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Rachael Skreen
  • Patent number: 11928338
    Abstract: A method of measuring durability of a nonvolatile memory device that includes a plurality of memory blocks, the method including: periodically receiving a read command for a first memory block among the plurality of memory blocks; periodically performing a read operation on the first memory block based on the read command; periodically outputting at least one cell count value associated with the first memory block based on a result of the read operation; and periodically storing durability information associated with the first memory block in response to a periodic reception of the durability information, the durability information being obtained by accumulating the at least one cell count value.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunkyo Oh, Sanghyun Choi, Kangho Roh
  • Patent number: 11922052
    Abstract: A method including generating a new storage object derived from an existing storage object, wherein the new storage object has a first historical record identifying previous actions taken to generate the existing storage object. The method further includes generating a second historical record for the new storage object, wherein the second historical record represents the first historical record and an action that generated the new storage object from the existing storage object.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: March 5, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Andrew Sillifant, Taher Vohra, Robert Lee, Michael Richardson
  • Patent number: 11921587
    Abstract: A backup of a current state of a storage is determined to be initiated. A previous state of the storage storing key-object entries is analyzed to identify parallelization partition identifiers. At least a portion of the partition identifiers is used as boundaries between subgroups of the key-object entries processed in parallel to perform the backup of the current state of the storage.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 5, 2024
    Assignee: Cohesity, Inc.
    Inventors: Amandeep Gautam, Venkata Ranga Radhanikanth Guturi
  • Patent number: 11921640
    Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: March 5, 2024
    Assignee: Apple Inc.
    Inventors: Tyler J. Huberty, Vivek Venkatraman, Sandeep Gupta, Eric J. Furbish, Srinivasa Rangan Sridharan, Stephan G. Meier
  • Patent number: 11922066
    Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: March 5, 2024
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Michael Raymond Miller, Steven C. Woo
  • Patent number: 11922020
    Abstract: A read-disturb-based read temperature information persistence system includes a storage device coupled to a host subsystem. The storage device receives a first instruction from the host subsystem to write first data to the storage device, writes the first data to a first block in the storage device, and determines first read temperature(s) for the first data based on first read disturb information associated with the first block in the storage device. When a second instruction is received from the host subsystem to write second data to the storage device that is an updated version of the first data, the storage device identifies the first read temperature(s) determined for the first data in the first block in the storage device, and writes the second data and a first read temperature indication of the at least one first read temperature to a second block in the storage device.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: March 5, 2024
    Assignee: Dell Products L.P.
    Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson
  • Patent number: 11922042
    Abstract: A method is described.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 5, 2024
    Assignee: Scality, S.A.
    Inventors: Lam Pham Sy, Frederic Ferrandis, Benoit Artuso
  • Patent number: 11921650
    Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: March 5, 2024
    Assignee: Rambus Inc.
    Inventor: Liji Gopalakrishnan
  • Patent number: 11914485
    Abstract: A request to obtain an identified content item is received. It is determined that the identified content item is stored in a plurality of locations. It is determined to obtain the identified content item from a first storage location storing a first serialized representation of a file system snapshot that includes the identified content item and a second storage location storing a second serialized representation of the file system snapshot that includes the identified content item based on available resources associated with the plurality of locations. The identified content item is extracted from the first serialized representation at the first storage location and from the second serialized representation at the second storage location including building a stubbed tree data structure using the first serialized representation and the second serialized representation. The extracted identified content item is provided using the stubbed tree data structure.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Cohesity, Inc.
    Inventors: Prashant Pogde, Markose Thomas, Venkata Ranga Radhanikanth Guturi, Akshat Agarwal, Praveen Kumar Yarlagadda
  • Patent number: 11907541
    Abstract: Techniques for providing an adaptive approach to prefetching data for sequential read streams in a storage system. The techniques can include performing prefetch operations for a sequential read stream in accordance with a prefetch distance and a prefetch size, counting or otherwise keeping track of occurrences of failure scenarios in the prefetch operations while servicing the sequential read stream, and modifying or adjusting one of the prefetch distance and the prefetch size based on the occurrences of the respective failure scenarios. In this way, host input/output (IO) latency can be reduced, and IO bandwidth can be increased, in the servicing of sequential read streams by the storage system.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: February 20, 2024
    Assignee: Dell Products L.P.
    Inventors: Andrew Feld, Philippe Armangau, Christopher A. Seibel, Christopher Jones
  • Patent number: 11907127
    Abstract: In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: February 20, 2024
    Assignee: SMART IOPS, INC.
    Inventors: Ashutosh Kumar Das, Manuel Antonio d'Abreu
  • Patent number: 11907575
    Abstract: A memory controller includes: a first buffer configured to receive a memory request from a host and store therein the received memory request; a command generator configured to generate a first command corresponding to the memory request, and set a type of the first command indicating whether an address comprised in the memory request corresponds to a processing in memory (PIM) memory; a second buffer configured to store therein a plurality of commands comprising the first command; and a command scheduler configured to determine whether to change an order of the first command stored in the second buffer based on the type of the first command.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hosang Yoon, Seungwon Lee
  • Patent number: 11899930
    Abstract: An object of the present invention is to reduce deterioration in responsiveness to storage of content in a flash memory. A storage management apparatus according to the present invention includes a flash memory including a plurality of blocks each having a reserved area and a normal area, acquires a new dataset when a writable area included in a normal area of the plurality of blocks is larger than the new dataset and the new dataset is smaller in size than the writable area included in the normal area of the plurality of blocks in a case where unnecessary datasets included in the plurality of blocks are deleted, copies non-unnecessary datasets from the normal area of a specific block including the unnecessary datasets to the normal area of another block, deletes all datasets included in the normal area of the specific block, and stores the new dataset in the normal area of the specific block from which all the datasets are deleted.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: February 13, 2024
    Assignee: SONY INTERACTIVE ENTERTAINMENT INC.
    Inventors: Keiichi Aoki, Masaki Takahashi
  • Patent number: 11899575
    Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: February 13, 2024
    Assignee: Radian Memory Systems, Inc.
    Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
  • Patent number: 11899983
    Abstract: A semiconductor storage device includes a non-volatile first memory, a second memory that includes a first area for recording data to be recorded in the first memory and a second area for recording data read from the first memory, and a memory controller that controls the first memory.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: February 13, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Yohei Kato
  • Patent number: 11900142
    Abstract: Systems and methods for memory management for nested virtual machines. An example method may comprise running, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, wherein the Level 2 virtual machine is associated with a Peripheral Component Interconnect (PCI) device; generating, by the Level 0 hypervisor, a Level 1 page table by combining records from the guest page table with records from a host page table maintained by the Level 0 hypervisor; generating a Level 2 page table comprising a plurality of Level 2 page table entries; and causing a device driver of the Level 2 virtual machine to use the Level 2 page table for second level address translation.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: February 13, 2024
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Amnon Ilan
  • Patent number: 11892906
    Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: February 6, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Thomas Rabenalt, Michael Goessel
  • Patent number: 11895560
    Abstract: A distributed type traffic line tracing apparatus of the present disclosure is personally installed in a residence of a tracing target person, to automatically verify whether a traffic line of the tracing target person coincides with a traffic line of a confirmed person and automatically report a result to a disease management authority only when the traffic lines coincide with each other in an emergency situation such as an infectious disease pandemic, so that a quarantining target person is discovered and found early while protecting a privacy of an individual much more when compared to a centralized type, thereby rapidly establishing an infectious disease management system for patients with suspected diseases and efficiently managing the patients from the spread of infectious diseases.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 6, 2024
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventor: Jae-Chern Yoo
  • Patent number: 11893273
    Abstract: A method of writing to a tiered memory system of a computing device, the tiered memory system including volatile memory and persistent memory (PMEM), includes the steps of: in response to a first write request including first data to write to a first page of the tiered memory system, copying contents of the first page to a second page located in the PMEM; after copying the contents of the first page to the second page, writing the first data to the second page; and after writing the first data to the second page, updating a first mapping of the tiered memory system to reference the second page instead of the first page.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 6, 2024
    Assignee: VMware, Inc.
    Inventors: Robert T. Johnson, Alexander John Horton Conway, Yi Xu, Aishwarya Ganesan, Ramnatthan Alagappan
  • Patent number: 11892977
    Abstract: A method that includes instructing multiple compute entities, by an expansion manager and during a first phase of the stored entity metadata re-balancing, to: lookup any stored entity metadata by using: (a) a current translation function for linking identifiers of stored entities to stored entities metadata; wherein the current translation function is based on a size of a current storage space allocated to stored entities metadata; and (b) a next translation function for linking identifiers of stored entities to stored entities metadata; wherein the next translation function is based on a size of a next storage space allocated to stored entities metadata; wherein the current space is expanded during the expansion of the storage system to provide the next storage space, and to update any stored entity metadata accessed using the current translation function without updating stored entity metadata accessed using the next translation function.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: February 6, 2024
    Assignee: VAST DATA LTD.
    Inventors: Ido Yellin, Avi Goren, Oded Sonin
  • Patent number: 11886412
    Abstract: An indication to perform a backup of file system data is received. The file system data includes a content file having a size greater than a threshold size. A plurality of component file metadata structures for the content file are generated. File metadata of the content file split across the plurality of component file metadata structures is stored. The plurality of component file metadata structures are associated with different portions of the content file. A component file metadata structure of the plurality of component file metadata structures stores file metadata corresponding to a portion of the content file. The file metadata corresponding to the portion of the content file includes one or more references to locations of data chunks associated with the portion of the content file.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: January 30, 2024
    Assignee: Cohesity, Inc.
    Inventors: Zhihuan Qiu, Ganesha Shanmuganathan
  • Patent number: 11886300
    Abstract: The data duplication system comprises a first storage device having a first data protection area for storing backup images of multiple generations of a first volume for data read/write by an external device. The first data protection area is inaccessible to the external device. A second storage device coupled to the first storage device. The first storage device creates a second volume for storing a backup image of a particular generation of the plurality of generations of backup images stored in the first data protection area. The second storage device creates a third volume for storing the copy data, and a virtual volume that is mapped to the second volume of the first storage device. The second storage stores the backup data of a specific generation stored in the second volume in the third volume via the virtual volume by forming a pair that copies the data in the virtual volume and the third volume.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: January 30, 2024
    Assignee: HITACHI, LTD.
    Inventors: Shunsuke Nishiyama, Kenichi Oyamada, Hiroki Mera, Goro Kazama
  • Patent number: 11880337
    Abstract: Techniques are provided for on-demand creation and/or utilization of containers and/or serverless threads for hosting data connector components. The data connector components can be used to perform integrity checking, anomaly detection, and file system metadata analysis associated with objects stored within an object store. The data connector components may be configured to execute machine learning functionality to perform operations and tasks. The data connector components can perform full scans or incremental scans. The data connector components may be stateless, and thus may be offlined, upgraded, onlined, and/or have tasks transferred between data connector components. Results of operations performed by the data connector components upon base objects may be stored within sibling objects.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: January 23, 2024
    Assignee: NetApp, Inc.
    Inventors: Sharankumar Yelheri, Atul Ramesh Pandit, Tijin George, Kiran Nenmeli Srinivasan, Jeffrey David Prem
  • Patent number: 11880348
    Abstract: A database management system maintains a collection of data using a log-based storage structure. In response to a request to store data items (key-value pairs), the database management system stores mapping information to a data item in an in-memory data structure while the data items are stored on the log-based storage structure. The hash of the key includes information to identify an index entry that comprises information that maps to the location of the data item stored on the log-based storage structure.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: January 23, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Gourav Roy, Qu Chen, Allen Robert Samuels, Kevin R McGehee, Itay Maoz, Abhishek Kumar, Juan Carlos Gomez, Jan Raak, Ahmed Hesham Salem
  • Patent number: 11880298
    Abstract: One embodiment provides for a non-transitory machine-readable medium storing instructions to cause one or more processors to perform operations comprising receiving an instruction to dynamically allocate memory for an object of a data type and dynamically allocating memory for the object from a heap instance that is specific to the data type for the object, the heap instance including a memory allocator for the data type, the memory allocator generated at compile time for the instruction based on a specification of the data type for the heap instance.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: January 23, 2024
    Assignee: Apple Inc.
    Inventor: Filip J. Pizlo
  • Patent number: 11874769
    Abstract: A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device. The processing device further uses a first indicator and a second indicator of a plurality of indicators to indicate which data of data management units of a source group of data management units have been copied to a destination group of data management units during the media management operation. Data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units. Data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Ning Chen, Jiangli Zhu, Ying Yu Tai