Abstract: A computer implemented method for creating a tree of database states including accessing a database having at least one branch of database states, receiving at the database one or more write events that are applied to an identified state of the database, recovering the identified database state from the database, creating a new branch by creating a new patch as alternative state to the identified database state with a reference to the identified state.

Abstract: A computing platform comprising a first computer system including a first host and a first accelerator communicatively coupled to the first host, including a first memory, a first page table to perform a translation of virtual addresses to physical addresses in the first memory and a first trusted agent to validate the address translations.

Abstract: Framed event access in an ordered event stream (OES) storage system is disclosed. Events can be written to one or more segments of an OES and can have an inherent write sequence. Segments can be parallel segments. Reading events from parallel segments can result in a read sequence that does not match the write sequence. This mismatch can be more severe as segment length increases, as event density disparities increase, as access times diverge for different segments, or for numerous other reasons. Event framing can compartmentalize divergence between the write and read sequence. In an aspect, readers in the several segments of the OES can be constrained to read within a frame defined by frame boundaries until all readers have reached the frame boundary, then can advance to a next frame. The restriction can act as a pseudo-synchronization of readers that can mitigate difference between write and read sequences.

Abstract: A method for recovering data includes obtaining a recovery request for application data, identifying a backup associated with the recovery request, generating a placeholder disk associated with the backup, generating a template virtual machine associated with the placeholder disk, generating an application-based virtual disk based on the placeholder disk, generating a file extent map based on the recovery request, populating the application-based virtual disk using the backup, the placeholder disk, and the file extent map to obtain a populated application-based virtual disk, replacing the placeholder disk with the populated application-based virtual disk, and after replacing the placeholder disk with the populated application-based virtual disk, initiating a migration of the template virtual machine.

Abstract: The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors and an inter-processor communication (IPC) unit. The IPC unit includes one or more doorbell registers, wherein each doorbell register is associated with a uniquely assigned source processor and a uniquely assigned target processor. Each doorbell register is further configured to store doorbell data indicative of whether an interrupt is a high priority interrupt or a low priority interrupt. The IPC unit may also include one or more FIFO (first-in first-out) memories configured to store data associated with each interrupt.

Abstract: A memory device includes a non-volatile memory chip, a connector and a memory controller. The non-volatile memory chip includes an access partition and a hidden partition. The memory controller is used to set first logical blocks mapping to mapping physical blocks in the access partition. The memory controller is used to maintain a first mapping table recording the first logical blocks and the mapping physical blocks. During backup, the memory controller is used to duplicate data in the mapping physical blocks to the hidden partition according to the first mapping table to form backup physical blocks, and establish a second mapping table setting second logical blocks to map to the backup physical blocks. During recovery, the memory controller is used to map the second logical blocks to the backup physical blocks according to the second mapping table for the host system to recover an environment set at the backup operation.

Abstract: A data processing system includes a control register, a program counter and a controller. The control register is used to store a level status of an execution flow and at least one return address. When the controller reads a block call instruction while a level status of the execution flow has an initial value, the controller stores a return address of the block call instruction in the control register, increments a value of the level status, and redirects the execution flow to a target address indicated by the block call instruction. When the controller reads a block return instruction and the value of the level status is not equal to the initial value, the controller decrements the value of the level status. If the value of the level status becomes equal to the initial value, the controller redirects the execution flow to the return address.

Abstract: A low cost IC solution is disclosed in accordance with an embodiment to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are composed of diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

Abstract: The present invention concerns a device and a method at the device for selecting and configuring a default storage section. The device comprises connecting means for connecting at least one storage device comprising storing means to the device, characterized in that it comprises a selector for selecting a storage device, the selected storage device becoming the default storage section, configuring means for, on selection of a default storage section, partitioning the storing means of the default storage section into more than one directory, and securing means for defining access rights to the more than one directory.

Abstract: Aspects include a system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined whether the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations managed in different zones of memory. Based on determining that the memory address refers to the SMO, it is determined whether the configuration has access to the SMO. Based on determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the configuration and the plurality of configurations is allowed.

Abstract: In a distributed computing system that includes compute nodes that include computer memory, globally accessible memory space is administered by: for each compute node: mapping a memory region of a predefined size beginning at a predefined address; executing one or more memory management operations within the memory region, including, for each memory management operation executed within the memory region: executing the operation collectively by all compute nodes, where the operation includes a specification of one or more parameters and the parameters are the same across all compute nodes; receiving, by each compute node from a deterministic memory management module in response to the memory management operation, a return value, where the return value is the same across all compute nodes; entering, by each compute node after local completion of the memory management operation, a barrier; and when all compute nodes have entered the barrier, resuming execution.

Abstract: One embodiment of the present invention sets forth a technique for reducing the copying of data between memory allocated to a primary processor and a coprocessor is disclosed. The system memory is aliased as device memory to allow the coprocessor and the primary processor to share the same portion of memory. Either device may write and/or read the shared portion of memory to transfer data between the devices rather than copying data from a portion of memory that is only accessible by one device to a different portion of memory that is only accessible by the other device. Removal of the need for explicit primary processor memory to coprocessor memory and coprocessor memory to primary processor memory copies improves the performance of the application and reduces physical memory requirements for the application since one portion of memory is shared rather than allocating separate private portions of memory.

Abstract: A computer implemented method for sharing physical memory among logical partitions. A computer reserves physical memory of a Central Electronic Complex (CEC) for communication within the CEC as a shared memory pool. The computer creates a first logical partition using resources of the CEC that are not reserved as the shared memory pool. The computer creates a second logical partition using resources of the CEC that are not reserved as the shared memory pool. The computer creates a virtual local area network (VLAN) having at least two addresses within the CEC. The computer allocates a portion of the shared memory to the VLAN as the shared memory pool.

Abstract: A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined if the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations. In response to determining that the memory address refers to the SMO, it is determined if the configuration has access to the SMO. In response to determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the plurality of configurations is allowed.

Abstract: A method and system writes data to a memory device including writing data to varying types of physical write blocks. The method includes receiving a request to write data for a logical block address within an LBA range to the memory device. Depending on whether the quantity of valid data in the memory device meets a predetermined criteria, the data is written to a specific chaotic block, a general chaotic block, or a mapped block. The mapped block is assigned for writing data for the LBA range, the specific chaotic block is assigned for writing data for contiguous LBA ranges including the LBA range, and the general chaotic block is assigned for writing data for any LBA range. Lower fragmentation and write amplification ratios may result by using this method and system.

Abstract: An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory.

Abstract: A computer implemented method for automatically managing copies of source data volumes is provided. A copy management agent receives a message that target volume copies of source volumes are available. The copy management agent accesses the target volume copies of the source volumes. The copy management agent analyzes metadata for the target volume copies. The copy management agent determines whether any of the target volume copies is a boot volume copy based on the analyzed metadata. In response to a determination that one of the target volume copies is a boot volume copy, the copy management agent directs a provisioning agent to provision a new host for the target volume copies. The copy management agent directs the storage subsystem to present the target volume copies to a storage area network port associated with the new host. Then, the new host is booted using the boot volume copy.

Abstract: The present disclosure discloses a method of complete mutual access of multiple-processors. The method comprises: a separate boot memory and a separate address mapping module are allocated for each processor; the processors perform the mutual access in the multiple-processors through the address mapping module after the processors are booted. The present disclosure also discloses a system for enabling complete mutual access of the multiple-processors. The method and the system creates the advantage of allowing complete mutual access of the multiple-processors, thereby sharing address space in the multiple-processors, sharing the peripheral controller and memory, improving expansibility and performance of the system.

Abstract: Various embodiments of systems and methods for processing data in shared memory are described herein. A number of work processes of an application server write data in corresponding areas of shared memory. At least one data unit for a first process is read from a first area of the shared memory by the first process. The first process also reads at least one unit of data for a second process from a second area of the shared memory. The first process writes information in a third area of the memory to indicate that the at least one unit of data for the first process and the at least one unit of data for the second process are read. The read data units are aggregated and saved in a storage by the first process.

Abstract: A method for managing storage for a desktop pool is described. The desktop pool includes a plurality of virtual machines (VMs), each VM having at least one virtual disk represented as a virtual disk image file on one of a plurality of datastores associated with the desktop pool. To identify a target datastore for a VM, a weight of each datastore is calculated. The weight may be a function of a virtual capacity of the datastore and the sum of maximum sizes of all the virtual disk image files on the datastore. The virtual capacity is a product of the data storage capacity of the datastore and an overcommit factor assigned to the datastore. The target datastore is selected as the datastore having the highest weight. The VM may is moved to or created on the target datastore.

Abstract: A remote copy system includes: a first storage system having a first logical volume accompanied with a first plurality of disk drives in the first storage system; a second storage system having a second logical volume, which is a virtual volume not accompanied with a second plurality of disk drives in the second storage system, the virtual volume configuring a first remote copy pair with the first logical volume; and a third storage system having a third logical volume accompanied with a third plurality of disk drives in the third storage system, the third logical volume configuring a second remote copy pair with the virtual volume and storing a copied data of data stored in the first logical volume. If the second storage system receives write data sent from the first storage system to the virtual volume, the second storage system transfers the write data to the third logical volume in the third storage system.

Abstract: A method and system writes data to a memory device including dynamic assignment of logical block addresses (LBAs) to physical write blocks. The method includes receiving a request to write data for a logical block address within an LBA range to the memory device. The method assigns the LBA range to a particular write block exclusively or non-exclusively, depending on the existence of previously assigned write blocks and the availability of unwritten blocks. A data structure may be utilized to record the recent usage of blocks for assigning non-exclusive write blocks. An intermediate storage area may be included that implements the dynamic assignment of LBA ranges to physical write blocks. Data in the intermediate storage area may be consolidated and written to the main storage area. Lower fragmentation and write amplification ratios may result by using this method and system.

Abstract: A method and apparatus for accelerated shared data migration between cores is disclosed.

Abstract: In a data processing system including multiple logical partitions (LPARs), an application executes on a first logical partition (LPAR) of the multiple LPARs, where the application uses a first operation system stored in a first memory partition of a shared pool memory of the data processing system. A virtualization management component (a) initiates an update process that quiesces operations of the first LPAR, (b) pages in, via a virtual input/output server coupled to a first paging device, a first image of a second operating system from the first paging device to the shared pool memory; (c) changes one or more pointers associated with the application to point to one or more portions of the second operating system, such that the application uses the second operating system, when resumed; and (b) resumes execution the application.

Abstract: A device having a shared memory and a method for providing access status information by the shared memory are disclosed. A digital processing device includes n processors and a shared memory. The shared memory is coupled to each processor though a separate bus, its storage area includes m common sections, and generates and outputs access status information related to whether an arbitrary processor is accessing at least one of the common sections. With the present invention, a control sequence of each processor can be simplified at a maximum by allowing the shared memory to generate and output access status information related to the common sections.

Abstract: A generic storage container system is provided for a grid-based storage architecture, comprising a generic storage container comprising a plurality of storage domains along one axis against a plurality of rows of stripes along another axis defining a preselected storage capacity, and configuration information allocating the stripes in response to a storage format specified by an allocation request. A method is provided for storing the data, comprising: providing the generic storage container; providing configuration information adapted for selectively allocating the stripes in relation to a data storage format; specifying a desired storage format; and allocating the stripes in response to the desired format.

Abstract: The version set backup and restore facility responds to a version set backup request by backing up multiple snapshot copies of a storage object concurrently from a storage array to backup storage media. The version set backup and restore facility responds to a version set restore request by restoring a plurality of snapshot copies of the storage object concurrently from the backup storage media to the storage array. The on-tape backup image of the version set includes variable-length extents of data for each of the multiple snapshot copies of the storage object. The variable-length extents of data for each of the snapshot copies of the storage object are grouped together and ordered in the on-tape backup image by increasing or decreasing logical block address.

Abstract: Techniques for providing arbitrary precision floating number (APFN) processing are disclosed. In some aspects, an APFN store may be used to store a large number (i.e., an APFN) having many significant digits, which in turn may enable a high degree of precision in mathematical operations. An APFN module may be used to create and define the APFN store. The APFN module may enable a user to define a precision (significant digits) for the large number that corresponds to the size of an array of bytes in the APFN store that are allocated for storing the large number. In further aspects, the APFN store may be used to store additional intermediary data and a resultant.

Abstract: Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity.

Abstract: Provided is a storage controller that will not impair the operation of a storage control system even when a new storage area is added to a pool corresponding to an AOU volume. This storage controller includes a logical volume accessible by a host system; a pool associated with the logical volume and including one or more physical storage areas configuring a storage area of the logical volume; and a memory for storing attribute information showing an attribute of a physical storage area included in the pool; wherein the controller is configured to add a new physical storage area to the pool based on the attribute information.

Abstract: The system described herein may track references to a shared object by concurrently executing threads using a reference tracking data structure that includes an owner field and an array of byte-addressable per-thread entries, each including a per-thread reference counter and a per-thread counter lock. Slotted threads assigned to a given array entry may increment or decrement the per-thread reference counter in that entry in response to referencing or dereferencing the shared object. Unslotted threads may increment or decrement a shared unslotted reference counter. A thread may update the data structure and/or examine it to determine whether the number of references to the shared object is zero or non-zero using a blocking-optimistic or a non-blocking mechanism. A checking thread may acquire ownership of the data structure, obtain an instantaneous snapshot of all counters, and return a value indicating whether the number of references to the shared object is zero or non-zero.

Abstract: According to one exemplary embodiment, a method for modifying a shared data queue accessible by a plurality of processors comprises receiving an instruction from one of the processors to produce a modification to the shared data queue, running a microcode program in response to the instruction, to attempt to produce the modification, and generating a final datum to signify whether the modification to the shared data queue has occurred. In one embodiment, the modification comprises enqueuing data, and running the microcode program includes checking writability of a write pointer of the shared data queue, checking writability of a data field designated by the write pointer, locking the write pointer and checking the old value of its lock bit with atomicity, writing the data to the data field and incrementing the write pointer by the size of the data, and unlocking the write pointer.

Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.

Abstract: An approach is provided for selective sharing of semantic information sets in a smart space interoperable across platforms, devices, and equipment. A personal smart space application creates a personal information space for a user, wherein the personal information space includes a plurality of semantic information sets. Thereafter, the personal smart space application receives a request for selective sharing of the semantic information sets, and merges, in response to the request, a projection of the selected semantic information sets into a shared information space.

Abstract: The storage controller of the present invention is able to reduce the amount of purge message communication and increase the processing performance of the storage controller. Each microprocessor creates and saves a purge message every time control information in the shared memory is updated. After a series of update processes are complete, the saved purge messages are transmitted to each microprocessor. To the control information, attribute corresponding to its characteristics is established, and cache control and purge control are executed depending on the attribute.

Abstract: A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate.

Abstract: A method and system for generating a web log that includes transaction entries from transaction queues of one or more cores of a multi-core system. A transaction queue is maintained for each core so that either a packet engine or web logging client executing on the core can write transaction entries to the transaction queue. In some embodiments, a timestamp value obtained from a synchronized timestamp variable can be assigned to the transaction entries. When a new transaction entry is added to the transaction queue, the earliest transaction entry is removed from the transaction queue and added to a heap. Periodically the earliest entry in the heap is removed from the heap and written to a web log. When an entry is removed from the heap, the earliest entry in a transaction queue corresponding to the removed entry is removed from the transaction queue and added to the heap.

Abstract: A logically-partitioned computer system provides support for multiple logical partitions to access a single file system, thereby allowing the logical partitions to share a file without the overhead of communicating over a VLAN. An area of shared memory is defined that multiple logical partitions may access. One or more file control blocks that control access to the files in the file system are then created in the shared memory. Existing mechanisms for locking a file system between processes may then be used across logical partitions to serialize access to the file system by all processes in all logical partitions that share the file system. In this manner the sharing of files in a file system is enabled by leveraging existing technology that is used within a single logical partition to extend across multiple logical partitions.

Abstract: Shared storage architectures are provided. A particular shared storage architecture includes an Enterprise Service Bus (ESB) system. The ESB system includes shared storage including data and file system metadata separated from the data. The file system metadata includes location data specifying storage location information related to the data. An infrastructure function of the ESB system is provided to enable messaging between providers and consumers through the shared storage.

Abstract: Shared storage systems and methods are provided. A particular shared storage system is a system including multiple instances of shared storage. Each of the instances of shared storage includes data and file system metadata separated from the data. The file system metadata includes location data specifying storage location information related to the data. A persistent common view is provided of local and remote files, file systems, and services in the shared storage.

Abstract: A distributing device for generating private information correctly even if shared information is destroyed or tampered with. A shared information distributing device for use in a system for managing private information by a secret sharing method, including: segmenting unit that segments private information into a first through an nth pieces of shared information; first distribution unit that distributes the n pieces of shared information to n holding devices on a one-to-one basis; and second distribution unit that distributes the n pieces of shared information to the n holding devices so that each holding device holds an ith piece of shared information distributed by the first distribution unit, as well as a pieces of shared information being different from the ith piece of shared information in ordinal position among n pieces of shared information, “i” being an integer in a range from 1 to n.

Abstract: A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.

Abstract: Provided are a method, system, and article of manufacture for assigning alias addresses to base addresses. An assignment is provided of base addresses to the devices. The base addresses are used to access the devices assigned to the base addresses. An assignment is provided of a plurality of alias addresses to an alias address pool. The alias addresses in the alias address pool are capable of being dynamically assigned to the devices to service I/O requests to the devices. An Input/Output (I/O) request to access one target device comprising one of the devices is processed. A determination is made as to whether the base address assigned to the target device is available. One alias address is assigned to the target device in response to determining that the base address is not available. The I/O request is issued to the assigned alias address to transmit the request to the target device.

Abstract: A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item.

Abstract: A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.

Abstract: Hypervisor page fault processing logic is provided for a shared memory partition data processing system. The logic, responsive to an executing virtual processor of the shared memory partition data processing system encountering a hypervisor page fault, allocates an input/output (I/O) paging request to the virtual processor from an I/O paging request pool and increments an outstanding I/O paging request count for the virtual processor. A determination is then made whether the outstanding I/O paging request count for the virtual processor is at a predefined threshold, and if not, the logic places the virtual processor in a wait state with interrupt wake-up reasons enabled based on the virtual processor's state, otherwise, it places the virtual processor in a wait state with interrupt wake-up reasons disabled.

Abstract: One aspect relates to a computer system including a first data processing unit, a second data processing unit and a data transmission/memory device. The data transmission/memory can transmit sets of data from the first data processing unit to the second data processing unit. The data transmission/memory device includes a first memory region and a second memory region.

Abstract: The present invention discloses a modified computer architecture (50, 71, 72) which enables an applications program (50) to be run simultaneously on a plurality of computers (M1, . . . Mn). Shared memory at each computer is updated with amendments and/or overwrites so that all memory read requests are satisfied locally. During initial program loading (75), or similar, instructions which result in the application program (50) acquiring (or releasing) a lock on a particular asset (50A, 50X-50Y) (synchronization) are identified. Additional instructions are inserted (162, 163) to result in a modified synchronization routine with which all computers are updated.

Abstract: A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism.

Abstract: Method and device for providing a virtual drive on a workstation PC which is connected via a network to other workstation PCs, encompassing a driver which makes available the virtual drive and carries out the following steps: Administering a mapping table from which it is apparent which data is stored on which of the other workstation PCs, During reading of the data, checking the table and requesting data from the other workstation PC which is stored in the table, During writing of the data, checking the table to find a suitable entry in the table, sending the data to one of the other workstation PCs and entering a reference in the table on the other workstation PC which has acquired the data.