Abstract: Data is accessed in a multi-level hierarchical memory system. A request for data is received, including a virtual address for accessing the data. A translation buffer is queried to obtain an absolute address corresponding to the virtual address. Responsive to the translation buffer not containing an absolute address corresponding to the virtual address, the absolute address is obtained from a translation unit. A directory look-up is performed with the absolute address to determine whether a matching absolute address exists in the directory. A fetch request for the requested data is sent to a next level in the multi-level hierarchical memory system. Processing of the fetch request by the next level occurs in parallel with the directory lookup. The requested data is received in the primary cache to make the requested data available to be written to the primary cache.

Abstract: Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.

Abstract: A virtualization technique, in accordance with one embodiment of the present invention, includes emulating the small computing system interface (SCSI) protocol to access a virtual SCSI storage device backed by a file stored on network attached storage (NAS).

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and testing a system for providing lines of data from shared resources to caching agents are provided. The system provides for receiving a request from a caching agent for a line of data stored in a shared resource, assigning one of a plurality of coherency states as an initial coherency state for the line of data, each of the plurality of coherency states being assignable as the initial coherency state for the line of data, and providing the line of data to the caching agent in the initial coherency state assigned to the line of data.

Abstract: A memory device and method for content virtualization are disclosed. In one embodiment, a plurality of directories are created in the memory of the memory device, wherein each of the plurality of directories points to a same storage location of the digital content. In another embodiment, a first header for the digital content is stored in each of the different directories, wherein the first header comprises information about where to find the digital content in the memory. In yet another embodiment, the memory device comprises circuitry that receives an identification of a host device in communication with the memory device and reorganizes a directory structure of the memory in accordance with the identification of the host device, wherein the reorganization results in the digital content appearing to be located in a directory expected by the host device.

Abstract: A data storing system include a first and second storage system, each including a cache memory and a disk drive, and a third storage system coupled to the first and second storage systems and including a third disk drive to provide a third logical volume based on the third disk drive. First and second write data is transmitted from the first storage system to the second storage system according to copy pair management information. A certain storage system, which is one of the first and second storage systems, destages the second write data from a cache memory of the certain storage system to the third logical volume in the third storage system according to a volume and storage conversion table in the certain storage system.

Abstract: A “LUN Table” enables Logical Unit Number (LUN) mapping/masking within an Input/Output Virtualization IOV adapter included in a Serial Attached Small Computer System Interface (“SAS” or “Serial Attached SCSI”). A plurality of System Images (“SI”) share block storage through the SAS. The IOV adapter includes one or more Virtual Functions (VF), a Physical Function (PF), and a LUN Table within the PF. The VF allows each SI to communicate I/0 requests with a storage device through the PF. The LUN Table maps the I/0 requests to unique locations within the storage device. Each SI is isolated from all other SIs. Interference between each SI is avoided. A VIOS or a LUN mapping/masking SAN are not required. I/0 latency, processor overhead and storage cost are improved over prior LUN mapping/masking solutions.

Abstract: A method, including: initiating a memory operation at a first node including a first memory controller (MC) and a transaction table configured to store a list of nodes affected by the memory operation, transmitting a store request signal to a second node including a second MC and an access table (AT) where the store request signal includes data from the first MC, storing data to the AT in entries corresponding to memory address(es) (MAs) affected by the memory operation, identifying a memory conflict with one or more nodes in the list of nodes when the MAs affected by the memory operation are also affected by one or more conflicting transactions listed in the AT, transmitting an abort signal from the second node to each of the nodes corresponding to the memory conflict, and transmitting an intent to commit signal from the first node to the second node.

Abstract: A method and data processing system enables scheduling of atomic operations within a Peripheral Component Interconnect Express (PCIe) architecture during page migration. In at least one embodiment, firmware detects the activation of a page migration operation and sets a migration bit in the page table. When the PCIe Host Bridge (PHB) receives an atomic operation, the PHB checks the migration bit associated with the memory page targeted by the atomic operation and if the migration bit is set, the PHB buffers the atomic operation and sets an atomic operation stall (AOS) bit associated with the buffer. The atomic operation is stalled until the migration bit is reset, at which time the PHB resets the AOS bit of the buffer. The atomic operations are permitted to continue when the migration bit of the target memory page is not set, and along with DMA operations, may bypass other stalled atomic operations.

Abstract: One embodiment of the present invention sets forth a technique for efficiently and flexibly performing coalesced memory accesses for a thread group. For each read application request that services a thread group, the core interface generates one pending request table (PRT) entry and one or more memory access requests. The core interface determines the number of memory access requests and the size of each memory access request based on the spread of the memory access addresses in the application request. Each memory access request specifies the particular threads that the memory access request services. The PRT entry tracks the number of pending memory access requests. As the memory interface completes each memory access request, the core interface uses information in the memory access request and the corresponding PRT entry to route the returned data.

Abstract: The flash file system includes a flash memory and a subsystem interfacing between the flash memory and a host system. The subsystem includes a hierarchical structure of a host system interface, cache memory system, flash translation layer unit and a flash memory interface. The host system interface interfaces with the host system. The cache memory system has a storage capacity of a predetermined number of data units and stores data for transfer to and from the host system via the host system interface. The flash translation layer unit maps a logical address received from the host system via the host system interface and the cache memory into a physical address of the flash memory.

Abstract: A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions.

Abstract: A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.

Abstract: Disclosed are a method, information processing system, and computer readable medium for scanning a storage medium table. The method includes retrieving location information associated with at least one other storage medium table scan. A storage medium table scan is started at a location within a storage medium table based on at least a location of the one other storage medium table scan. A weight is assigned to at least one storage medium block based on at least a current scanning location within the storage medium table relative to the location of the one other table scan. The method determines if a distance between the current scanning location and the location of the one other table scan is greater than a first given threshold. A current scanning operation is delayed, in response to the distance being greater than the given threshold, until the distance is below a second given threshold.

Abstract: A system, method and computer-readable medium for updating an address translation table. In the method, a message indicating a physical memory location that corresponds to a virtual address is received from a processor. An I/O Memory Management Unit (IOMMU) is used to update an entry within the address translation table corresponding to the virtual address according to the indicated physical memory location.

Abstract: In one embodiment, the present invention includes a virtual machine monitor (VMM) to access a protection indicator of a page table entry (PTE) of a page of a set of memory buffers and determine a state of the protection indicator, and if the protection indicator indicates that the page is a user-level page and if certain information of an agent that seeks to use the page matches that in a protected memory address array, a page table base register (PTBR) is updated to a protected page table (PPT) base address. Other embodiments are described and claimed.

Abstract: Some embodiments are directed to a technique for storing and/or locating content units stored on an object addressable storage (OAS) system, wherein each content unit is identified by an object identifier. The OAS system may comprise a plurality of zones, each of which stores content units. A mapping process may be defined that maps object identifiers for content units to zones on the OAS system. Thus, the storage location for a content unit on the OAS system may be the zone on the OAS system to which the object identifier for the content unit maps.

Abstract: A lookup unit matrix combines a plurality of lookup units to provide a longest prefix match for a search key longer than the lookup unit's mapper key. A portion of the search key is provided to each of the plurality of lookup units in a single search request issued to the lookup unit matrix. Each lookup unit in the lookup unit matrix performs a multi-level search for the result value based on the portion of the search key forwarded as the mapper key and the result of a multilevel search in the previous lookup unit. The search results in a value corresponding to the search key stored in a single location in one of the lookup units.

Abstract: Provided are an embedded system and a method for relocating memory pages therefor. The embedded system includes a processor, a data relocating circuit for receiving a logical address from the processor, mapping the received logical address to a physical address to locate a valid page in a predetermined bank, and generating a bank power control signal according to whether or not a corresponding memory bank includes valid pages, and a memory including a plurality of memory banks addressed by a physical address outputted from the data relocating circuit and a plurality of switching means for selectively supplying a power voltage to each of memory banks in response to the bank power control signal.

Abstract: A virtualization technique, in accordance with one embodiment of the present invention, includes emulating the small computing system interface (SCSI) protocol to access a virtual SCSI storage device backed by a file stored on network attached storage (NAS).

Abstract: In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

Abstract: A command receiver receives, from an external access requesting entity, a command with which to access data, together with an address to be accessed and IOID to identify the access requesting entity. Based on the IOID, the access decision unit determines whether or not an access is one that is to be permitted for an access requesting entity to access a region of access destination. The access decision unit determines whether access of the access requesting entity is permitted or not, for each page that serves as the basic management unit of logical address in the processor space.

Abstract: Provided are a method for Ternary Contents Address Memory (TCAM) table management and a computer-readable recording medium for recording a program that implements the method. The method includes the steps of: a) dividing a memory area of TCAM into fixed-size blocks depending on priority to configure a lookup table; b) assigning a priority to each routing entry being inputted to the lookup table based on prefix length; c) storing the routing entry having been assigned with the priority in a lookup table block of a corresponding priority; and d) when a modification occurs in the lookup table, modifying the lookup table to maintain an arranged state for a longest prefix match.

Abstract: A “LUN Table” enables Logical Unit Number (LUN) mapping/masking within an IOV adapter included in a Serial Attached Small Computer System Interface (“SAS” or “Serial Attached SCSI”). A plurality of System Images (“SI”) share block storage through the SAS. The IOV adapter includes one or more Virtual Functions (VF), a Physical Function (PF), and a LUN Table within the PF. The VF allows each SI to communicate I/0 requests with a storage device through the PF. The LUN Table maps the I/0 requests to unique locations within the storage device. Each SI is isolated from all other SIs. Interference between each SI is avoided. A VIOS or a LUN mapping/masking SAN are not required. I/0 latency, processor overhead and storage cost are improved over prior LUN mapping/masking solutions.

Abstract: An allocation control apparatus may access an address table storing addresses of slice areas allocated in a storage area for an entire storage system having a plurality of storage devices and addresses that do not correspond to allocated slice areas. The allocation control apparatus includes a reception unit receiving a request for allocating an arbitrary storage capacity an allocation unit allocating, by referring to the address table, an address that does not correspond to the allocated slice area for at least a part of the requested storage capacity and allocates an address for the slice area to the remaining storage capacity when the reception unit receives the allocation request, and a transmission unit transmitting the result allocated by the allocation unit to a requesting source of the allocation request.

Abstract: A method of selecting a data item from a memory within a first device, the method comprising the steps of evaluating within the first device a function of an input argument so as to form an output value, using the output value to select a data item from the memory and transmitting the selected data item to a second device.

Abstract: Dynamic pointer analysis techniques are able to produce faster pointer dependency test code and analyze more complex code in high-level languages such as in the programming languages C and C++ (not excluding other languages), as compared to known techniques.

Abstract: A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS medium based on a determination of the correlation of the LBA data to host file data. The memory system includes non-volatile memory using the DFS format, an interface for receiving LBA format data, and a controller configured to communicate with the host via an LBA interface and generate file objects from the LBA format data correlated to the host application files usable by the memory system.

Abstract: The invention relates to a method for accessing matrix elements, wherein accesses to two matrix elements that are adjacent in a row or in a column of a matrix and that are each specified by a respective relative address (ar, ac) are performed for the first of said elements in a first memory block (Bp1) using a first local address (a?1) and for the second of said elements in a different second memory block (Bp2) using a second local address (a?2)

Abstract: A cache receives a request from an instruction execution unit, searches for necessary data, outputs the data to the instruction execution unit if there is a cache hit, and instructs a request storage unit to request a move-in of the data if a cache miss occurs. The request storage unit stores therein the request corresponding to the instruction of the cache while the requested process is being executed. A REQID assignment unit reads the request stored in the request storage unit, selects an unused REQID from a REQID table, and assigns the unused REQID to the read request. The REQID is an identification number of the request based on the number of requests set as the maximum number that can be received at a simultaneous time by a system controller of the response side.

Abstract: A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.

Abstract: System and method for accessing and displaying personal information along with advertisement, software applications, or the like. The system and method include: retrieving from a memory device a unique identifier and a pointer; retrieving a redirect pointer from a pointer table responsive to the retrieved unique identifier and pointer; executing the retrieved redirect pointer to launch a software application to display a first content; displaying a second content and/or an advertisement with the first content.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collision of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.