Using Access Table, E.g., Matrix Or List, Etc. (epo) Patents (Class 711/E12.096)
  • Patent number: 11949595
    Abstract: An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Yonatan Meir Levitt, Gaspar Mora Porta
  • Patent number: 8918610
    Abstract: A chip including a processor for performing a predetermined operation, a provider for providing a clock signal, with which the processor is clocked, a counter for decrementing or incrementing a count based on the clock signal, a monitor for signaling the predetermined operation to be prevented, depending on the count, and a non-volatile storage for non-volatily storing the count.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventor: Peter Laackmann
  • Patent number: 8904123
    Abstract: A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device in which selected data of the first plurality of clusters of the first storage server are stored. A copy services command is received to copy the selected data from the first storage server to a second storage server having a second plurality of clusters. The virtual logical unit that stores the learning metadata is copied, from the first storage server to the second storage server, via the copy services command. Selected logical units corresponding to the selected data are copied from the first storage server to the second storage server, and the learning metadata is used to place the selected data in the type of storage device indicated by the learning metadata.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joshua J. Crawford, Benjamin J. Donie, Andreas B. Koster
  • Patent number: 8880848
    Abstract: A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuyuki Ninomiya
  • Patent number: 8762665
    Abstract: A switch connectable between hosts and storage device, the switch for providing a service of allotting virtual areas to be deployed in the storage device to any of the hosts upon demand, the switch includes: a processor for controlling allotment of virtual areas to the hosts and allocation of physical areas of the storage device to the virtual areas; and a memory for storing information of the host allowed access to the virtual areas, the processor controlling access by any of the hosts to the virtual area so as to restrict access by any of the hosts to a part of the virtual areas allotted to the any of the hosts in reference to the memory.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: June 24, 2014
    Assignee: Fujitsu Limited
    Inventors: Akira Satou, Kenichi Fujita, Koutarou Sasage, Atsushi Masaki, Hiroshi Shiomi, Masakazu Sakamoto, Takuya Kurihara, Toshiaki Takeuchi, Atsushi Shinohara
  • Patent number: 8706980
    Abstract: A dispersed storage system includes a plurality of storage units that each include a partial rebuild grid module. The partial rebuild grid module includes partial rebuilding functionality to reconstruct one of a plurality of encoded data slices wherein the plurality of encoded data slices are generated from a data segment based on an error encoding dispersal function. In the partial rebuilding process, a data slice is rebuilt by combining in any order slice partials generated from at least a threshold number T of the plurality of data slices.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: April 22, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Greg Dhuse, Andrew Baptist, Zachary J. Mark, Jason K. Resch, Ilya Volvovski
  • Patent number: 8706997
    Abstract: A storage device for storing data includes a device configured to store data read or written by a host, a command storage unit configured to store commands transmitted by the host to acquire information relating to the device, a command acquisition unit configured to acquire commands issued to the device when the host requests access to the data stored in the device, and an access determination unit configured to permit the access, if the commands acquired by the command acquisition unit have been stored in the command storage unit.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Limited
    Inventor: Atsushi Katano
  • Patent number: 8639895
    Abstract: A memory protection unit (MPU) is configured to store a plurality of region descriptor entries, each region descriptor entry defining an address region of a memory, an attribute corresponding to the region, and an attribute override control corresponding to the attribute. A memory access request to a memory address is received and determined to be within a first address region defined by a first region descriptor entry and within a second address region defined by a second region descriptor entry. When the attribute override control of the first region descriptor entry indicates that override is to be performed, the value of the attribute of the first region descriptor entry is applied for the memory access. When the attribute override control of the second region descriptor entry indicates that override is to be performed, the value of the attribute of the second region descriptor entry is applied for the memory access.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: January 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William C. Moyer
  • Patent number: 8589659
    Abstract: A method for writing data to a storage pool. The method includes receiving a virtual identifier (ID) and an offset for an object, extracting a node identifier (ID) that identifies a first storage server in the storage pool from the virtual ID, obtaining an object layout (OL) for the object from the first storage server, hashing an object ID and an offset ID to obtain a hashed value, where the virtual ID comprises the object ID and where the offset ID is generated from the offset, identifying a second storage server in the storage pool using a global namespace layout (GL), the OL, and the hashed value, and issuing a write request to write data to the object in the second storage server, where the write request comprises the object ID and the offset.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: November 19, 2013
    Assignee: DSSD, Inc.
    Inventor: Michael W. Shapiro
  • Patent number: 8539175
    Abstract: A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device in which selected data of the first plurality of clusters of the first storage server are stored. A copy services command is received to copy the selected data from the first storage server to a second storage server having a second plurality of clusters. The virtual logical unit that stores the learning metadata is copied, from the first storage server to the second storage server, via the copy services command. Selected logical units corresponding to the selected data are copied from the first storage server to the second storage server, and the learning metadata is used to place the selected data in the type of storage device indicated by the learning metadata.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Joshua James Crawford, Benjamin Jay Donie, Andreas Bernadrus Mattias Koster
  • Patent number: 8495313
    Abstract: A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device in which selected data of the first plurality of clusters of the first storage server are stored. A copy services command is received to copy the selected data from the first storage server to a second storage server having a second plurality of clusters. The virtual logical unit that stores the learning metadata is copied, from the first storage server to the second storage server, via the copy services command. Selected logical units corresponding to the selected data are copied from the first storage server to the second storage server, and the learning metadata is used to place the selected data in the type of storage device indicated by the learning metadata.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Joshua James Crawford, Benjamin Jay Donie, Andreas Bernardus Mattius Koster
  • Patent number: 8407450
    Abstract: An electronic device receives satellite signals from positioning information satellites and acquires positioning information and time information. A stored data table comprises a first block of data having a first array of time difference data and a second block of data having a second array of time difference data that is different than the first array of time difference data. A stored memory address table stores the memory address of each of the first and second blocks of data, at least one the blocks of data being stored a plurality of times in the memory address table. The data block corresponding to the acquired positioning information is identified, the memory address corresponding to that data block is read, the data block data indicated by the memory address is acquired, and the time difference data for the segment corresponding to the positioning information is acquired from the data block.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: March 26, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Oh Jaekwan
  • Patent number: 8402247
    Abstract: Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 19, 2013
    Assignee: NetApp, Inc.
    Inventors: Garth R. Goodson, Rahul N. Iyer
  • Patent number: 8332603
    Abstract: A computer system and method which stores path definition information including a storage ID, a volume ID, and validities of paths between a host computer and a first or second storage system identified by the storage ID for accessing a volume identified by the volume ID in one of the storage systems, sends an I/O request via the paths, based on the path definition information, receives information indicating the storage and volume IDs, and updates the path definition information. During initial copying from the second to the first volume, validity corresponding to a first path is set to “Invalid” and validity corresponding to a second path is set to “Valid”. After completion of initial copying, the validity corresponding to the first path included in the path definition information is changed to “Valid.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 11, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Nobuhiro Maki, Kenichi Oyamada, Kazuhiko Watanabe, Masaaki Hosouchi
  • Patent number: 8245002
    Abstract: Call stack protection, including executing at least one application program on the one or more computer processors, including initializing threads of execution, each thread having a call stack, each call stack characterized by a separate guard area defining a maximum extent of the call stack, dispatching one of the threads of the process, including loading a guard area specification for the dispatched thread's call stack guard area from thread context storage into address comparison registers of a processor; determining by use of address comparison logic in dependence upon a guard area specification for the dispatched thread whether each access of memory by the dispatched thread is a precluded access of memory in the dispatched thread's call stack's guard area; and effecting by the address comparison logic an address comparison interrupt for each access of memory that is a precluded access of memory in the dispatched thread's guard area.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E Attinella, Mark E Giampapa, Thomas M. Gooding
  • Publication number: 20120151168
    Abstract: Methods for providing shadow page tables that virtualize processor memory protection. In one embodiment, two shadow L2 page tables are maintained for each section, for example, each 1 MB section, of guest address space covered by a shadow L1 descriptor.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Applicant: VMWARE, INC.
    Inventors: Harvey TUCH, Prashanth P. BUNGALE, Scott W. DEVINE, Lawrence S. ROGEL
  • Patent number: 8156305
    Abstract: Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: April 10, 2012
    Assignee: NetApp, Inc.
    Inventors: Garth R. Goodson, Rahul N. Iyer
  • Publication number: 20110055474
    Abstract: A plurality of data slices are generated from a block of data to be stored in the dispersed storage system. A plurality of dispersed storage units are determined for storing the plurality of data slices, based on a geographical location associated with the plurality of dispersed storage units.
    Type: Application
    Filed: March 30, 2010
    Publication date: March 3, 2011
    Applicant: CLEVERSAFE, INC.
    Inventor: Jason K. Resch
  • Publication number: 20110010492
    Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.
    Type: Application
    Filed: September 17, 2010
    Publication date: January 13, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hitoshi Kurosawa
  • Patent number: 7774561
    Abstract: A method, system, and program key-controlled object-based memory protection are provided. A processing unit includes an authority check for controlling access by the processing unit to pages of memory according to whether a hardware protection key set currently loaded in an authority mask register allows access to the pages. In particular, each page of memory is assigned a page key number that indexes into the hardware protection key set. The currently loaded hardware protection key set specifies those page key numbers that are currently accessible to the processing unit for the execution context. Each hardware key within the hardware protection key set may be associated with a particular data object or group of data objects. Thus, effectively, the currently loaded hardware protection key set identifies which data objects or groups of data objects are currently accessible.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: Thomas S. Mathews, Bruce Mealey, Pratap Chandra Pattnaik, Ravi A. Shankar
  • Publication number: 20100153672
    Abstract: A method of controlling data access to non-volatile memory is disclosed. The method includes storing a data file in a non-volatile memory. The non-volatile memory includes a memory array including a plurality of address ranges one or more of which corresponding to a protected portion of the memory array and one or more of which corresponding to an unprotected portion of the memory array. The method also includes communicating to a host device an indication that a memory request with respect to the protected portion of the memory array is denied. The indication is communicated for instructing the host device to avoid a timeout when the memory request is denied.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 17, 2010
    Applicant: SANDISK CORPORATION
    Inventors: FABRICE JOGAND-COULOMB, ROBERT CHANG, PO YUAN, MEI YAN, XIAN JUN LIU
  • Patent number: 7664924
    Abstract: A system and method to securing a computer system from software viruses and other malicious code by intercepting attempts by the malicious code to write data to a storage medium. The invention intercepts the write access requests made by programs and verifies that the program is authorized to write before letting the write proceed. Authorization is determined by using the identity of the program as a query element into a database where permission values are stored. Depending on the presence or value of the permission value, write access is permitted or denied. Permission values can be set by the user, downloaded from a central server, or loaded into the central server by a group of users in order to collectively determine a permission value. The interception code can operate in kernel mode.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: February 16, 2010
    Assignee: Drive Sentry, Inc.
    Inventor: John Safa
  • Publication number: 20090300710
    Abstract: The invention provides a USB storage device and an access control method thereof. An access control module is provided on the USB storage device. The storage space is divided into at least one data storage entity. Each user's access right to each data storage entity is set and stored in the USB storage device as an access control list. The process between the USB storage device's being connected with a USB host and its being disconnected from the USB host is one session. When a session is established, the user provides authentication information for the USB device to authenticate him/her, and saves the user information used in the current session. In the current session, when the host of the user issues an access request for the data storage entity on the USB storage device, the access control module queries the access right list based on the user information in the current session to determine whether the user has an access right to the requested data storage entity.
    Type: Application
    Filed: January 31, 2007
    Publication date: December 3, 2009
    Inventors: Haixin Chai, Sheng Lu
  • Patent number: 7624242
    Abstract: An embodiment of the present invention is a technique to protect memory. A memory identifiers storage stores memory identifiers associated with protected components. The memory identifiers include exclusive memory identifiers and shared memory identifiers. The memory identifier storage is protected from access by a host operating system. A memory identifier management service (MMS) manages the memory identifiers. The MMS resides in a protected environment. An access control enforcer (ACE) enforces an access control policy with the memory identifiers.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: November 24, 2009
    Assignee: Intel Corporation
    Inventors: Uday Savagaonkar, Ravi Sahita, Hormuzd Khosravi, Priya Rajagopal
  • Patent number: 7543126
    Abstract: The apparatus, system and method implement subcontexts which associate groups of memory blocks. The apparatus, system and method maintain a permissions mapping for inter-subcontext memory accesses. A control module monitors all inter-subcontext memory accesses and prevents those accesses for which a permissions mapping does not exist.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: June 2, 2009
    Assignee: International Business Machines Corporation
    Inventor: Russell Lee Lewis