Abstract: Provided is a latency processing unit. The latency processing unit may include a plurality of multiplier-accumulator (MAC) trees configured to perform a matrix product operation for at least one of a plurality of partitions that implement an artificial intelligence (AI) model, streamlined memory access configured to connect each of the plurality of MAC trees to high bandwidth memory in which the at least one partition has been stored through a plurality of channels, a vector execution engine configured to perform an additional operation on results of the operation of the plurality of MAC trees, a local memory unit configured to store the results of the operation of the vector execution engine and an activation value, and an instruction scheduling unit configured to schedule the operations of the plurality of MAC trees and the vector execution engine.

Abstract: Systems, apparatuses and methods may provide for technology that automatically determines a runtime performance of a plurality of heterogeneous processing units based on system-level thread characteristics, wherein the runtime performance is determined on a per performance class basis. The technology may also automatically determine a runtime energy efficiency of the heterogeneous processing units, wherein the runtime energy efficiency is determined on a per efficiency class basis. In one example, technology selectively unparks one or more of the heterogeneous processing units based on the runtime performance and the runtime energy efficiency.

Abstract: The computing efficiency of an electronic computing device is improved. HPCs 20 to 23 include arithmetic processing units HA0 to HA3, respectively. Each of the arithmetic processing units HA0 to HA3 executes arithmetic processing in parallel. LPCs 30 to 33 includes management processing units LB0 to LB3, respectively. Each of the management processing units LB0 to LB3 manages execution of specific processing by an accelerator 6 when each of the arithmetic processing units HA0 to HA3 causes the accelerator 6 to execute the specific processing, and performs a series of commands for causing the accelerator 6 to execute the specific processing on a DMA controller 5 and the accelerator 6.

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address, and execution circuitry to execute the decoded instruction to store configuration information about usage of storage for two-dimensional data structures at the memory address.

Abstract: In one aspect, a data accumulation apparatus includes a script execution environment, an accumulation and retrieval unit accumulating data and performing retrieval on the accumulated data, a notification unit outputting notification in response to that data newly accumulated in the accumulation and retrieval unit matches one of conditions registered in advance, and a storage unit storing scripts and action correspondence information. The script execution environment has property of being capable of describing an instruction to perform data retrieval and an instruction to perform communication through the network, according to a script being executed.

Abstract: An electronic control device includes: a logic circuit for reconfiguring a plurality of arithmetic circuits including a first circuit and a second circuit; a reconfiguration controller that reconfigures the arithmetic circuits and checks the reconfigured arithmetic circuits based on reconfiguration commands; and a process controller that transmits the reconfiguration commands to the reconfiguration controller and instructs the arithmetic unit to execute operations, in which when a first reconfiguration command is received, the reconfiguration controller reconfigures and checks the first circuit, when the check of the first circuit by the reconfiguration controller is completed, the process controller instructs the first circuit to execute an operation, the process controller transmits a second reconfiguration command to the reconfiguration controller and instructs the reconfiguration controller to start to reconfigure the second circuit until the execution of a predetermined process of the first circuit is co

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: The described technology relates to a publish-subscribe message framework in which an application, decomposed to a plurality of processing stages, is run by executing respective processing stages of the application asynchronously and simultaneously with each other. Communications between the respective processing stages may exclusively be in accordance with the publish-subscribe execution model. The described publish-subscribe framework provides for processing stages to be executed in a multi-process and/or multi-threaded manner while also enabling the distribution of the processing stages to respective processing resources in a multi-processor/multi-core processing environment. An example electronic exchange application and a corresponding example exchange gateway application are described.

Abstract: A processing device in a memory system receives a request to execute a first operation of a first input/output (I/O) operation type at a memory device. The processing device further determines whether a second operation of a second I/O operation type is being executed at the memory device. Responsive to determining that the second operation is being executed, the processing device suspends the second operation after a delay time period, the delay time period corresponds to a first operation weight of the first operation and a second operation weight of the second operation, executes the first operation at the memory device, and responsive to determining that executing the first operation is complete, the processing device resumes execution of the second operation at the memory device.

Abstract: The processor chip can have a pre-execution pipeline sharing a plurality of resources including at least one resource of interest, a resource tracker having more than one credit unit associated with each one of said at least one resource of interest. The method can include: decoding the instruction data to determine a resource requirement including a quantity of virtual credits required from the credit units for the at least one resource of interest, checking the resource tracker for an availability of said quantity of virtual credits and, if the availability of the amount of said virtual credits is established, i) dispatching the instruction data, and ii) subtracting the quantity of said credits from the resource tracker.

Abstract: Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least one local memory unit that allows for data reuse opportunities. The first custom computing apparatus optimizes the code for reduced communication execution on the second computing apparatus.

Abstract: Systems and techniques are provided for hardware architecture used in parallel computing applications to improve computation efficiency. An integrated circuit system may include a data store that stores data for processing and a reconfigurable systolic array that may process the data. The reconfigurable systolic array may include a first row of processing elements (PE) that process the data according to a first function and a second row of PE that process the data according to a second function. The reconfigurable systolic array may also include a routing block coupled to the first row of PE, the second row of PE, and the data store. Further, the reconfigurable systolic array may receive data from the first row of PE, transmit the data received from the first row of PE to the second row of PE, and transmit data output by the second row of PE to the first row of PE.

Abstract: A semiconductor device capable of retaining data for a long period is provided. The semiconductor device includes a first memory cell and a second memory cell. The first memory cell includes a first transistor. The second memory cell includes a second transistor. The threshold voltage of the second transistor is higher than the threshold voltage of the first transistor. The first transistor includes a first metal oxide. The second transistor includes a second metal oxide. Each of the first metal oxide and the second metal oxide includes a channel formation region. Each of the first metal oxide and the second metal oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. The atomic ratio of the element M to In in the second metal oxide is greater than that in the first metal oxide.

Abstract: Representative apparatus, method, and system embodiments are disclosed for configurable computing. In a representative embodiment, a system includes an interconnection network, a processor, a host interface, and a configurable circuit cluster. The configurable circuit cluster may include a plurality of configurable circuits arranged in an array; an asynchronous packet network and a synchronous network coupled to each configurable circuit of the array; and a memory interface circuit and a dispatch interface circuit coupled to the asynchronous packet network and to the interconnection network. Each configurable circuit includes instruction or configuration memories for selection of a current data path configuration, a master synchronous network input, and a data path configuration for a next configurable circuit.

Abstract: Methods, apparatus, systems, and articles of manufacture to manage heat in a CPU are disclosed. An example apparatus includes a metric collection agent to output a metric representative of a property of the central processor unit including a first core and a second physical core, the first physical core and the second physical core mapped to first and second logical cores by a map. A policy processor is to evaluate the first metric to determine whether to change the map to remap at least one of the first and second logical cores relative to the second one of the first and the second physical cores to move a process between the first and second physical cores to adjust the property, the moving of the process between the physical cores being transparent to an application/OS layer. A mapping controller is responsive to the policy processor to change the map.

Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line; an internal control circuit capable of implementing a calculation operation including the simultaneous activation in read mode of at least two rows of the array; and a shuffle circuit including a data input register, a configuration register, and an output port, the shuffle circuit being capable of delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to the state of its configuration register.

Abstract: Distinct system registers for logical processors are disclosed. In one example of the disclosed technology, a processor includes a plurality of block-based physical processor cores for executing a program comprising a plurality of instruction blocks. The processor also includes a thread scheduler configured to schedule a thread of the program for execution, the thread using the one or more instruction blocks. The processor further includes at least one system register. The at least one system register stores data indicating a number and placement of the plurality of physical processor cores to form a logical processor. The logical processor executes the scheduled thread. The logical processor is configured to execute the thread in a continuous instruction window.

Abstract: Various techniques are disclosed for offloading the processing of data packets that contain financial market data. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize financial market data in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

Abstract: There are provided a system, a method and a computer program product for selecting an active data stream (a lane) while running Single Program Multiple Data code on a Single Instruction Multiple Data machine. The machine runs an instruction stream over input data streams and machine increments lane depth counters of all active lanes upon the thread-PC reaching a branch operation and updates the lane-PC of each active lane according to targets of the branch operation. An instruction of the instruction stream includes a barrier indicating a convergence point for all lanes to join. In response to a lane reaching a barrier: evaluating whether all lane-PCs are set to a same thread-PC; and if the lane-PCs are not set to the same thread-PC, selecting an active lane from the plurality of lanes; otherwise, incrementing the lane-PCs of all the lanes, and then selecting an active lane from the plurality of lanes.

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

Abstract: An apparatus and method for collecting and using profile data during graphics processing. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics commands responsive to execution of an application; and profile storage to store graphics execution profile data associated with one or more graphics workloads; and a profile manager to read the profile data upon detecting one of the graphics workloads during execution of the application and to configure the graphics processor in accordance with the profile data.

Abstract: A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to monitor each of loads of processor cores performing processes for which a parallel operation is inhibited. The processor cores are included in the information processing apparatus. The processor is configured to identify a first process that is being performed by a first processor core having a load that equals or exceeds a predetermined threshold value of a first load from among the processor cores based on a correspondence relationship between the processes and the first processor core.

Abstract: Embodiments include load-balancing a plurality of simultaneous threads of a processor. An example method includes computing a minimum group count for a thread from the plurality of threads. The minimum group count indicates a minimum number of groups of instructions to be assigned to the thread. The method further includes computing a maximum allowed group count for the thread. The maximum allowed group count indicates a maximum number of groups of instructions to be assigned to the thread. The method further includes issuing one or more groups of instructions for execution by the thread based on the minimum group count and the maximum allowed group count for the thread.

Abstract: An apparatus for selecting an efficient processor includes a comparison module that compares performance characteristics of a plurality of processors available for execution of a function, where each performance characteristic varies as a function of function size. The apparatus includes a selection module that selects, based on a size of the function, a processor from the plurality of processors with a best performance for execution of the function, and an execution module that executes the function on the selected processor.

Abstract: An electronic device includes a combinational logic circuit, one or more state-sampling components, and protection circuitry. The combinational logic circuit has one or more inputs and one or more outputs. The state-sampling components are configured to sample the outputs of the combinational logic circuit at successive clock cycles. The protection circuitry is configured to protect the combinational logic circuit by, per clock cycle, starting to apply random data to the inputs of the combinational logic circuit a given time duration before a sampling time of the state-sampling components for that clock cycle, and, after applying the random data, switching to apply functional data to the inputs of the combinational logic circuit, to be sampled by the state-sampling components. A propagation delay, over any signal path via the combinational logic circuit, is no less than the given time duration.

Abstract: Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

Abstract: An order management device and method of implementing that device in an integrated circuit. The order management device including a memory having a first and second data structure. The first data structure stores orders associated with a set of P limits. The second data structure includes the limits in a list of N limits that are not contained in the subset P, the entries in the second data structure being allocated dynamically. A first management core processes input commands related to an order, updates the first data structure and generates at least one update command to be sent to a second management core. The second management core updates the second data structure in response to the update. The first management core processes input commands independently of the update command processing by the second processing core.

Abstract: Examples herein describe a self-test process where an integrated circuit includes a test controller responsible for testing a plurality of frames in the memory of an integrated circuit. The test controller can receive a test pattern which the controller duplicates and stores in each of the plurality of frames. However, frames may be non-uniform meaning the frames have varying sizes. As such, some of the frames may only store parts of the test pattern rather than all of it. In any case, the test controller reads out the stored data and generates a checksum which can then be compared to a baseline checksum generated from simulating the integrated circuit using design code to determine whether there is a manufacturing defect in the frames.

Abstract: A storage system includes a management processor and main processors. Each of the main processors is configured to alternately switch between a period in which main function processing, including I/O processing in response to an I/O request from a host, is executed and a period in which a management instruction is executed. The management processor is configured to: manage information associating each of uncompleted management instructions, which are already transmitted to the main processors, with a transmission destination main processor to which the each of the uncompleted management instructions is transmitted; select, based on the uncompleted management instructions of the main processors, a transmission destination main processor to which a next management instruction is to be transmitted, from among the main processors; and transmit the next management instruction to the selected transmission destination main processor.

Abstract: A mechanism is described for facilitating dynamic merging of atomic operations in computing devices. A method of embodiments, as described herein, includes facilitating detecting atomic messages and a plurality of slot addresses. The method further includes comparing one or more slot addresses of the plurality of slot addresses with other slot addresses of the plurality of slot addresses to seek one or more matched slot addresses, where the one or more matched slot addresses are merged into one or more merged groups. The method may further include generating one or more merged atomic operations based on and corresponding to the one or more merged groups.

Abstract: The present invention facilitates efficient and effective utilization of storage management features. In one embodiment, a system comprises: a storage component, a memory controller, and a communication link. The storage component stores information. The memory controller controls the storage component. The communication link communicatively couples the storage component and the memory controller. In one embodiment, the communication link communicates storage system management information between the memory storage component and memory controller, and communication of the storage system management information does not interfere with command/address information communication and data information communication.

Abstract: Systems and methods for implementing an integrated circuit with core-level predication includes: a plurality of processing cores of an integrated circuit, wherein each of the plurality of cores includes: a predicate stack defined by a plurality of single-bit registers that operate together based on one or more of logical connections and physical connections of the plurality of single-bit registers, wherein: the predicate stack of each of the plurality of processing cores includes a top of stack single-bit register of the plurality of single-bit registers having a bit entry value that controls whether select instructions to the given processing core of the plurality of processing cores is executed.

Abstract: A method of activating scheduling instructions within a parallel processing unit is described. The method includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.

Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.

Abstract: Methods and systems are disclosed for optical network link traversal, including a method comprising the steps of receiving, by a traverser software module for an optical network, from a first node in a network link defining a path in the optical network, one or more node sets indicative of one or more of a second node also in the network link; determining, with the traverser software module, an order of traversal of the one or more node sets; traversing the network link using the determined order of traversal; communicating, by the traverser software module, information with a feature manager software module for a first software feature, the first software feature configured to perform a function specific to a specific node; and triggering, by the feature manager software module, the first software feature to execute one or more computer executable instruction based on information from the traverser software module.

Abstract: Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

Abstract: Systems and methods to automatically or manually generate various multi-stage pyramid network based fabrics, either partially connected or fully connected, are disclosed by changing different parameters of multi-stage pyramid network including such as number of slices, number of rings, number of stages, number of switches, number of multiplexers, the size of the multiplexers in any switch, connections between stages of rings either between the same numbered stages (same level stages) or different numbered stages, single or multi-drop hop wires, hop wires of different hop lengths, hop wires outgoing to different directions, hop wires incoming from different directions, number of hop wires based on the number and type of inlet and outlet links of large scale sub-integrated circuit blocks. One or more parameters are changed in each iteration so that optimized fabrics are generated, at the end of iterations, to route a given set of benchmarks or designs having a specific connection requirements.

Abstract: A memory correcting method includes steps: providing a memory with a plurality of memory bytes; respectively adding a plurality of correcting bytes to the plurality of memory bytes; providing a plurality of non-volatile compared memory bytes; detecting whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory bytes of the memory to complete the correction. Alternatively, the method respectively provides a plurality of compared memory address bytes for the plurality of memory bytes and for the plurality of correcting bytes for labeling underperforming-bit addresses. Then, the method detects whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory address bytes of the memory to complete the correction.

Abstract: In certain embodiments, a device for outputting updated messages a determinate number of times is provided. The device may comprise an output, an input, one or more processors, a memory, code stored in the memory and executed by the processor, wherein at least one message is received from time to time by the device through the input, and wherein the code selects if and when the at least one message is to be provided on the device via the output a determinate number of times. The operation of the enabled device can allow the message to be delivered to the user as the result of some action in regards to enabled device usage.

Abstract: Matching processing between pieces of vector data is accelerated. A matching device 100 performs, for a plurality of pieces of vector data each having a plurality of dimensions, a predetermined operation pertaining to each dimension of each piece of vector data. The matching device 100 includes a collective operation unit 150 and an individual operation unit 160. The collective operation unit 150 performs the predetermined operation pertaining to a specific dimension among the plurality of dimensions by a vector operation for different pieces of vector data in the plurality of pieces of vector data. The individual operation unit 160 performs the predetermined operation pertaining to each dimension other than the specific dimension for a piece of vector data that satisfies a predetermined condition among the plurality of pieces of vector data.

Abstract: A hybrid gaming system comprised of a terminal including an entertainment software controller coupled to a subscriber interface provider operator control access, wherein the entertainment software controller receives credit and provides an entertainment game; a real world controller provides a gambling game; and the subscriber interface which receives coupling requests; determines that the request is approved; and allows an operator to couple the game world controller to the entertainment software controller, when the a subscriber interface that the request is approved.

Abstract: In particular embodiments, a data subject request processing system may be configured to utilize one or more local storage nodes in order to process a data subject access request on behalf of a data subject. In particular embodiments, the one or more local storage nodes may be local to the data subject making the request (e.g., in the same country as the data subject, in the same jurisdiction, in the same geographic area, etc.). The system may, for example, be configured to: (1) receive a data subject access request from a data subject (e.g., via a web form); (2) identify a suitable local storage node based at least in part on the request and/or the data subject; (3) route the data subject access request to the identified local storage node; and (4) process the data subject access request at the identified local storage node.

Abstract: Embodiments include a system, method, and computer program product for distributed intelligent pattern recognition. Embodiments include a cooperative multi-agent detection system that enables an array of disjunctive devices (e.g., cameras, sensors) to selectively cooperate to identify objects of interest over time and space, and to contribute an object of interest to a shared deep learning pattern recognition system based on a bidirectional feedback mechanism. Embodiments provide updated information and/or algorithms to one or more agencies for local system learning and pattern updating recognition models. Each of the multiple agencies may in turn, update devices (e.g., cameras, sensors) coupled to the local machine learning and pattern recognition models.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for restructuring an image processing pipeline. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; or splitting the directed acyclic graph into smaller graphs.

Abstract: A method is described. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes any of: recognizing there are a different number of kernels in the program code than stencil processors in the image processor; recognizing that at least one of the kernels is more computationally intensive than another one of the kernels; and, recognizing that the program code has resource requirements that exceed the image processor's memory capacity.

Abstract: There are provided a system, a method and a computer program product for selecting an active data stream (a lane) while running SPMD (Single Program Multiple Data) code on SIMD (Single Instruction Multiple Data) machine. The machine runs an instruction stream over input data streams. The machine increments lane depth counters of all active lanes upon the thread-PC reaching a branch operation. The machine updates the lane-PC of each active lane according to targets of the branch operation. The machine selects an active lane and activates only lanes whose lane-PCs match the thread-PC. The machine decrements the lane depth counters of the selected active lanes and updates the lane-PC of each active lane upon the instruction stream reaching a first instruction. The machine assigns the lane-PC of a lane with a largest lane depth counter value to the thread-PC and activates all lanes whose lane-PCs match the thread-PC.

Abstract: Techniques involving a compute engine architecture to support data-parallel loops with reduction operations are described. In some embodiments, a hardware processor includes a memory unit and a plurality of processing elements (PEs). Each of the PEs is directly coupled via one or more neighbor-to-neighbor links with one or more neighboring PEs so that each PE can receive a value from a neighboring PE, provide a value to a neighboring PE, or both receive a value from one neighboring PE and also provide a value to another neighboring PE. The hardware processor also includes a control engine coupled with the plurality of PEs that is to cause the plurality of PEs to collectively perform a task to generate one or more output values by each performing one or more iterations of a same subtask of the task.

Abstract: A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.