Processing Architecture Patents (Class 712/1)
  • Patent number: 11294815
    Abstract: A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: April 5, 2022
    Assignee: Mobileye Vision Technologies Ltd.
    Inventors: Yosef Kreinin, Yosi Arbeli, Gil Israel Dogon
  • Patent number: 11269799
    Abstract: A cluster of processing elements has a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking an outcome of a primary processing workload performed by a corresponding primary processing element. A shared cache is provided, having a predetermined cache capacity accessible to each of the processing elements when in the split mode. In the lock mode, the predetermined cache capacity of the shared cache is fully accessible to the at least one primary processing element.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 8, 2022
    Assignee: Arm Limited
    Inventors: R Frank O'Bleness, Erez Amit
  • Patent number: 11221953
    Abstract: A memory device includes a memory cell array, an information register and a prefetch circuit. The memory cell array stores a valid data array, a base array and a target data array, where the valid data array includes valid elements among elements of first data, the base array includes position elements indicating position values corresponding to the valid elements and the target data array includes target elements of second data corresponding to the position values. The information register stores indirect memory access information including a start address of the target data array and a unit size of the target elements. The prefetch circuit prefetches, based on the indirect memory access information, the target elements corresponding to the position elements that are read from the memory cell array.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: January 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-Soon Jo, Young-Geun Choi, Seung-Yeun Jeong
  • Patent number: 11215665
    Abstract: The present disclosure provides a multi-core processor. The multi-core processor comprises a plurality of cores and a debug circuit, the debug circuit comprising debug circuits in the same number as that of the cores, transmission controllers in the same number as that of the cores, and a master control circuit, each of the debug circuits being connected to one core and one transmission controller, respectively, and all transmission controllers being connected to the master control circuit. Each of the debug circuits is configured to generate a debug event signal and respond to the generated debug event signal or received debug event signals generated by other debug circuits. Each of the transmission controllers is configured to respectively control transmission of the debug event signal between the respectively connected debug circuit and the master control circuit. The master control circuit is configured to forward debug event signals among different transmission controllers.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: January 4, 2022
    Assignee: C-SKY Microsystems Co., Ltd.
    Inventors: Taotao Zhu, Yubo Guo
  • Patent number: 11194615
    Abstract: A method performed by a physical computing system includes, with a hypervisor, determining a first time difference between when pause exiting was last enabled for the virtual machine and present time. The method further includes, with the hypervisor, in response to determining that the first time difference is greater than an enablement threshold, enabling pause exiting. The method further includes, with the hypervisor, with pause loop exiting enabled, determining a second time difference between when pause exiting was last disabled and the present time. The method further includes, with the hypervisor, disabling pause exiting in response to determining that the second time difference exceeds a disablement threshold.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 7, 2021
    Assignee: RED HAT, INC.
    Inventors: Andrea Arcangeli, Bandan Das
  • Patent number: 11137941
    Abstract: Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information received over the heterogeneous memory channel, that an error has occurred requiring a recovery sequence. In response to the error, the method initiates the recovery sequence including (i) transmitting selected memory access commands that are stored in the replay queue, and (ii) transmitting non-volatile reads that are stored in the NV queue.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 5, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jing Wang, James R. Magro, Kedarnath Balakrishnan
  • Patent number: 11084438
    Abstract: A power supply apparatus for vehicles includes a first power supply circuit that converts a voltage applied to a first conductive path and applies the resulting voltage to a second conductive path, and second power supply circuits that convert a voltage applied to the first conductive path and apply the resulting voltage to third conductive paths, and switch portions are provided respectively between the second conductive path and the third conductive paths. Control units switch switch portions off when at least one of the first power supply circuit and the second conductive path is not in the predetermined abnormal state, and switch the switch portions on in the predetermined abnormal state.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 10, 2021
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Takafumi Kawakami
  • Patent number: 11086637
    Abstract: An initial configuration query for an initial configuration query result is received from a service. The initial configuration query result comprises an executable configuration query engine that can be run by the service to serve one or more subsequent configuration query results to one or more subsequent configuration queries constrained by one or more immutable configuration constraints, wherein the initial configuration query comprises the one or more immutable configuration constraints. A subset of configuration data from a configuration database is selected based at least in part on the one or more immutable configuration constraints. The executable configuration query engine is generated, wherein the executable configuration query engine serves configuration data from the selected subset of configuration data.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 10, 2021
    Assignee: Akamai Technologies, Inc.
    Inventors: Mehrdad Reshadi, Madhukar Nagaraja Kedlaya
  • Patent number: 11063939
    Abstract: A method and an apparatus for secure interaction between terminals, where the method includes indicating or indirectly indicating, by a companion terminal with an embedded Universal Integrated Circuit Card (eUICC), a Hypertext Transfer Protocol (HTTP) over Secure Socket Layer (HTTPS) Uniform Resource Locator (URL) including security information to a primary terminal such that the primary terminal initiates establishment of a local Transport Layer Security (TLS) connection according to the HTTPS URL, receiving, by the companion terminal, an HTTP request from the primary terminal using the local TLS connection, completing establishment of an HTTPS session when the companion terminal determines that the HTTP request includes the security information, and receiving, by the companion terminal, an operation instruction for the eUICC from the primary terminal using the HTTPS session.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: July 13, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ziyao Cheng, Shuiping Long
  • Patent number: 11057307
    Abstract: Approaches, techniques, and mechanisms are disclosed for assigning paths to network packets. The path assignment techniques utilize path state information and/or other criteria to determine whether to route a packet along a primary candidate path selected for the packet, or one or more alternative candidate paths selected for the packet. According to an embodiment, network traffic is at least partially balanced by redistributing only a portion of the traffic that would have been assigned to a given primary path. Move-eligibility criteria are applied to traffic to determine whether a given packet is eligible for reassignment from a primary path to an alternative path. The move-eligibility criteria determine which portion of the network traffic to move and which portion to allow to proceed as normal. In an embodiment, the criteria and functions used to determine whether a packet is redistributable are adjusted over time based on path state information.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 6, 2021
    Assignee: Innovium, Inc.
    Inventors: William Brad Matthews, Puneet Agarwal, Meg Pei Lin, Rupa Budhia
  • Patent number: 11010330
    Abstract: An example method for adjusting operation of an integrated circuit includes testing a plurality of electronic elements of the integrated circuit including one or more redundant electronic elements designated as inactive according to a manufacturer's default configuration of the integrated circuit to determine one or more operating parameters of the integrated circuit. The method further includes selecting a subset of electronic elements from the plurality of electronic elements based on the one or more operating parameters, wherein the subset of electronic elements is designated as active according to an updated configuration of the integrated circuit, and controlling operation of the integrated circuit using the updated configuration instead of the manufacturer's default configuration.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: May 18, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: William Paul Hovis, Peter A. Atkinson, Robert James Ray, Garrett Douglas Blankenburg, Andres Felipe Hernandez
  • Patent number: 10956168
    Abstract: A computer data processing system includes an instruction pipeline having a front end and a back end, a decoding and dispatch unit to dispatch a current instruction; and a pipeline by-pass unit to invoke an out-of-order pipeline by-pass operation. The pipeline by-pass unit by-passes a section of the instruction pipeline such that the current instruction architecturally completes before initiating instruction execution. The computer data processing system further includes a post-completion execution unit that executes the current instruction after the current instruction architecturally completes.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Avery Francois, Christian Jacobi, Gregory William Alexander
  • Patent number: 10956163
    Abstract: A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin Pohlack, Luke Yen
  • Patent number: 10908901
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 2, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Joseph Zbiciak
  • Patent number: 10911401
    Abstract: A communication device may receive a target IP address from a target device by using a first communication scheme; after the target IP address which is a global IP address has been received from the target device, send a first signal including the target IP address as a destination IP address via the Internet by using a second communication scheme; determine whether a second signal is received via the Internet by using the second communication scheme in response to sending the first signal, the second signal including the target IP address as a source IP address; and in a case where it is determined that the second signal is received, execute a security process related to security of the target device.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: February 2, 2021
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Ryoya Tsuji
  • Patent number: 10852955
    Abstract: A storage system includes a communication fabric, a storage module, a client device having an object descriptor (OD) generator to generate object descriptors (ODs) to access data stored in storage devices of the storage module. The storage system further includes a first control module (CM) coupled to the client device and the storage module via the communication fabric to manage accesses of the storage module. The first CM is adapted to receive a request from client device to access a data object stored in the storage module, where the request includes an OD uniquely identifying the data object and created by the OD generator of the client device. In response, the first CM examines a first object descriptor table (ODT) associated with the first CM to determine whether the OD is valid, and if the OD is valid allows the storage module to service the request.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: December 1, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: David Powell
  • Patent number: 10817309
    Abstract: A method for runtime optimization of a configurable processing architecture are disclosed. The method comprises receiving a plurality of calls for running at least one function; identifying at least one pattern among the plurality of received calls; and based on the at least one pattern, manipulating at least a portion of the configurable processing architecture, to compute the least one function.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 27, 2020
    Assignee: Next Silicon Ltd
    Inventor: Elad Raz
  • Patent number: 10761986
    Abstract: A data processing system includes a host processor, a local memory coupled to the host processor, a plurality of remote memory media, and a scalable data fabric coupled to the host processor and to the plurality of remote memory media. The scalable data fabric includes a filter for storing information indicating a location of data that is stored by the data processing system. The host processor includes a hardware sequencer coupled to the filter for selectively moving data stored by the filter to the local memory.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 1, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Blagodurov, Timothy E. Landreth, Stanley Ames Lackey, Jr., Patrick Conway
  • Patent number: 10763349
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Jeanette M. Roberts, James S. Clarke, Zachary R. Yoscovits, David J. Michalak
  • Patent number: 10754782
    Abstract: Systems, methods, and apparatuses relating to circuitry to accelerate store processing are described. In one embodiment, a processor includes a (e.g.
    Type: Grant
    Filed: March 30, 2019
    Date of Patent: August 25, 2020
    Assignee: INTEL CORPORATION
    Inventors: Binh Pham, Chen Dan
  • Patent number: 10713213
    Abstract: Systems and methods for multi-architecture computing. Some computing devices may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Eliezer Tamir, Ben-Zion Friedman
  • Patent number: 10691453
    Abstract: A method is disclosed for loading a vector with a processor. The method includes obtaining, by the processor, a variable-length vector load instruction. The method also includes determining that the vector load instruction specifies a vector register for a target, a memory address, and a length, wherein the memory address and the length are each specified in at least a general purpose register. The method also includes determining whether data should be loaded into the vector register using big endian byte-ordering or little endian byte-ordering. The method further includes loading data from memory into the vector register, wherein if the length is less than a length of the vector register, setting one or more residue bytes in the vector register to a pad value, wherein the residue bytes are determined based on the determined byte-ordering.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Brett Olsson
  • Patent number: 10691455
    Abstract: A method and apparatus are provided. The method includes executing a plurality of threads in a temporal dimension, executing a plurality of threads in a spatial dimension, determining a branch target address for each of the plurality of threads in the temporal dimension and the plurality of threads in the spatial dimension, and comparing each of the branch target addresses to determine a minimum branch target address, wherein the minimum branch target address is a minimum value among branch target addresses of each of the plurality of threads.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Tejash M. Shah, Srinivasan S. Iyer, David C. Tannenbaum
  • Patent number: 10691456
    Abstract: A method is disclosed for storing vector data into memory with a processor. The method includes obtaining, by the processor, a variable-length vector store instruction. The method also includes determining that the vector store instruction specifies a vector register for a source, a memory address, and a length, where the memory address and the length are each specified in at least a general purpose register. The method also includes determining whether data should be stored into memory at the memory address using big endian byte-ordering or little endian byte-ordering. The method further includes storing data from the vector register into memory, where if the length is less than a length of the vector register, storing only the data from the vector register specified by the length.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Brett Olsson
  • Patent number: 10678599
    Abstract: A system and method for selecting a resource from among a plurality of resources. A total range of numbers is divided into a plurality of sub-ranges, each associated with a respective one of the resources. An indexing number, e.g., a random number, is generated and, when it falls within the total range of numbers, the resource associated with the sub-range into which the indexing number falls is selected. When the indexing number falls outside of the total range, a resource associated with the difference between the indexing number and the greatest number in the total range is selected.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: June 9, 2020
    Assignee: Rockley Photonics Limited
    Inventors: Bhaskar Chowdhuri, Chiang Yeh, Cyriel Johan Agnes Minkenberg, Guy Regev
  • Patent number: 10681066
    Abstract: A method and system for an online help network containing a server and a plurality of terminals are disclosed. The method includes registering users of the plurality of terminals, wherein the plurality of terminals form a peer-to-peer network over which the plurality of terminals communicate with one another without going through the server; determining a question from a user of one of the terminals and a target recipient as one of the server and the peer-to-peer network; receiving an answer to the question from the target recipient; obtaining a risk detection category from the user; obtaining one or more detection patterns associated with the risk detection category; based on the one or more detection patterns, detecting a cyber risk on the terminal of the user with the risk detection category; and prompting the user of the cyber risk detected on the terminal of the user.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: June 9, 2020
    Inventor: William Harrison Tan
  • Patent number: 10635831
    Abstract: Provides a method to control the Background Region of a Memory Protection Unit (MPU) in order to create isolated privileged tasks (ptasks), which are an important step in the process of converting ordinary tasks to unprivileged tasks (utasks) and which also offer improved security and reliability in privileged mode.
    Type: Grant
    Filed: January 6, 2018
    Date of Patent: April 28, 2020
    Inventor: Ralph Crittenden Moore
  • Patent number: 10560477
    Abstract: An information processing system that facilitates management of information security policy even for an extended application installed from exterior. A receiving unit receives security policy data in which a security policy is described. A management unit manages an extended application that can be added and deleted and that operates in an image processing apparatus. A notification unit notifies an administrator of error information about a security policy of an extended application managed by the management unit, when the extended application managed by the management unit does not comply with the security policy described in the security policy data, and when an identifier of an extended application that is extracted from the security policy data and that is excepted from applying the security policy does not match with the identifier of the extended application managed by the management unit.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: February 11, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Naoki Tsuchitoi, Akari Yasukawa, Shota Shimizu
  • Patent number: 10534650
    Abstract: According to one embodiment of the present disclosure, there is provided a processing method including obtaining parallelized unit information for video parallel processing; obtaining performance information that indicates performance of a plurality of cores; and allocating a plurality of video unit data to the plurality of cores based on the parallelized unit information and the performance information. The parallelized unit information includes complexity information that indicates complexity of the plurality of video unit data.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: January 14, 2020
    Assignee: GACHON UNIVERSITY OF INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventor: Eun-Seok Ryu
  • Patent number: 10521207
    Abstract: Systems, methods, and computer program products relating to compiling source code to reduce memory operations during execution. A compiler receives source code. The compiler identifies an indirect access array operation in the source code. The compiler generates replacement code for the indirect access array operation. The replacement code includes a mask array and a union data structure. The compiler generates modified code. The modified code modifies the source code to include the replacement code in place of the indirect access array operation.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventors: Archana Ravindar, Satish Kumar Sadasivam
  • Patent number: 10409599
    Abstract: A method including fetching a group of instructions, where the group of instructions is configured to execute atomically by a processor is provided. The method further includes decoding at least one of a first instruction or a second instruction, where: (1) decoding the first instruction results in a processing of information about a group of instructions, including information about a size of the group of instructions, and (2) decoding the second instruction results in a processing of at least one of: (a) a reference to a memory location having the information about the group of instructions, including information about the size of the group of instructions or (b) a processor status word having information about the group of instructions, including information about the size of the group of instructions.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: September 10, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jan Gray, Doug Burger, Aaron Smith
  • Patent number: 10390010
    Abstract: In some embodiments, distributed video reorder buffers of a video (e.g. HEVC, H.265) encoder/decoder each include a circular FIFO array of pointers to buffer allocation units, and control logic which assigns allocation units to incoming video data in an order that allocation units are released by outgoing video data. The assignment order allows increased buffer utilization and lower buffer sizes, which is of increased importance for relatively large (e.g. 64×64, 32×32) video blocks, as supported by HEVC encoding/decoding.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 20, 2019
    Assignee: oViCs
    Inventor: Sorin C. Cismas
  • Patent number: 10387358
    Abstract: A plurality of Peripheral Component Interconnect Express (PCIe) endpoints of a multi-socket network interface device are attached to a host for exchanging ingress traffic and egress traffic. An operating system of the host includes a bonding/teaming module having a plurality of network interfaces. The bonding/teaming module is configured to select one of the endpoints for the egress traffic. The network interface device has a hardware bond module configured to steer the ingress traffic to designated ones of the endpoints.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: August 20, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventor: Tzahi Oved
  • Patent number: 10372713
    Abstract: A system and method for extrapolating a set of specific representational identifiers that are represented or covered by a generic representational identifier found in a target document. Queries are constructed and performed on a corpus of source documents in which members of the extrapolated set of specific representational identifiers are compared to a database of representational data. By matching representational data in this way, any overlap between the generic representational data and specific instances of the generic representational identifier within the source documents is determined. In a more specific implementation, the system and method reduces the scope of the generic representational identifier such that the reduced scope generic representational identifier encompasses only novel specific representational identifiers.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: August 6, 2019
    Assignee: PURDUE PHARMA L.P.
    Inventors: Paul Blake, Kevin Brogle, Kevin Brown, Don Kyle
  • Patent number: 10342485
    Abstract: A removable base of a wearable medical monitor includes a mating surface configured to reversibly couple the removable base to a body of the wearable medical monitor. The removable base may also include certain functional features, such as a sensor configured to detect a physiological parameter of a patient and/or a memory configured to store data for identifying characteristics of the sensor or the patient.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 9, 2019
    Assignee: COVIDIEN LP
    Inventors: Andy S. Lin, Friso Schlottau, David B. Berlin, Paul Von Der Lippe, Kristine Michelle Cohrs, Mark Yu-Tsu Su
  • Patent number: 10333307
    Abstract: A computer-implemented method, system, and computer program product are provided for demand charge management. The method includes receiving an active power demand for a facility, a current load demand charge threshold (DCT) profile for the facility, and a plurality of previously observed load DCT profiles. The method also includes generating a forecast model from a data set of DCT values based on the current load DCT profile for the facility and the plurality of previously observed load DCT profiles. The method additionally includes forecasting a monthly DCT value for the facility using the forecast model. The method further includes preventing actual power used from a utility from exceeding the next month DCT value by discharging a battery storage system into a behind the meter power infrastructure for the facility.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 25, 2019
    Assignee: NEC Corporation
    Inventors: Ali Hooshmand, Ratnesh Sharma, Ramin Moslemi
  • Patent number: 10324908
    Abstract: Various examples are directed to exposing database artifacts. For example, a rules engine may receive schema data describing a database schema of an in-memory database. The schema data may describe a table, a view, and a procedure. The rules engine may generate a data model comprising a plurality of translation artifacts including a table translation artifact describing a table of the database schema, a view translation artifact describing a view of the database schema, and a procedure translation artifact describing a procedure of the database schema. A mapping service may receive from a client application a first client request comprising first metadata describing the view translation artifact. The mapping service may initiate execution of the view at an in-memory database to determine a view result; and send the view result to the client application.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: June 18, 2019
    Assignee: SAP SE
    Inventors: Apoorva Kumar, Suresh Pasumarthi, C Sachin
  • Patent number: 10282206
    Abstract: According to certain general aspects, the present embodiments allow register files and states with different data types to share logic area while minimizing unnecessary use of power in a configurable processor. Embodiments include allowing configurable processor designers to describe alias register files and states. Using alias register files and states, designers can implement vector and scalar operations on different register files, but the scalar register file can be implemented on the vector register file. In addition, the upper lanes of the vector register file can be clock gated when the scalar operation performs computations. With this gating, the clocks for the entire upper lanes (including the register file, state, semantic, mux, decoder) can be disabled, which provides power savings.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: May 7, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Fei Sun, Tiansi Hu
  • Patent number: 10268602
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Patent number: 10268479
    Abstract: Systems, apparatuses, and methods for executing an instruction. The instruction includes fields for a first source operand, a second source operand, and a destination operand. A decoded instruction causes a reduction of broadcasted packed data elements of a first packed data source with a reduction operation and store a result of each of the reductions in a packed data destination, wherein the packed data elements of the first packed data source to be used in the reduction are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source without broadcasting.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Mikhail Plotnikov, Jesus Corbal, Robert Valentine
  • Patent number: 10254819
    Abstract: A method for controlling a pipeline-based processor. The method includes determining a change in a workload. The method also includes activating or shutting down, by at least one controller circuit, one or more of the plurality of enhanced pipeline stages based on at least one corresponding enhanced stage priority level of the one or more of the plurality of enhanced pipeline stages and requirements for performance of the workload. The method additionally includes activating or shutting down, by the at least one controller circuit, one or more of the plurality of enhanced modules of the particular pipeline stage based on at least one corresponding priority level of the one or more of the plurality of enhanced modules of the particular pipeline stage and the requirements for the performance of the workload.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wen Bo Shen, Peng Shao, Yu Li, Xiao Tao Chang, Yi Ge, Hua Yong Wang, Huan Hao Zou
  • Patent number: 10223091
    Abstract: In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Carlo Bertolli, John K. O'Brien, Olivier H. Sallenave, Zehra N. Sura
  • Patent number: 10222944
    Abstract: A device may provide a user interface element for display in association with a displayed document that contains code. The user interface element may be associated with at least one adjustable state. The device may determine, based on a user interaction with the user interface element, a selected state of the at least one adjustable state of the user interface element. The device may generate information based on the selected state of the user interface element. The device may store the user interface element, the selected state of the user interface element, and the information in association with the document.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: March 5, 2019
    Assignee: The MathWorks, Inc.
    Inventors: Joseph F. Hicklin, Joseph R. Bienkowski, John W. Glass, Edward W. Gulley, Claudia G. Wey, Jeng-Tsung Tsai, Chen Su
  • Patent number: 10210094
    Abstract: It is provided an information processing system. A first processing unit instructs a second processing unit to update the state management information regarding first data managed by the second processing unit when the first processing unit accesses the first data and detects an error regarding the first data, the second processing unit issues a command for discarding the first data acquired by a processing unit other than the second processing unit to the processing unit other than the second processing unit, when the processing unit which acquires the first data receives the command, the processing unit which acquires the first data discards the first data and transmits a result of the discarding of the first data to the second processing unit, and the second processing unit updates the state management information regarding the first data based on the result received from the processing unit which acquires the first data.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Jin Takahashi, Seishi Okada
  • Patent number: 10192168
    Abstract: In some aspects, a quantum computing system includes a control system and a quantum processor cell. The control system generates quantum processor control information for a group of devices housed in the quantum processor cell, and each device in the group has a distinct operating frequency. In some cases, a waveform generator generates a multiplexed control signal based on the quantum processor control information, and the multiplexed control signal is communicated an input signal processing system. In some cases, the input signal processing system includes an input channel configured to receive the multiplexed control signal, a de-multiplexer configured to separate device control signals from the multiplexed control signal, and output channels configured to communicate the respective device control signals into the quantum processor cell.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: January 29, 2019
    Assignee: Rigetti & Co, Inc.
    Inventors: Chad Tyler Rigetti, Dane Christoffer Thompson
  • Patent number: 10169044
    Abstract: A method including fetching information regarding a group of instructions, where the group of instructions is configured to execute atomically by a processor, including an encoding format for the information regarding the group of instructions, is provided. The method further includes processing the encoding format to interpret the information regarding the group of instructions.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 1, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Doug Burger, Aaron Smith
  • Patent number: 10169041
    Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eyal Naor, Martin Recktenwald, Christian Zoellin, Aaron Tsai
  • Patent number: 10157060
    Abstract: Techniques and mechanisms for exchanging control signals in a data path module of a data stream processing engine. In an embodiment, the data path module may be configured to form a set of one or more data paths corresponding to an instruction which is to be executed. In another embodiment, data processing units of the data path module may be configured to exchange one or more control signals for elastic execution of the instruction.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventor: Vladimir Ivanov
  • Patent number: 10146823
    Abstract: A relevant-information providing method comprising in response to update of an application carried out in a system, storing, in a storage, difference information that is a difference between information on the application that has not been updated and information on the application that has been updated and modification information on management of the system modified as a result of the update, in response to acquisition of update information on a first application, extracting, from the stored difference information, a piece of difference information that is in a predetermined similarity relation with first difference information that is a difference between information on the first application that has not been updated and information on the first application that has been updated, and outputting a piece of the modification information corresponding to the piece of difference information that has been extracted.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: December 4, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Kitajima, Yasuhide Matsumoto
  • Patent number: 10120822
    Abstract: Aspects include acquiring measurement data of a synchronous input/output (I/O) link between an operating system and a recipient. The acquiring measurement data can include monitoring operating system usage of synchronous I/O commands on the synchronous I/O link and storing the operating system usage in a measurement block as the measurement data. Further, the measurement block is accessible by the operating system to determine that the measurement data is acquired.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Beth A. Glendening, Dale F. Riedy, Peter G. Sutton, Harry M. Yudenfriend