Vector Processor Patents (Class 712/2)
  • Patent number: 10318353
    Abstract: An architecture for a load-balanced groups of multi-stage manycore processors shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 11, 2019
    Inventor: Mark Henrik Sandstrom
  • Patent number: 10303473
    Abstract: A vector permutation circuit and a vector processor are provided. The vector permutation circuit includes a grouping unit, m selection units connected to the grouping unit, j switching units connected to the m selection units, and a control unit connected to each selection unit and each switching unit, where each switching unit is connected to m/j selection units; the grouping unit divides to-be-permutated vector data into n vector data groups and output the n vector data groups to the m selection units; under control of the control unit, each selection unit selects a second vector data group from an input first vector data group, and outputs the second vector data group to a switching unit connected to the selection unit; under control of the control unit, each switching unit switches and outputs elements in the input second vector data group.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 28, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD
    Inventors: Yunbi Chen, Kai Hu
  • Patent number: 10261789
    Abstract: A data processing apparatus and a method of controlling performance of speculative vector operations are provided. The apparatus comprises processing circuitry for performing a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements, and speculation control circuitry for maintaining a speculation width indication indicating the number of vector elements of each vector operand to be subjected to the speculative vector operations. The speculation width indication is set to an initial value prior to performance of the sequence of speculative vector operations. The processing circuitry generates progress indications during performance of the sequence of speculative vector operations, and the speculation control circuitry detects, with reference to the progress indications and speculation reduction criteria, presence of a speculation reduction condition.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: April 16, 2019
    Assignee: ARM Limited
    Inventors: Alastair David Reid, Daniel Kershaw
  • Patent number: 10228941
    Abstract: A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Bret L. Toll, Ronak Singhal, Buford M. Guy, Mishali Naik
  • Patent number: 10135815
    Abstract: The present invention relates generally to the use of biometric technology for authentication and identification, and more particularly to non-contact based solutions for authenticating and identifying users, via computers, such as mobile devices, to selectively permit or deny access to various resources. In the present invention authentication and/or identification is performed using an image or a set of images of an individual's palm through a process involving the following key steps: (1) detecting the palm area using local classifiers; (2) extracting features from the region(s) of interest; and (3) computing the matching score against user models stored in a database, which can be augmented dynamically through a learning process.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: November 20, 2018
    Assignee: ELEMENT, INC.
    Inventors: Yann LeCun, Adam Perold, Yang Wang, Sagar Waghmare
  • Patent number: 10085302
    Abstract: An access node for a telecommunications network is partitioned into a front end unit and a back end unit coupled by an internet protocol (IP) packet based communication link to provide for data and control packets to be sent between the back end unit and the front end unit. The front end unit performs physical layer and media access layer (MAC) sublayer processing for data for transmission to/from user equipment in the network using baseband processing units that perform highly parallel floating/fixed point operations. The back end unit includes a plurality of general purpose processors to provide data link layer and network layer processing. back end portions may be pooled to provide greater efficiency.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 25, 2018
    Assignees: AT&T Mobility II LLC, AT&T Intellectual Property I, L.P.
    Inventors: Dimas R. Noriega, Arthur R. Brisebois, Giuseppe De Rosa, Henry J. Fowler, Jr.
  • Patent number: 9958917
    Abstract: Disclosed is a resettable memory device including a memory unit, a reset status indicator circuit, a logic sampling circuit, and a multiplexer for performing a reset function. The memory unit includes cells for storing states of signals in a design under test. The reset status indicator stores states of indicators indicating whether corresponding cells should be reset or not. Responsive to the reset status indicator indicating that the value of the cell should not be reset, the multiplexer receives the value stored in the cell and outputs the retrieved value from the cell. Responsive to the reset status indicator indicating that the value of the cell should be reset, the multiplexer outputs a reset value instead of the value stored in the cell. The reset value may be changed by the logic sampling circuit at different time periods or certain logic conditions, and output through the multiplexer.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: May 1, 2018
    Assignee: Synopsys, Inc.
    Inventors: Ngai Ngai William Hung, Dhiraj Goswami
  • Patent number: 9916130
    Abstract: An apparatus comprises processing circuitry for performing, in response to a vector instruction, a plurality of lanes of processing or respective data elements with at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry may support performing at least two of the lanes of processing with different rounding modes for generating rounding values for the corresponding result data elements of the result vector. This allows two or more calculations with different rounding modes to be executed in response to a single instruction, to improve performance.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: March 13, 2018
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess
  • Patent number: 9891914
    Abstract: An apparatus and method for performing an efficient scatter operation. For example, one embodiment of a processor comprises: an allocator unit to receive a scatter operation comprising a number of data elements and responsively allocate resources to execute the scatter operation; a memory execution cluster comprising at least a portion of the resources to execute the scatter operation, the resources including one or more store data buffers and one or more store address buffers; and a senior store pipeline to transfer store data elements from the store data buffers to system memory using addresses from the store address buffers prior to retirement of the scatter operation.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Ramon Matas, Alexey P. Suprun, Roger Gramunt, Chung-Lun Chan, Rammohan Padmanabhan
  • Patent number: 9887714
    Abstract: It is provided a remote radio head configured to provide a radio interface for a network node. The remote radio head comprising an antenna, an analog interface for connecting with the network node, radio frequency (RF) circuitry configured to convert between intermediate frequency signals of the analog interface and RF signals of the antenna, digital circuitry configured to process transmission and/or reception signals, a first analog to digital converter (ADC) connected to the digital circuitry, and a first digital to analog converter (DAC) connected to the digital circuitry. The first ADC, the digital circuitry, and the first DAC are connected between the antenna and the analog interface for receiving or transmitting radio signals. A corresponding method is also presented.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: February 6, 2018
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Marko E. Leinonen, Kauko Heinikoski
  • Patent number: 9886459
    Abstract: Methods and apparatuses for determining set-membership using Single Instruction Multiple Data (“SIMD”) architecture are presented herein. Specifically, methods and apparatuses are discussed for determining, in parallel, whether multiple values in a first set of values are members of a second set of values. Many of the methods and systems discussed herein are applied to determining whether one or more rows in a dictionary-encoded column of a database table satisfy one or more conditions based on the dictionary-encoded column. However, the methods and systems discussed herein may apply to many applications executed on a SIMD processor using set-membership tests.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: February 6, 2018
    Assignee: Oracle International Corporation
    Inventors: Shasank K. Chavan, Phumpong Watanaprakornkul
  • Patent number: 9798684
    Abstract: Methods and systems are described for reading from or writing to a plurality of slave devices connected to a communications bus having a common data line. The slave devices are mapped to a virtual device address and the communication is initiated by the master by signaling a start condition and the virtual device address. Each of the slave devices mapped to the virtual device address identifies a register in that slave device associated with the virtual device address and, in sequence, performs a read or write operation on the bus with regard to its identified register in a respective predetermined time slot within the communication or to a corresponding virtual register address assigned to the slave device previously.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: October 24, 2017
    Assignee: BLACKBERRY LIMITED
    Inventor: Jens Kristian Poulsen
  • Patent number: 9792118
    Abstract: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption are disclosed. Related vector processor systems and methods are also disclosed. The VPEs are configured to provide filter vector processing operations. To minimize re-fetching of input vector data samples from memory to reduce power consumption, a tapped-delay line(s) is included in the data flow paths between a vector data file and execution units in the VPE. The tapped-delay line(s) is configured to receive and provide input vector data sample sets to execution units for performing filter vector processing operations. The tapped-delay line(s) is also configured to shift the input vector data sample set for filter delay taps and provide the shifted input vector data sample set to execution units, so the shifted input vector data sample set does not have to be re-fetched during filter vector processing operations.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 17, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Raheel Khan, Fahad Ali Mujahid, Afshin Shiravi
  • Patent number: 9769873
    Abstract: An access node for a telecommunications network is partitioned into a front end unit and a back end unit coupled by an internet protocol (IP) packet based communication link to provide for data and control packets to be sent between the back end unit and the front end unit. The front end unit performs physical layer and media access layer (MAC) sublayer processing for data for transmission to/from user equipment in the network using baseband processing units that perform highly parallel floating/fixed point operations. The back end unit includes a plurality of general purpose processors to provide data link layer and network layer processing. back end portions may be pooled to provide greater efficiency.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: September 19, 2017
    Assignees: AT&T Intellectual Property I, L.P., AT&T Mobility II LLC
    Inventors: Dimas R. Noriega, Arthur R. Brisebois, Giuseppe De Rosa, Henry J. Fowler, Jr.
  • Patent number: 9753765
    Abstract: An integrated circuit unit and method for synchronizing processing threads running on respective processors are provided. The unit includes an interrupt request controller which is programmable to provide a first desired number of synchronization objects and a second desired number of interrupt request signals for supply to such processors. The controller is operable to direct and interrupt request signals to a chosen processor in dependence upon data received from the processors.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: September 5, 2017
    Assignee: Altera Corporation
    Inventor: Robert Jackson
  • Patent number: 9727526
    Abstract: A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: August 8, 2017
    Assignee: NXP USA, Inc.
    Inventors: Malcolm Stewart, Ali Osman Ors, Daniel Laroche
  • Patent number: 9665360
    Abstract: A computer implemented method for updating configuration data in at least one automated banking machine is configured to execute configuration update steps embodied with a computer readable medium. The method includes identifying one or more sub-systems implemented within the automated banking machine, receiving an update to configuration data for at least one of the identified sub-systems, generating a restore point based on a current implementation of the sub-systems for the automated banking machine, and installing the configuration data in the automated banking machine. The identified sub-systems can include at least two of roll storage modules, a note handling module controller, a note detector module, and an interface controller.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: May 30, 2017
    Assignee: Glory Global Solutions (International) Limited
    Inventors: Dominik Cipa, Gunnar Kunz, Ulrich Marti, Olivier Martin
  • Patent number: 9639354
    Abstract: A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Seth Abraham, Robert Valentine, Elmoustapha Ould-Ahmed-Vall, Zeev Sperber, Amit Gradstein
  • Patent number: 9632781
    Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Ajay A. Ingle, Marc M. Hoffman, Jose Fridman, Lucian Codrescu
  • Patent number: 9477475
    Abstract: According to embodiments disclosed herein, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embodiment, the computer processor includes: (1) a decode unit for decoding instruction packets fetched from a memory holding the instruction packets, (2) a control processing channel capable of performing control operations and (3) a data processing channel capable of performing data processing operations, wherein, in use the decode unit causes instructions of instruction packets comprising a plurality of only control instructions to be executed sequentially on the control processing channel, and wherein, in use the decode unit causes instructions of instruction packets comprising a plurality of instructions comprising at least one data processing instruction to be executed simultaneously on the data processing channel.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: October 25, 2016
    Assignee: Nvidia Technology UK Limited
    Inventor: Simon Knowles
  • Patent number: 9448847
    Abstract: An architecture for a load-balanced groups of multi-stage manycore processors shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: September 20, 2016
    Assignee: THROUGHPUTER, INC.
    Inventor: Mark Henrik Sandstrom
  • Patent number: 9405546
    Abstract: An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor may include at least one functional unit (FU) to execute the at least one operation, and the at least one FU may process the transferred input data using at least one of a regular latency operation and an irregular latency operation.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: August 2, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwon Taek Kwon, Sang Oak Woo, Shi Hwa Lee, Seok Yoon Jung
  • Patent number: 9319254
    Abstract: The present method and system enables receiving a radio frequency (RF) signal. The received RF signal is assigned to a single instruction multiple data (SIMD) module in an accelerated processing device (APD) for processing to extract network messages. The extracted network layer messages are further processed by the SIMD module to obtain data transmitted via the RF signal.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: April 19, 2016
    Assignee: ATI Technologies ULC
    Inventor: Moiz Haq
  • Patent number: 9038073
    Abstract: Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: May 19, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Mathias Kohlenz, Irfan Anwar Khan, Sathyanarayan Madhusudan, Shailesh Maheshwari, Srividhya Krishnamoorthy, Sandeep Urgaonkar, Thomas Klingenbrunn, Tim Tynghuei Liou, Idreas Mir
  • Patent number: 9009528
    Abstract: The described embodiments include a processor that handles faults. The processor first receives an input vector, a control vector, and a predicate vector, each vector comprising a plurality of elements. Then, for a first element of the input vector for which corresponding elements of the control vector and the predicate vector are active, the processor performs a scalar read operation using an address from the element of the input vector. When a fault condition is encountered while performing the read operation, the processor determines if the element is a first element where a corresponding element of the control vector is active. If so (i.e., if the element is a first element where a corresponding element of the control vector is active), the processor processes the fault. Otherwise, the processor masks the fault for the element.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: April 14, 2015
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Publication number: 20150052330
    Abstract: In a particular embodiment, a method includes executing a vector instruction at a processor. The vector instruction includes a vector input that includes a plurality of elements. Executing the vector instruction includes providing a first element of the plurality of elements as a first output. Executing the vector instruction further includes performing an arithmetic operation on the first element and a second element of the plurality of elements to provide a second output. Executing the vector instruction further includes storing the first output and the second output in an output vector.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 19, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Ajay Anant Ingle, Marc Murray Hoffman, Deepak Mathew, Mao Zeng
  • Patent number: 8938642
    Abstract: The described embodiments include a processor with a fault status register (FSR) that executes a Confirm instruction. In these embodiments, when executing the Confirm instruction, the processor receives a predicate vector that includes N elements. For a first set of bit positions in the FSR for which corresponding elements of the predicate vector are active, the processor determines if at least one of the first set of bit positions in the FSR holds a predetermined value. When at least one of the first set of bit positions in the FSR holds the predetermined value, the processor causes a fault in the processor.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 20, 2015
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Patent number: 8935468
    Abstract: A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation loads one of the data values into a first register, and moves at least a remainder of the current contents of the memory interface into the buffer for use in a successive invocation. Another instruction loads a reversed representation of a set of data values obtained via the memory interface into a second register. Another instruction implements an FIR computation including a SIMD operation involving multiple data values of the stream and the reversed representation.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: January 13, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dror E. Maydan, William A. Huffman, Sachin Ghanekar, Fei Sun
  • Patent number: 8918553
    Abstract: A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian K. Flachs, Harm P. Hofstee, Charles R. Johns, Matthew E. King, John S. Liberty, Brad W. Michael
  • Patent number: 8862932
    Abstract: The described embodiments include a processor that handles faults. The processor first receives a first input vector, a control vector, and a predicate vector, each vector comprising a plurality of elements. For each element in the first input vector for which a corresponding element in the control vector and the predicate vector are active, the processor then performs a read operation using an address from the element of the first input vector. When a fault condition is encountered while performing the read operation, the processor determines if the element is a first element where a corresponding element of the control vector is active. If so, the processor handles/processes the fault. Otherwise, the processor masks the fault for the element.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: October 14, 2014
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Publication number: 20140189287
    Abstract: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Inventors: Mikhail Plotnikov, Andrey Naraikin, Elmoustapha Ould-Ahmed-Vall
  • Publication number: 20140122831
    Abstract: Instructions and logic provide vector compress and rotate functionality. Some embodiments, responsive to an instruction specifying: a vector source, a mask, a vector destination and destination offset, read the mask, and copy corresponding unmasked vector elements from the vector source to adjacent sequential locations in the vector destination, starting at the vector destination offset location. In some embodiments, the unmasked vector elements from the vector source are copied to adjacent sequential element locations modulo the total number of element locations in the vector destination. In some alternative embodiments, copying stops whenever the vector destination is full, and upon copying an unmasked vector element from the vector source to an adjacent sequential element location in the vector destination, the value of a corresponding field in the mask is changed to a masked value. Alternative embodiments zero elements of the vector destination, in which no element from the vector source is copied.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Inventors: Tal Uliel, Elmoustapha Ould-Ahmed-Vall, Robert Valentine
  • Patent number: 8687008
    Abstract: A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: April 1, 2014
    Assignee: NVIDIA Corporation
    Inventors: Ashish Karandikar, Shirish Gadre, Stephen D. Lew
  • Patent number: 8682631
    Abstract: A design specifications-driven platform (100) for analog, mixed-signal and radio frequency verification with one embodiment comprising a client (160) and server (150) is presented. The server comprises an analog verification database (110), a code and document generator (1020), a design to specifications consistency checker (103), a symbol generator (104), a coverage analyzer (105), a server interface (106), a web server (111), and an analog verification server application (101). The client comprises a web browser (130), generated datasheets and reports (120), generated models, regression tests, netlists, connect modules, and symbols (121), generated simulation scripts (122), a client interface (124), design data (131), simulators (132), and a design data extractor (123).
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: March 25, 2014
    Inventors: Henry Chung-herng Chang, Kenneth Scott Kundert
  • Patent number: 8683178
    Abstract: The described embodiments provide a processor that executes vector instructions. In the described embodiments, the processor initializes an architectural fault-status register (FSR) and a shadow copy of the architectural FSR by setting each of N bit positions in the architectural FSR and the shadow copy of the architectural FSR to a first predetermined value. The processor then executes a first first-faulting or non-faulting (FF/NF) vector instruction. While executing the first vector instruction, the processor also executes one or more subsequent FF/NF instructions. In these embodiments, when executing the first vector instruction and the subsequent vector instructions, the processor updates one or more bit positions in the shadow copy of the architectural FSR to a second predetermined value upon encountering a fault condition.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: March 25, 2014
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Patent number: 8650382
    Abstract: A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 11, 2014
    Assignee: Intel Corporation
    Inventor: Patrice Roussel
  • Patent number: 8649508
    Abstract: A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further on using it to determine Elliptic curve scalar multiplication over a finite elliptic curve.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: February 11, 2014
    Assignee: Tata Consultancy Services Ltd.
    Inventor: Natarajan Vijayarangan
  • Patent number: 8578209
    Abstract: The described embodiments include a processor that handles faults during execution of a vector instruction. The processor starts by receiving a vector instruction that uses at least one vector of values that includes N elements as an input. In addition, the processor optionally receives a predicate vector that includes N elements. The processor then executes the vector instruction. In the described embodiments, when executing the vector instruction, if the predicate vector is received, for each element in the vector of values for which a corresponding element in the predicate vector is active, otherwise, for each element in the vector of values, the processor performs an operation for the vector instruction for the element in the vector of values. While performing the operation, the processor conditionally masks faults encountered (i.e., faults caused by an illegal operation).
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: November 5, 2013
    Assignee: Apple Inc.
    Inventors: Jeffry E. Gonion, Keith E. Diefendorff
  • Patent number: 8554421
    Abstract: A vehicle having a dynamics control system, the vehicle comprising: a first set comprising multiple adjustable sub-systems that affect the performance of the vehicle's powertrain; a second set comprising multiple adjustable sub-systems that affect the vehicle's handling; a dynamics user interface including a first input device and a second input device; and a dynamics controller coupled to the user interface and configured to adjust the operation of the sub-systems of the first set in dependence on the first input device and to adjust the operation of the sub-systems of the second set in dependence on the second input device.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: October 8, 2013
    Assignee: McLaren Automotive Limited
    Inventors: Antony Sheriff, Mark Vinnels, Richard Felton
  • Patent number: 8539200
    Abstract: A system, method, and computer readable medium for an operating system (OS) mediated launch of an OS dependent application is disclosed. An application running within an OS may operate outside an OS environment by constructing for example a capsule file, passing the capsule file to firmware interface, and restarting the system. The firmware interface may load various drivers and applications contained within the capsule file and execute them to perform a task. Upon completion of the task, the OS is booted again and the original application may resume control, making use of any information stored by the firmware interface in a dedicated status table or file. Other embodiments may be employed, and other embodiments are described and claimed.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: September 17, 2013
    Assignee: Intel Corporation
    Inventors: David H. Huang, Xin Li, Ruth Li, Vincent J. Zimmer
  • Publication number: 20130232317
    Abstract: A vector processing apparatus includes a storage pointer generation unit and an instruction execution unit including a plurality of vector pipeline units. The storage pointer generation unit receives the vector instruction and range information thereof and generates the storage pointer value. When receiving a succeeding vector instruction being able to be processed in parallel together with a preceding vector instruction, the storage pointer generation unit updates the storage pointer value based on the range information so as to input each element of the succeeding vector instruction into a vector pipeline unit that is unused by the preceding vector instruction, and the instruction execution unit processes in parallel the preceding vector instruction and the succeeding vector instruction according to the storage pointer value.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 5, 2013
    Inventor: Masao YASUDA
  • Publication number: 20130024651
    Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an operand vector, a selection vector, and a control vector are disclosed. The executed instructions may also cause the processor to perform a wrapping rotate previous operation dependent upon the input vectors.
    Type: Application
    Filed: September 28, 2012
    Publication date: January 24, 2013
    Applicant: APPLE INC.
    Inventor: Apple Inc.
  • Patent number: 8356159
    Abstract: The described embodiments provide a system that sets elements in a result vector based on an input vector. During operation, the system determines a location of a key element within the input vector. Next, the system generates a result vector. When generating the result vector, the system sets one or more elements of the result vector based on the location of the key element in the input vector.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: January 15, 2013
    Assignee: Apple Inc.
    Inventors: Jeffry E. Gonion, Keith E. Diefendorff, Jr.
  • Patent number: 8271832
    Abstract: The described embodiments include a processor that handles faults during execution of a vector instruction. The processor starts by receiving a vector instruction that uses at least one vector of values that includes N elements as an input. In addition, the processor optionally receives a predicate vector that includes N elements. The processor then executes the vector instruction. In the described embodiments, when executing the vector instruction, if the predicate vector is received, for each element in the vector of values for which a corresponding element in the predicate vector is active, otherwise, for each element in the vector of values, the processor performs an operation for the vector instruction for the element in the vector of values. While performing the operation, the processor conditionally masks faults encountered (i.e., faults caused by an illegal operation).
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: September 18, 2012
    Assignee: Apple Inc.
    Inventors: Jeffry E. Gonion, Keith E. Diefendorff
  • Patent number: 8261085
    Abstract: According to some implementations methods, apparatus and systems are provided involving the use of processors having at least one core with a security component, the security component adapted to read and verify data within data blocks stored in a L1 instruction cache memory and to allow the execution of data block instructions in the core only upon the instructions being verified by the use of a cryptographic algorithm.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: September 4, 2012
    Assignee: Media Patents, S.L.
    Inventor: Álvaro Fernández Gutiérrez
  • Patent number: 8253750
    Abstract: Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: August 28, 2012
    Assignee: NVIDIA Corporation
    Inventors: Jen-Hsun Huang, Gerrit A. Slavenburg, Stephen D. Lew, John C. Schafer, Thomas F. Fox, Taner E. Ozcelik
  • Patent number: 8243083
    Abstract: A system, method, and computer program product are provided for converting a scan algorithm to a segmented scan algorithm in an operator independent manner. In operation, a scan algorithm and a limit index data structure are identified. Utilizing the limit index data structure, the scan algorithm is converted to a segmented scan algorithm in an operator-independent manner. Additionally, the segmented scan algorithm is performed to produce an output.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: August 14, 2012
    Assignee: NVIDIA Corporation
    Inventors: Michael J. Garland, Shubhabrata Sengupta
  • Patent number: 8234416
    Abstract: An apparatus configured to couple to a universal serial bus (USB) 3.0 connector. The apparatus includes a management controller configured to couple to the USB 3.0 connector. The management controller is configured to detect from behavior on the D+ and D? pins of the USB 3.0 connector whether a device plugged into the USB 3.0 connector is a conventional USB 3.0 device or an optical USB device, where the optical USB device employs one of the D+ and D? pins of the USB 3.0 connector to transmit a data signal and the other to transmit a clock signal.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: July 31, 2012
    Assignee: VIA Technologies, Inc.
    Inventor: Jiin Lai
  • Patent number: 8209525
    Abstract: The described embodiments provide a system that executes program code. While executing program code, the processor encounters at least one vector instruction and at least one vector-control instruction. The vector instruction includes a set of elements, wherein each element is used to perform an operation for a corresponding iteration of a loop in the program code. The vector-control instruction identifies elements in the vector instruction that may be operated on in parallel without causing an error due to a runtime data dependency between the iterations of the loop. The processor then executes the loop by repeatedly executing the vector-control instruction to identify a next group of elements that can be operated on in the vector instruction and selectively executing the vector instruction to perform the operation for the next group of elements in the vector instruction, until the operation has been performed for all elements of the vector instruction.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: June 26, 2012
    Assignee: Apple Inc.
    Inventors: Jeffry E. Gonion, Keith E. Diefendorff, Jr.
  • Patent number: 8203567
    Abstract: A graphics processing method and apparatus described herein is capable of converting graphics processing of a window system into a vector-based application program interface (API) format usable in the GPU and performing the converted graphics processing in the GPU. For example, the vector-based API may be based on an OpenVG standard or an EGL standard.
    Type: Grant
    Filed: July 3, 2009
    Date of Patent: June 19, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kyun Jeong, Soo-chan Lim, Na-min Kim